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Traffic Light IntersectionVersion 9.50.11
Jenniffer EstradaEE365: Advanced Digital Design
Prof. KhondkerDecember 4, 2008
Executive SummaryA traffic intersection is simulated on the DE1 board, using a button press, KEY0, for a
pedestrian wanting to cross, a switch, SW0, to simulate a car waiting at the low priority street. Unless there is a pedestrian or a car in the low priority street, the green light will be set for the high priority street. Key1 is used to return the system to the initial default state, and 3 red and 3 green LEDs as well as three 7 segment displays are used to display the output of the system.
Problem DescriptionThe traffic light control system will be implemented in a two street intersection that allows
pedestrians to cross on request. A cross-walk button, KEY 0, can be used to halt all traffic to allow pedestrians to cross. Each traffic signal uses at two LED’s (green and red) per traffic light or the pedestrian crossing point, one of the two streets has a priority over the other. For the high priority street, the traffic signal will always remain green until the low priority street car sensor has been tripped or a pedestrian has pressed a crosswalk button. The occurrence of such an event gives the high priority street 5 seconds before the light changes to red. Switch, SW0, to simulate a car sensor at the low priority street and a button KEY0 to simulate the crosswalk request button for pedestrian use. Multiple button presses would be treated as a single press until the pedestrian gets a WALK (green) signal. The duration of the green light for the low priority street and the pedestrian crossing is 9 and 4 seconds, respectively. The system utilizes a second button, KEY1, to reset the circuit, at which the seven segment displays are set to their default values (5, 9, and 4) and the highest priority street becomes a green light. At no time should there ever be more than one green light in the system. Each traffic or pedestrian crossing light of this system will use seven segment displays that will display the number of seconds left that the light will remain green. When any of these seven segment displays reach zero they should reset to the default value (5, 9 and 4) and await the next countdown.
Design Problem Statement
The Traffic Light system defaults to having the high priority street having the green light unless the low priority street or the pedestrian are triggered. When this happens, the high priority street HEX2 will count down to zero, and the pedestrian or the low priority street will count down from 4 and 9 seconds, respectively.
Problem Decomposition
Clock
Enable
Input
Output
Clock
Enable
Input
Output
Clock Enable
Clock Enable
Clock
EffClock
crosswalktraffic
lowpriortraffic
reset
HIP
HiDone
LOWP
LowDone
PED
PedDone
HiCount[3..0]
LowCount[3..0]
PedCount[3..0]
BitInput[3..0] HexOutput[6..0]
BitInput[3..0] HexOutput[6..0]
BitInput[3..0] HexOutput[6..0]
Edge_Detect:PedCross
Edge_Detect:Rst
TrafficControl:ControlIntersect
DecodeHex:Pedestrian
DecodeHex:LowPriority
DecodeHex:HighPriority
CLOCK_50
KEY[1..0]
SW[0..0]
HEX0[6..0]
HEX1[6..0]
HEX2[6..0]HEX3[6..0]7' h7F --
LEDR[2..0]
LEDG[2..0]
ClockCounter:OneSec
ClockCounter:OneMilliSec
Figure.1. Main Entity TrafficLightIntersection RTL view
D
ENA
QPRE
CLR
D
ENA
QPRE
CLR
D
ENA
QPRE
CLR
D
ENA
QPRE
CLR
D
ENA
QPRE
CLR
D QPRE
ENA
CLR
D
ENA
QPRE
CLR
D
ENA
QPRE
CLR
D
ENA
QPRE
CLR
D QPRE
ENA
CLR
SELDATAA
DATABOUT0
MUX21
0
1
clk
crosswalktraffic
Go2Ped
lowpriortraffic
reset
countdown4[3..0]
countdown5[3..0]
countdown9[3..0]
HighPrior
LowPrior
Pedestrian
COUNT5_Ped
COUNT5_Low
L2Ped
D
ENA
QPRE
CLR
D QPRE
ENA
CLR
0
11
SEL
DATAA
DATAB
OUT0
MUX21
+A[4..0]
B[4..0]
ADDER
=A[4..0]
B[4..0]
EQUAL
DENA
PRE
CLR
Q
0
110
11
SEL[1..0]
DATA[1..0]
OUT
SELECTOR
DENA
PRE
CLR
Q
SEL[5..0]
DATA[5..0]
OUT
SELECTOR
SEL[5..0]
DATA[5..0]
OUT
SELECTOR
SEL[5..0]
DATA[5..0]
OUT
SELECTOR
DENA
PRE
CLR
Q
SEL[1..0]
DATA[1..0]
OUT
SELECTOR
DENA
PRE
CLR
Q
SEL[5..0]
DATA[5..0]
OUT
SELECTOR
+A[4..0]
B[4..0]
ADDER
SELDATAA
DATABOUT0
MUX21
=A[4..0]
B[4..0]
EQUAL
+A[4..0]
B[4..0]
ADDER
SELDATAA
DATABOUT0
MUX21
=A[4..0]
B[4..0]
EQUAL
WideOr5_OUT0
Go2Ped~1_OUT0
CurrentS_HighPrior
CurrentS_LowPrior
CurrentS_PedestrianCurrentS_COUNT5_PedCurrentS_COUNT5_Low
CurrentS_L2Ped
Works~0_OUT0
NextS~2_OUT0
Selector8_OUT
trip4~0_OUT0
0
countdown9[0]
EffClock
LowCount[3..0]
HiCount[3..0]
countdown4[2]
PedCount[3..0]
countdown4[3]
countdown5[2]
countdown4[1..0]
countdown5[3]
countdown5[0]
countdown9[3]
countdown9[2..1]
countdown9~[3..0]
4' h9 --count9Down~0
reset
trip9~5
crosswalktrafficGo2Ped~1
CurrentS
Clock
lowpriortraffic
LowDone
LOWP
PedDone
PED
register9
register[5..4]
Works~0
Works~1
trip9~3
Count5Down~0
NextS~2count4Down~0
trip9~4
trip5~[1..0]
2' h3 --
Add1
1' h1 - -
5' h1D --
Equal1
1' h0 - -
5' h00 --
Works~3
Works~2
Go2Ped
trip9~0
trip4~2
trip9~1
Selector9
1' h1 --
trip9
Selector10
1' h1 --
1' h1 --
Selector12
2' h3 --
trip9~6
trip4
trip5
Selector6
3' h7 --
Add0
1' h1 - -
5' h1D --
countdown5~[3..0]
4' h5 --
Equal0
1' h0 --
5' h00 --
Add2
1' h1 --
5' h1D --
countdown4~[3..0]
4' h4 --
Equal2
1' h0 - -
5' h00 --
Selector11
1' h1 --
NextS~6
Selector13
1' h1 - -
3' h7 - -
countdown5[1]
Figure.1. Traffic Control RTL view
+A[15..0]
B[15..0]
ADDER
D QPRE
ENA
CLR
D
ENA
QPRE
CLR
=A[15..0]
B[15..0]
EQUAL
SELDATAA
DATABOUT0
MUX21
count[15..0]Enable~reg0Equal0
16' hC34E --
count~[15..0]
16' h0000 --
Clock
Enable
Add0
16' h0001 --
Figure.2. Clock Counter RTL view
Instead of using a clock divider, a counter is used to count up to an arbitrary value, UpperBound, to create an enable signal. Since the Altera DE1 board has an internal 50 MHz clock, the counter will count up to 49999999 and 49999, to create a 1 second and 1 millisecond enable signal, respectively.
D
ENA
QPRE
CLR
D QPRE
ENA
CLR
OutSigOutSig~0Q[2..0]
ClockEnable
InputOutput
Figure.3. Edge Detect RTL
Edge Detect is used to prevent metastability within the circuit that may cause glitches. Both D Flip Flops are seeing the same clock and same enable signal.
SEL[3..0]
DATA[15..0]OUT
MUX
SEL[3..0]
DATA[15..0]OUT
MUX
SEL[3..0]
DATA[15..0]OUT
MUX
SEL[3..0]
DATA[15..0]OUT
MUX
SEL[3..0]
DATA[15..0]OUT
MUX
SEL[3..0]
DATA[15..0]OUT
MUX
SEL[3..0]
DATA[15..0]OUT
MUX
Mux2
16' h02BA --
Mux3
16' h8692 --
Mux4
16' hD004 --
Mux5
16' hD860 --
Mux6
16' h2812 --
HexOutput[6..0]
Mux0
16' h1083 --
BitInput[3..0]
Mux1
16' h208E --
Figure.4. Seven Segment Display Decoder RTL view
Seven Multiplexers are used to determine the correct output to the seven segment displays given by BitInput.
Significant Details of Design ProcessThe design is written to be modular for future use of components. The Top Level Entity,
TrafficLightIntersection, has four components, ClockCounter, Edge_Detect, TrafficControl and DecodeHex.
One instantiation of ClockCounter.vhd uses the 50Mhz clock from the DE1 board to count 50000000 pulses to synchronously enable TrafficControl at 1 second intervals and the other to count 50000 pulses to enable Edge_Detect at 1 millisecond intervals
Edge_Detect.vhd takes in an input from a key press and sends an enable signal to TrafficControl confirming that the button has been pressed and released. Edge_Detect runs at 1 millisecond to ensure that TrafficControl has the correct input in time.
TrafficControl.vhd controls all three states of the intersection. When initialized, the system is set to the default settings, with the green light on the high priority light, and the displays reading the default values, 5, 9, 4. When KEY0 is pressed or SW is toggled, the system will begin counting down the high priority light and give the green light to the pedestrian or the low priority light, respectively. The 7 segment displays will count down until the counter hits zero and will return to the default state and await another input. KEY1 is used to asynchronously reset the entire system to the default values.
DecodeHex.vhd takes the four bit binary vector and acts as a 4 to 7 Multiplexer, displaying the corresponding decimal number on the 7 segment display.
The top level entity, TrafficLightIntersection, uses structural architecture and instantiates the component DecodeHex three times and ClockCounter twice.
Alternative DesignsAn alternate design for this project is the extent of modularity for the component,
TrafficControl, could be explored further. Another change would be to make the states on the case statement into numbers, instead of words. Instead of having one giant file that does all the needed functions to control the intersection, many small counters and signals could be implemented to help aide with the extent of the project’s modularity.
Design Documentation
COUNTDOWN5Ped COUNTDOWN5Low LowPriority Pedestrian L2Pedreset
HighPriority
Figure.5. State Machine
Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;
ENTITY TrafficLightIntersection ISPORT (CLOCK_50: IN std_logic;
KEY : IN std_logic_vector(1 downto 0); SW : IN std_logic_vector(0 downto 0); HEX0 : OUT std_logic_vector(6 DOWNTO 0); HEX1 : OUT std_logic_vector(6 DOWNTO 0); HEX2 : OUT std_logic_vector(6 DOWNTO 0); HEX3 : OUT std_logic_vector(6 DOWNTO 0); LEDR : OUT std_logic_vector(2 DOWNTO 0); LEDG : OUT std_logic_vector(2 DOWNTO 0));
END TrafficLightIntersection;
ARCHITECTURE Behavior OF TrafficLightIntersection IS
COMPONENT DecodeHex ISPORT ( BitInput: IN std_logic_vector(3 DOWNTO 0);
HexOutput: OUT std_logic_vector(6 DOWNTO 0));END COMPONENT DecodeHex;
COMPONENT ClockCounter ISGENERIC (UpperBound: integer);PORT ( Clock: IN std_logic;
Enable: OUT std_logic);END COMPONENT ClockCounter;
component TrafficControl IS PORT ( EffClock: IN STD_LOGIC;
Clock : IN STD_LOGIC;crosswalktraffic: IN STD_LOGIC;lowpriortraffic: IN STD_LOGIC;reset : IN STD_LOGIC;HIP : OUT STD_LOGIC; LOWP : OUT STD_LOGIC;PED : OUT STD_LOGIC;HiDone : OUT STD_LOGIC;LowDone : OUT STD_LOGIC;PedDone : OUT STD_LOGIC; HiCount : OUT STD_LOGIC_VECTOR (3 downto 0);LowCount : OUT STD_LOGIC_VECTOR (3 downto 0);PedCount : OUT STD_LOGIC_VECTOR (3 downto 0));
END component TrafficControl;
COMPONENT Edge_Detect isPort( Clock: IN std_logic;
Enable: IN std_logic;
Input: IN std_logic;Output: OUT std_logic);
END COMPONENT Edge_Detect;
signal Enable1s : STD_LOGIC;signal Enable1ms : STD_LOGIC;signal PedXing : STD_LOGIC;signal reset : STD_LOGIC;signal HiCountsig : STD_LOGIC_VECTOR (3 downto 0);signal LowCountsig : STD_LOGIC_VECTOR (3 downto 0);signal PedCountsig : STD_LOGIC_VECTOR (3 downto 0);
begin
PedCross: Edge_Detect port map (Clock => CLOCK_50,Input => KEY(0),Enable => Enable1ms,Output=> PedXing);
Rst: Edge_Detect port map( Clock => CLOCK_50,Input => KEY(1),Enable => Enable1ms,Output => reset);
OneSec: ClockCounter Generic map ( UpperBound=>49999999)port map( Clock => CLOCK_50,
Enable => Enable1s);
OneMilliSec: ClockCounter Generic map(UpperBound=>49999)port map( Clock => CLOCK_50,
Enable => Enable1ms);
ControlIntersect: TrafficControl port map (EffClock => Enable1s,Clock => CLOCK_50,crosswalktraffic => PedXing,
lowpriortraffic => SW(0),reset => reset,HIP => LEDG(2), LOWP => LEDG(1),PED => LEDG(0),HiDone => LEDR(2),LowDone => LEDR(1),PedDone => LEDR(0), HiCount => HIcountsig,LowCount => LOWcountsig,PedCount => PEDcountsig);
Pedestrian: DecodeHex port map(BitInput => PEDcountsig,HexOutput => HEX0);
LowPriority: DecodeHex port map(BitInput => LOWcountsig,HexOutput => HEX1);
HighPriority: DecodeHex port map(BitInput => HIcountsig,HexOutput => HEX2);
HEX3 <= "1111111"; --Always off--
end Behavior;Figure.6. Top Level Entity VHDL Code
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
ENTITY ClockCounter ISGENERIC (UpperBound: integer);PORT ( Clock: IN std_logic;
Enable: OUT std_logic);END ClockCounter;
ARCHITECTURE behavior OF ClockCounter ISsignal count : integer range 0 to(UpperBound-1);BEGINPROCESS (Clock)
BEGINIF (rising_edge(Clock)) then
IF(count = (UpperBound-1)) thencount <= 0;Enable <= '1';
elsecount <= count+1;Enable <= '0';
end if;end if;
END PROCESS;END behavior;
Figure.7. Modular Clock Counter Component VHDL Code
library ieee;use ieee.std_logic_1164.all;
ENTITY DecodeHex ISPORT(
BitInput: IN std_logic_vector(3 downto 0);HexOutput: OUT std_logic_vector(6 downto 0));
END DecodeHex;
ARCHITECTURE Behavior OF DecodeHex IS
BEGINWITH BitInput SELECTHexOutput <= "1000000" WHEN "0000",
"1111001" WHEN "0001", "0100100" WHEN "0010", "0110000" WHEN "0011", "0011001" WHEN "0100", "0010010" WHEN "0101", "0000010" WHEN "0110", "1111000" WHEN "0111", "0000000" WHEN "1000", "0011000" WHEN "1001", "0001000" WHEN "1010", "0000011" WHEN "1011", "1000110" WHEN "1100", "0100001" WHEN "1101", "0000110" WHEN "1110", "0001110" WHEN "1111", "1111111" WHEN others;
END Behavior;
Figure.8. Modular 7 Segment Display Decoder VHDL Code
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
Entity Edge_Detect isPort( Clock: IN std_logic;
Input: IN std_logic;Output: OUT std_logic);
END Edge_Detect;
Architecture structural of Edge_Detect ISsignal Q1:std_logic;signal Q0:std_logic;
BeginProcess(Clock)BEGINif (rising_edge (Clock)) thenQ0<=not Input;Q1<=Q0;Output <= not(Q0) and (Q1);END IF;end process;end structural;
Figure.9. Modular Edge Detection VHDL File
Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;
Entity TrafficControl is PORT (EffClock: IN STD_LOGIC;
Clock : IN STD_LOGIC;crosswalktraffic : IN STD_LOGIC;lowpriortraffic : IN STD_LOGIC;reset : IN STD_LOGIC;HIP : OUT STD_LOGIC; LOWP : OUT STD_LOGIC;PED : OUT STD_LOGIC;HiDone : OUT STD_LOGIC;LowDone : OUT STD_LOGIC;PedDone : OUT STD_LOGIC; HiCount : OUT STD_LOGIC_VECTOR (3 downto 0);LowCount : OUT STD_LOGIC_VECTOR (3 downto 0);PedCount : OUT STD_LOGIC_VECTOR (3 downto 0));
end TrafficControl;
architecture Behavioral of TrafficControl is
type State is (HighPriority, LowPriority, Pedestrian, COUNTDOWN5Ped, COUNTDOWN5Low, L2Ped);
signal CurrentState , NextState : State;signal countdown9 : std_logic_vector (3 downto 0); signal countdown4 : std_logic_vector (3 downto 0); signal countdown5 : std_logic_vector (3 downto 0);
signal resetsig : std_logic; signal HiEnable : std_logic;
signal LowEnable : std_logic;signal PedEnable : std_logic;signal register5 : std_logic;signal register9 : std_logic;signal register4 : std_logic;signal trip5 : std_logic;signal trip9 : std_logic;signal trip4 : std_logic;signal Go2Ped : std_logic;
begin HiCount <= countdown5;LowCount <= countdown9;PedCount <= countdown4;resetsig <= reset;
Works : process (Go2Ped, reset, CurrentState, countdown4, countdown5, countdown9, NextState, crosswalktraffic, lowpriortraffic, Clock)begin
case CurrentState iswhen HighPriority =>
NextState <= CurrentState;HIP <= '1';
LOWP <= '0';PED <= '0';HiDone <= '0';LowDone <= '1';PedDone <= '1'; HIenable <= '0';LowEnable <= '0';PedEnable <= '0';trip5 <= '1';trip4 <= '1';trip9 <= '1';Go2Ped <= '0';if crosswalktraffic = '1' then
NextState <= COUNTDOWN5Ped;elsif lowpriortraffic = '1' then
NextState <= COUNTDOWN5Low;elsif reset = '1' then
NextState <= HighPriority;trip4 <='1';trip5 <='1';trip9 <='1';
end if;
when Pedestrian =>NextState <= CurrentState;HIP <= '0'; LOWP <= '0';PED <= '1';HiDone <= '1';LowDone <= '1';PedDone <= '0'; HIenable <= '0';LowEnable <= '0';PedEnable <= '1'; trip4 <= '0';Go2Ped <= '0';if countdown4 = 0 and lowpriortraffic = '1' then
NextState <= LowPriority;trip4 <= '1';
elsif countdown4 = 0 and lowpriortraffic = '0' thenNextState <= HighPriority;trip4 <= '1';
elsif reset = '1' thenNextState <= HighPriority;trip4 <='1';trip5 <='1';trip9 <='1';
end if;
when LowPriority =>NextState <= CurrentState;HIP <= '0'; LOWP <= '1';PED <= '0';HiDone <= '1';LowDone <= '0';
PEDdone <= '1'; HiEnable <= '0';LowEnable <= '1';PedEnable <= '0';trip9 <= '0';if countdown9 = 0 and Go2Ped = '0' then
NextState <= HighPriority;trip4 <='1';trip5 <='1';trip9 <='1';
elsif countdown9 = 0 and Go2Ped = '1' thenNextState <= L2Ped;trip4 <='1';trip5 <='1';trip9 <='1';
elsif crosswalktraffic = '1' thenGo2Ped <= '1';
elsif reset = '1' thenNextState <= HighPriority;trip4 <='1';trip5 <='1';trip9 <='1';
end if;
when COUNTDOWN5Ped =>NextState <= CurrentState;HIP <= '1'; LOWP <= '0';PED <= '0';HiDone <= '0';LowDone <= '1';PedDone <= '1'; HiEnable <= '1';LowEnable <= '0';PedEnable <= '0';trip5 <= '0';Go2Ped <= '0';if countdown5 = 0 then
NextState <= pedestrian;trip5 <= '1';
elsif reset = '1' thenNextState <= HighPriority;trip4 <='1';trip5 <='1';trip9 <='1';
end if;
when COUNTDOWN5low =>NextState <= CurrentState;HIP <= '1'; LOWP <= '0';PED <= '0';HiDone <= '0';LowDone <= '1';PedDone <= '1'; HiEnable <= '1';
LowEnable <= '0';PedEnable <= '0';trip5 <= '0';Go2Ped <= '0';if countdown5 = 0 then
NextState <= LowPriority;trip5 <='1';
elsif crosswalktraffic = '1' thenNextState <= COUNTDOWN5Ped;
elsif reset = '1' thenNextState <= HighPriority;trip4 <='1';trip5 <='1';trip9 <='1';
end if;
when L2Ped =>NextState <= CurrentState;HIP <= '1'; LOWP <= '0';PED <= '0';HiDone <= '0';LowDone <= '1';PedDone <= '1'; HiEnable <= '1';LowEnable <= '0';PedEnable <= '0';trip5<='0';if countdown5 = 0 then
NextState <= Pedestrian;trip5 <= '1';
elsif reset = '1' thenNextState <= HighPriority;trip4 <='1';trip5 <='1';trip9 <='1';
end if;end case;
end process;
CountDOWN5Down : process (EffClock, HiEnable, resetsig, countdown5, trip5)begin
if register5 = '1' or resetsig = '1' thencountdown5 <= "0101";
elsif (RISING_EDGE (EffClock)) and HiEnable = '1' THENif countdown5 = 0 then
countdown5 <= "0101";else
countdown5 <= countdown5 - 1; end if;
end if;end process;
count9Down : process (EffClock, LowEnable, resetsig, countdown9, trip9)begin
if register9 = '1' or resetsig = '1' then
countdown9 <= "1001";elsif (Rising_Edge(EffClock)) and LowEnable = '1' THEN
if countdown9 = 0 thencountdown9 <= "1001";
elsecountdown9 <= countdown9 - 1;
end if;end if;
end process; count4Down : process (EffClock, PedEnable, resetsig, countdown4, trip4)begin
if register4 = '1' or resetsig = '1' thencountdown4 <= "0100";elsif (rising_edge (EffClock)) and PedEnable = '1' THEN
if countdown4 = 0 thencountdown4 <= "0100";
elsecountdown4 <= countdown4 - 1;
end if;end if;
end process;
PROCESS(Clock)begin
IF Rising_Edge(Clock) THENCurrentState <= NextState;register5 <= trip5;register4 <= trip4;register9 <= trip9;
END IF;END PROCESS;
end Behavioral;Figure.10. ControlTraffic VHDL File
Performance Results and Analysis
Figure.11. Flow Summary of Compilation Report
The design implemented based on the specifications was successful. It is a possibility that the circuit might experience failure due to issues with timing and metastability from the asynchronous inputs and outputs.
