Example Snapshots From Some Of Example Snapshots From Some Of The Signal Integrity Interactive The Signal Integrity Interactive

Software ModulesSoftware Modules•The following slides highlight some of the The following slides highlight some of the output graphs/plots from the interactive Signal output graphs/plots from the interactive Signal Integrity softwareIntegrity software•The software is highly interactive and allows The software is highly interactive and allows the user to change many of the system the user to change many of the system variables in order to learn as much from the variables in order to learn as much from the software as possiblesoftware as possible

Module 1Module 1The Impact Of Propagation Delay And Drive Output Impedance OnThe Impact Of Propagation Delay And Drive Output Impedance On

Signal Integrity For High-Impedance LoadsSignal Integrity For High-Impedance Loads

Module 2Module 2Transmission Line Discontinuities With A Series Via And A SplitTransmission Line Discontinuities With A Series Via And A Split

Termination With A Capacitive LoadTermination With A Capacitive Load

Module 3Module 3Transmission Line Discontinuities With A Series Via, A Tapped Transmission Line Discontinuities With A Series Via, A Tapped

Transmission Line, And A Split Termination With A Capacitive LoadTransmission Line, And A Split Termination With A Capacitive Load

Module 4Module 4Transmission Line Equalization Using An RC Equalizer At The End Transmission Line Equalization Using An RC Equalizer At The End

Of The Line For Differential Transmission linesOf The Line For Differential Transmission lines

Module 5Module 5Near-End And Far-End CrosstalkNear-End And Far-End Crosstalk

Module 6Module 6Data-Dependent Timing Jitter Due To Closely Spaced TransmissionData-Dependent Timing Jitter Due To Closely Spaced Transmission

Lines Within A Data Bus And Their Variable ImpedancesLines Within A Data Bus And Their Variable Impedances

Module 7Module 7Pulse Transmission Through Optical FibersPulse Transmission Through Optical Fibers

Module 8Module 8Pre-emphasis And Its Impact On Signal Integrity For Very High Speed SignalsPre-emphasis And Its Impact On Signal Integrity For Very High Speed Signals

Module 10Module 10Pre-emphasis And RC Equalization For Very High-Speed SignalingPre-emphasis And RC Equalization For Very High-Speed Signaling

Module 11Module 11Data-Dependent Timing Jitter Due To Closely Spaced, Multidrop Broadcast Data BusesData-Dependent Timing Jitter Due To Closely Spaced, Multidrop Broadcast Data Buses

Module 12Module 12The Impact Of Signal Jumping From A Reference Ground Plane To A Different Reference Ground PlaneThe Impact Of Signal Jumping From A Reference Ground Plane To A Different Reference Ground Plane

Module 13Module 13The Impact Of Signal Jumping From A Reference Ground Plane To A Different Reference Ground PlaneThe Impact Of Signal Jumping From A Reference Ground Plane To A Different Reference Ground Plane

Module 14Module 14The Impact Of Signal Jumping From One Side Of A Ground Plane To The Other Side Of The Same The Impact Of Signal Jumping From One Side Of A Ground Plane To The Other Side Of The Same

Ground Plane On Signal IntegrityGround Plane On Signal Integrity

Module 15Module 15The Impact Of Signal Jumping From A Ground Plane To A Power Plane On Signal IntegrityThe Impact Of Signal Jumping From A Ground Plane To A Power Plane On Signal Integrity

Module 16Module 16The Impact Of Signal Jumping Between Multiple, Different Reference Planes On Signal IntegrityThe Impact Of Signal Jumping Between Multiple, Different Reference Planes On Signal Integrity

Module 20Module 20Groundbounce and PowerbounceGroundbounce and Powerbounce

Module 21Module 21Characteristic Impedances For Various Transmission Line StructuresCharacteristic Impedances For Various Transmission Line Structures

Example StriplineExample Stripline** Output Plots And Tabular Results Output Plots And Tabular Results

**Many other printed circuit board transmission Many other printed circuit board transmission line structures are discussed in this module.line structures are discussed in this module.

Module 22Module 22Transmission Line T-JunctionsTransmission Line T-Junctions

Module 23Module 23Routing A Signal Trace Over Rectangular Cutouts Within The Reference Plane Of The Return CurrentRouting A Signal Trace Over Rectangular Cutouts Within The Reference Plane Of The Return Current

These results are from a 0.04 inch tall and 0.04 inch wide rectangular cutout. The dimensions of the cutout, as well as the number of cutouts, can be changed in the software.

Module 24Module 24Coupled Microstriplines: Even And Odd Mode Signal PropagationCoupled Microstriplines: Even And Odd Mode Signal Propagation

How to interpret thesetables is described inthe software

Impedance surface plots are used to extract 3-dimensional information

Module 25Module 25Microstripline DispersionMicrostripline Dispersion

Module 26Module 26Microstripline LossesMicrostripline Losses

The softwaredescribes howto interpretthe surfaceplots.

Module 27Module 27Right Angle BendsRight Angle Bends

Module 28Module 28Steps in Microstripline Conductor WidthsSteps in Microstripline Conductor Widths

Time delays due to steps inthe conductor width, as wellas other considerations, areautomatically calculated inthe software.

Module 29Module 29Losses For Coplanar Strip Transmission LinesLosses For Coplanar Strip Transmission Lines

How to interpret these tables and surface plots is described in the software.

Module 30Module 30Far-End Crosstalk Design GuidelineFar-End Crosstalk Design Guideline

How to interpret the crosstalk plot is describedin the software, and is used to define a regionthat does not exceed a given percentage maximum crosstalk.

Module 31Module 31Far-End Crosstalk For Loosely Coupled and Tightly Coupled Differential Far-End Crosstalk For Loosely Coupled and Tightly Coupled Differential

MicrostriplinesMicrostriplines

Differentialcrosstalk results are displayed in tables and how to interpret these tables is described in the software.

Module 32Module 32Dielectric Losses For Coplanar (Differential) MicrostriplinesDielectric Losses For Coplanar (Differential) Microstriplines

Example Surface Plots Of Dielectric Loss

Dielectric Loss Tables For FrequenciesUp Through 10GHz For The Odd Mode

Similar loss tables are shown for even mode signal propagation up Similar loss tables are shown for even mode signal propagation up through 10GHz. Design tables showing the propagation delays, as well through 10GHz. Design tables showing the propagation delays, as well as characteristic impedances for even and odd mode signal propagation as characteristic impedances for even and odd mode signal propagation are generated in this module.are generated in this module.

Module 33Module 33Determining The Impact Of Termination Resistor Location On Signal IntegrityDetermining The Impact Of Termination Resistor Location On Signal Integrity

Example Input And Output Eye PatternsExample Input And Output Eye Patterns(Other Kinds Of Time-Domain Plots Are Generated In This Module)(Other Kinds Of Time-Domain Plots Are Generated In This Module)

Module 34Module 34The Impact Of Propagation Delay And Driver Output Impedances OnThe Impact Of Propagation Delay And Driver Output Impedances On

Signal Integrity For High-Impedance Loads And For TTL And CMOS DriversSignal Integrity For High-Impedance Loads And For TTL And CMOS Drivers

Input and Output Bit StreamsInput and Output Bit Streams

Input and Output Eye PatternsInput and Output Eye Patterns

Module 35Module 35Selecting Resistor Values For The Split Termination For A Capacitive Load Selecting Resistor Values For The Split Termination For A Capacitive Load

Graphical Analysis Results ShowGraphical Analysis Results ShowHow To Select The Resistance ValuesHow To Select The Resistance Values

Driver Clock Signal

Receiver 2 Clock Signal

Module 36Module 36Signal Integrity Of Low Impedance Clock Distribution LinesSignal Integrity Of Low Impedance Clock Distribution Lines

Module 37Module 37Parallel Clock Distribution NetworksParallel Clock Distribution Networks

Example Received Clock Signals

Clock Distribution Topology

Module 38Module 38Determining The Impact Of Load Termination Resistor Location On Signal IntegrityDetermining The Impact Of Load Termination Resistor Location On Signal Integrity

Example Pulse ResponsesExample Pulse Responses

Example Transmitted And ReceivedExample Transmitted And ReceivedBit StreamsBit Streams

Module 39Module 39Routing A Signal Over A Rectangular Cutout Within The Reference Plane Of The ReturnRouting A Signal Over A Rectangular Cutout Within The Reference Plane Of The Return

Current When A Stitching Capacitor Or A Nearby Reference Plane Is Available To SupportCurrent When A Stitching Capacitor Or A Nearby Reference Plane Is Available To SupportThe Return CurrentThe Return Current

Stitching Capacitor And Nearby Reference Plane

No Stitching Capacitor Or Nearby Reference Plane

2Gb/s2Gb/s

Example Output Eye Patterns GeneratedWith This Module