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Example of Scheduling and Allocation. based on Jaap Hofstede. IIR Filter. #define m1 … #define m2 … #define m3 … #define m4 … main() {float t, i1, o1, d1=0.0, d2=0.0; while (1) { in(i1); t = i1 + m3*d2 + m1*d1; o1 = t + m4*d2 + m2*d1; d2 = d1; d1 = t; out(o1); } }. - PowerPoint PPT Presentation
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Example of Scheduling and
Allocation
based on Jaap Hofstede
IIR Filter
#define m1 …#define m2 …#define m3 …#define m4 …
main(){ float t, i1, o1, d1=0.0, d2=0.0;
while (1) {in(i1);t = i1 + m3*d2 + m1*d1;o1 = t + m4*d2 + m2*d1;d2 = d1; d1 = t;out(o1);
}}
Specification in C
IIR Filter with 4 coefficients
Recursive circuitRecursive circuit
Draw data flowgraphDraw data flowgraph
Original dataflow graph
Memory elements
#define m1 …#define m2 …#define m3 …#define m4 …
main(){ float t, i1, o1, d1=0.0, d2=0.0;
while (1) {in(i1);t = i1 + m3*d2 + m1*d1;o1 = t + m4*d2 + m2*d1;d2 = d1; d1 = t;out(o1);
}}
tt
This is example of wide class of circuits called linear systems with applications in communication, image processing, radar, control, robotics, prediction etc . See 573 class
Please note the Please note the feedback loop in feedback loop in this circuitthis circuit
m1
+
+
+
+
i1
o1
D2
D1D2
D1
C8
C2
C7C1
C5C6C3C4
m3 m2 m4
ASAP (4 stages)
:=
Calculate multipliers and adders with students
ASAPASAP
Feedback not Feedback not shownshown
outputoutput
inputinput
m1 +
+
+
+
o1
D2
D1
C8
C2 C7
C1 C5C6
C3
C4
m3
m2 m4
ALAP (4stages)
D2
D1
:=
i1
Calculate multipliers and adders with students
ALAPALAP
m1 +
+
+
+
o1
D2
D1
C8
C2
C7
C1
C5
C6
C3
C4
m3
m2
m4
1 Adder, 1 multiplier (6 stages - tradeoff)D2
D1
:= ??in adder
i1 Calculate multipliers and adders with students
Move operatorsMove operators
m1
+
+
+
+
i1
o1
D2
D1
C8
C2
C7
C1
C5
C6
C3C3
C4C4
m3
m2
m4
1 Adder, 1 multiplier (6 stages)C1, C2 moved down D2
D1
:=
Move operatorsMove operators
m1
+
+
+
+
o1
D2
D1
C8
C2
C7
C1
C5
C6
C3
C4
m3
m2
m4
N2N1
N1N2
1 Adder, 1 multiplier (4 stages)loop pipelineloop pipeline D2
D1
:=
i1
Move operators, create pipeline, look at cMove operators, create pipeline, look at c33 c c44
1
2
3
4
m1
+
+
+
+
o1
D2
D1
C8
C2
C7
C1
C5
C6
C3
C4
m3
m2
m4
N2N1
N2
9 Registers Registers included
V1 V2
V6
V5V3
V7
V8 V9
D2
D1
:=
N1
V4
i1
Add pipeline registersAdd pipeline registers
v5 and v6 are compatible
1
2
There are many methods to add registers.
Here we take into account feedbacks that are not shown. We assume the same delay for add and mul. Separate logic blocks with one register
4321
V1
V3
V2
V4
V5
V6
V7
V8
V9
Analyze Lifetimes of registers Analyze Lifetimes of registers 9 Registers 9 Registers included included
v5 and v6 are compatible
Time steps
V1 created in time 1
V1 used in time 2 and not used after
V3 created in time 2
5 1+
8 7+ 2 6
9+
4+
3:=
Lifetime compatibility Lifetime compatibility graphgraph
(+ (+ := is := is source of datasource of data))
compatiblev5 and v6 are compatible
Find registers that Find registers that are compatible, are compatible, their cliquestheir cliques
We can prove from this graph that creating a clique 5,7,8 would not lead to smaller number of registers Ri
5 1
8 7 2 6
9
4
3R1 R2
R3
R5
R6
R4
Clique partitioning
R2 R6 R5 R4 R1 R3
+
O1
I1I1
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
R5 R4 R3R2 R1
R2R3
R5
R3
R1R1
R2 R5R4
m1m3
m2
m4
R5
R4
1,3 4 2 2 1,32,4
Correspondingnon-optimiseddata path
Numbers are time steps
Numbers are time steps
m1
+
+
+
+
o1
D2
D1
C8
C2
C7
C1
C5
C6
C3
C4
m3
m2
m4
N2N1
N2
V1 V2
V6
V5V3
V7
V8 V9
D2
D1
:=
N1
V4
i1
1
2
R2 R6 R5 R4 R1 R3
+
O1
I1I1
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
R5 R4 R3R2 R1
R2R3
R5
R3
R1R1
R2 R5R4
m1m3
m2
m4
R5
R4
1,3
4 2 2 1,3
2,4
Correspondingnon-optimiseddata path
m1
+
+
+
+
o1
D2
D1
C8
C2
C7
C1
C5
C6
C3
C4
m3
m2
m4
N2N1
N2
V1 V2
V6
V5V3
V7
V8 V9
D2
D1
:=
N1
V4
i1
Step 1
2Step 2
Step 3
Step 4
R2 R6 R5 R4 R1 R3
+
O1
I1 I1
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
R5 R4 R3R2 R1
R2R1
R5
R3
R1R3
R2 R5R4
m1m3
m2
m4
R5
R4
1,3 4 2 2 1,32,4
Multiplexers optimised by commutative property
R2 R6 R5 R4 R1 R3
+
O1
I1
1,3 2,4 1 2,3 4
1 2 3 4
1,4 2,3
R5 R4 R3R2 R1
R5
R3
R1R2
m1m3
m2
m4
R5
R4
1,3 4 2 2 1,32,4
I1
Size of multiplexers reduced
M1 M2 M3 M4
Design of Controller – stage 1
• All six registers have an enable input, enaRx.ena
• M1 and M4 have 1 control input, s:Mx.s
• M2 and M3 have 2 control inputs, s1 and s0:Mx.s1 and Mx.s0
• Controller has four states:State1, State2, State3, State4
Design of Controller – details
• All six registers have an enable input, enaRx.ena
• M1 and M4 have 1 control input, s:Mx.s
• M2 and M3 have 2 control inputs, s1 and s0:Mx.s1 and Mx.s0
• Controller has four states:State1, State2, State3, State4
R2 R6 R5 R4 R1 R3
+
O1
I1
1,3 2,4
1 2,3 4
1 2 3 4
1,4 2,3
R5R4 R3R2 R1
R5
R3
R1R2
m1
m3
m2 m
4
R5R4
1,3
4 2 2 1,3
2,4
I1
M1 M2 M3 M4
Design of Controller – stage 2
R1.ena = M1.s = M3.s0 = State2 + State4
R2.ena = R3.ena = State1 + State3
R4.ena = R5.ena = State2
R6.ena = M2.s1 = State4
M2.s0 = M4.s = State2 + State3
M3.s1 = State3 + State4
enable M1 M2 M3 M4State R1 R2 R3 R4 R5 R6 s s1 s0 s1 s0 s
1 0 1 1 0 0 0 0 0 0 0 0 02 1 0 0 1 1 0 1 0 1 0 1 13 0 1 1 0 0 0 0 0 1 1 0 14 1 0 0 0 0 1 1 1 0 1 1 0
Design of Controller – details
R2 R6 R5 R4 R1 R3
+
O1
I1
1,3 2,4 1 2,3 4 1 2 3 4 1,4 2,3
R5 R4 R3R2 R1
R5
R3
R1R2
m1
m3
m2 m
4
R5R4
1,3
4 2 2 1,3
2,4
I1
M1 M2 M3 M4
enable M1 M2 M3 M4State R1 R2 R3 R4 R5 R6 s s1 s0 s1 s0 s
1 0 1 1 0 0 0 0 0 0 0 0 02 1 0 0 1 1 0 1 0 1 0 1 13 0 1 1 0 0 0 0 0 1 1 0 14 1 0 0 0 0 1 1 1 0 1 1 0
• R1.ena = M1.s = M3.s0 = State2 + State4
• R2.ena = R3.ena = State1 + State3• R4.ena = R5.ena = State2• R6.ena = M2.s1 = State4• M2.s0 = M4.s = State2 + State3• M3.s1 = State3 + State4
Controls Controls of muxesof muxes
Design of Controller – stage 2
R1.ena = M1.s = M3.s0 = State2 + State4
R2.ena = R3.ena = State1 + State3
R4.ena = R5.ena = State2
R6.ena = M2.s1 = State4
M2.s0 = M4.s = State2 + State3
M3.s1 = State3 + State4
enable M1 M2 M3 M4State R1 R2 R3 R4 R5 R6 s s1 s0 s1 s0 s
1 0 1 1 0 0 0 0 0 0 0 0 02 1 0 0 1 1 0 1 0 1 0 1 13 0 1 1 0 0 0 0 0 1 1 0 14 1 0 0 0 0 1 1 1 0 1 1 0
