Example

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

• Speculative Dynamic Machine specification

• Issue rate of 1

• One broadcast per cycle for CDB

• branch takes 1 cycle,

• Load takes 1 cycle,

• integer alu takes 1 cycle,

• float add takes 2 cycle

• float multiply takes 3 cycle.

• These cycle count doesn’t include write to CDB

Entry Busy Instruction State Destination value

1 N

2 N

3 N

4 N

5 N

6 N

7 N

8 N

9 N

Reorder buffer

Name Busy OP Vj Vk Qj Qk Rob des

Add1 N

Add2 N

Add3 N

Mult1 N

Mult2 N

Int1 N

Int2 N

Int3 N

Reservation table

Field F0 f2

Reorder #

Busy n n

FP register status

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Cycle 0

Entry Busy Instruction State Destination value

1 Y Ld f0, 0(R1) issue f0 Mem(R1)

2 N

3 N

4 N

5 N

6 N

7 N

8 N

9 N

Reorder buffer

Name Busy OP Vj Vk Qj Qk Rob des

Add1 N

Add2 N

Add3 N

Mult1 N

Mult2 N

Int1 Y ld R1 #1

Int2 N

Int3 N

Reservation table

Field F0 f2

Reorder # #1

Busy Y n

FP register status

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Cycle 1

Entry Busy Instruction State Destination value

1 Y Ld f0, 0(R1) execute F0 Mem(R1)

2 Y Add.d f0 f0, f2 issue F0 #1+F2

3 N

4 N

5 N

6 N

7 N

8 N

9 N

Reorder buffer

Name Busy OP Vj Vk Qj Qk Rob des

Add1 Y addd f2 #1 #2

Add2 N

Add3 N

Mult1 N

Mult2 N

Int1 Y ld R1 #1

Int2 N

Int3 N

Reservation table

Field F0 f2

Reorder # #2

Busy Y N

FP register status

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Cycle 2

Entry Busy Instruction State Destination value

1 Y Ld f0, 0(R1) Write F0 Mem(R1)

2 Y Add.d f0 f0, f2 Excute F0 #1+F2

3 Y S.D 0(R1), F0 issue

4 N

5 N

6 N

7 N

8 N

9 N

Reorder buffer

Name Busy OP Vj Vk Qj Qk Rob des

Add1 Y addd f2 #1 #2

Add2 N

Add3 N

Mult1 N

Mult2 N

Int1 Y ld R1 #1

Int2 Y sd R1 #2

Int3 N

Reservation table

Field F0 f2

Reorder # #2

Busy Y N

FP register status

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Cycle 3

Entry Busy Instruction State Destination value

1 N Ld f0, 0(R1) commit F0 Mem(R1)

2 Y Add.d f0 f0, f2 Excute F0 #1+F2

3 Y S.D 0(R1), F0 Excute

4 Y L.D F0, 0(R2) Issue F0 Mem(R2)

5 N

6 N

7 N

8 N

9 N

Reorder buffer

Name Busy OP Vj Vk Qj Qk Rob des

Add1 Y addd f0 f2 #2

Add2 N

Add3 N

Mult1 N

Mult2 N

Int1 N ld R1 #1

Int2 Y sd R1 #2

Int3 Y ld R2 #4

Reservation table

Field F0 f2

Reorder # #4

Busy Y N

FP register status

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Cycle 4

Entry Busy Instruction State Destination value

1 N Ld f0, 0(R1) Commit F0 Mem(R1)

2 N Add.d f0 f0, f2 Commit F0 #1+F2

3 N S.D 0(R1), F0 Commit

4 N L.D F0, 0(R2) Commit F0 Mem(R2)

5 Y Mult.D F0, F0, F2 Write F0

6 Y S.D 0(R2), F0 execute

7 Y SUBI R1, R1, 8 Execute R1 R1+8

8 Y SUBI R2, R2, 8 execute R2 R2+8

9 Y Bnez r1, loop Issue

Reorder buffer

Name Busy OP Vj Vk Qj Qk Rob des

Add1 N

Add2 N

Add3 N

Mult1 Y Multd f0 f2 #5

Mult2 N

Int1 Y sd r2 #5 #6

Int2 Y Subi R1 #7

Int3 Y subi r2 #8

Reservation table

Field F0 f2

Reorder # #5

Busy Y N

FP register status

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Cycle n

Entry Busy Instruction State Destination value

1 N Ld f0, 0(R1) issue F0 Mem(R1)

2 N Add.d f0 f0, f2 Commit F0 #1+F2

3 N S.D 0(R1), F0 Commit

4 N L.D F0, 0(R2) Commit F0 Mem(R2)

5 N Mult.D F0, F0, F2 commit F0 F0*F2

6 Y S.D 0(R2), F0 execute

7 Y SUBI R1, R1, 8 write R1 R1+8

8 Y SUBI R2, R2, 8 execute R2 R2+8

9 Y Bnez r1, loop Issue

Reorder buffer

Name Busy OP Vj Vk Qj Qk Rob des

Add1 N

Add2 N

Add3 N

Mult1 N Multd f0 f2 #5

Mult2 N

Int1 Y sd r2 f0 #6

Int2 Y Subi R1 #7

Int3 Y subi r2 #8

Reservation table

Field F0 f2

Reorder #

Busy N N

FP register status

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Cycle n+1

Entry Busy Instruction State Destination value

1 Y Ld f0, 0(R1) issue F0 Mem(R1)

2 N Add.d f0 f0, f2 Commit F0 #1+F2

3 N S.D 0(R1), F0 Commit

4 N L.D F0, 0(R2) Commit F0 Mem(R2)

5 N Mult.D F0, F0, F2 commit F0 F0*F2

6 N S.D 0(R2), F0 commit

7 Y SUBI R1, R1, 8 Done write R1 R1+8

8 Y SUBI R2, R2, 8 write R2 R2+8

9 Y Bnez r1, loop Issue

Reorder buffer

Name Busy OP Vj Vk Qj Qk Rob des

Add1 N

Add2 N

Add3 N

Mult1 N Multd f0 f2 #5

Mult2 N

Int1 Y ld r1 #1

Int2 N Subi R1 #7

Int3 Y subi r2 #8

Reservation table

Field F0 f2

Reorder # #1

Busy Y N

FP register status

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Cycle n+2

Entry Busy Instruction State Destination value

1 Y Ld f0, 0(R1) issue F0 Mem(R1)

2 N Add.d f0 f0, f2 Commit F0 #1+F2

3 N S.D 0(R1), F0 Commit

4 N L.D F0, 0(R2) Commit F0 Mem(R2)

5 N Mult.D F0, F0, F2 commit F0 F0*F2

6 N S.D 0(R2), F0 commit

7 Y SUBI R1, R1, 8 Execute R1 R1+8

8 Y SUBI R2, R2, 8 execute R2 R2+8

9 Y Bnez r1, loop Issue

Reorder buffer

Name Busy OP Vj Vk Qj Qk Rob des

Add1 N

Add2 N

Add3 N

Mult1 N Multd f0 f2 #5

Mult2 N

Int1 Y ld r1 #1

Int2 Y Subi R1 #7

Int3 Y subi r2 #8

Reservation table

Field F0 f2

Reorder # #1

Busy Y N

FP register status

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R1, Loop

Cycle n+3

VLIW exampleLoop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

•Static machine specification

•One delay slot between any true data flow dependency

•One branch delay slot

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F0, 0(R2)

Mult.D F0, F0, F2

S.D 0(R2), F0

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F1, 0(R2)

Mult.D F1, F1, F2

S.D 0(R2), F1

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Register rename

Loop: L.D F0, 0(R1)

Add.D F0, F0, F2

S.D 0(R1), F0

L.D F1, 0(R2)

Mult.D F1, F1, F2

S.D 0(R2), F1

SUBI R1, R1, 8

SUBI R2, R2, 8

BNEZ R2, Loop

Instruction reorder

Loop: L.D F0, 0(R1)

L.D F1, 0(R2) Add.D F0, F0, F2

Mult.D F1, F1, F2

S.D 0(R1), F0

S.D 0(R2), F1

SUBI R2, R2, 8 BNEZ R2, Loop SUBI R1, R1, 8

Software pipeline

L.D F0, 0(R1)

L.D F1, 0(R2)

Add.D F0, F0, F2

Mult.D F1, F1, F2

S.D 0(R1), F0

S.D 0(R2), F1

SUBI R2, R2, 8

SUBI R1, R1, 8

BNEZ R2, Loop

L.D F0, 0(R1)

L.D F1, 0(R2)

Add.D F0, F0, F2

Mult.D F1, F1, F2

S.D 0(R1), F0

S.D 0(R2), F1

SUBI R2, R2, 8

SUBI R1, R1, 8

BNEZ R2, Loop

L.D F0, 0(R1)

L.D F1, 0(R2)

Add.D F0, F0, F2

Mult.D F1, F1, F2

S.D 0(R1), F0

S.D 0(R2), F1

SUBI R2, R2, 8

SUBI R1, R1, 8

BNEZ R2, Loop

8 copies

Code for one iteration.