EX1 - UPC Universitat Politècnica de Catalunyadigsys.upc.es/.../1011Q1/EX/EX1/EX1_10-11_Q1B.docx · Web viewIn this Section B of EX1, ... follow its design flow to implement a

EX1 Section B: Logic functions and combinational circuits

EX 1 DIGITAL CIRCUITS AND SYSTEMS

Section B: Logic functions and combinational circuits

1.1 Cooperative groupTEAM NUMBER: ___________

DUE DATE: ________________ 1st review due date: ________________

STUDY TIME:

Study time

(in hours)

Group work Classroom and laboratory sessions

Sessions out of classroom

Individual Student 1

Student 2

Student 3

STATEMENT:

My signature below indicates that I have (1) made equitable contribution to EX 1 as a member of the group, (2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in the completion of this document.

Today’s date: __________________

Active members Roles: (reporter, simulator, etc.)

(1) ________________________________________ _______________

(2) _________________________________________ _______________

(3) _________________________________________ _______________

Acknowledgement of individual(s) who assisted this group in completing this document:

1

EPSC – Digital Circuits and Systems CSD

(1) _______________________

(2) _______________________

1.2 Abstract Explain here the most significant developments, results or conclusions about the exercise. Use the remaining space in this sheet (200 words maximum).

(This section is mandatory. You must complete it in order to get a mark.)

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CONTENT

Section B: Logic functions and combinational circuits............................................................................1

1.1 Cooperative group.....................................................................................................................................1

1.2 Abstract.....................................................................................................................................................1

1.3 Description................................................................................................................................................3

1.4 Topics........................................................................................................................................................3

1.5 Part 1: The basics (analysis)......................................................................................................................4

1.5.1 Analysis of combinational circuit based on logic gates....................................................................4

1.5.2 WolframAlpha...................................................................................................................................4

1.5.3 Installing and using Proteus-ISIS.....................................................................................................5

1.5.4 Installing and using ispLEVER Classic............................................................................................5

1.6 Part 2: The basics (design process).........................................................................................................10

1.6.1 Truth table, sum of minterms and product of maxterms.................................................................10

1.6.2 Simplifying logic functions using Minilog.......................................................................................10

1.6.3 Circuits in CMOS technology.........................................................................................................10

1.6.4 Circuits in LS-TTL technology........................................................................................................11

1.7 VHDL simulation using ModelSim or Active HDL...............................................................................11

1.7.1 Flat design in VHDL.......................................................................................................................11

1.7.2 Hierarchical design in VHDL.........................................................................................................11

1.8 Part 3: Building a library of standard combinational circuits.................................................................11

1.9 Another design example..........................................................................................................................12

1.10 Problem solution (títol 2)........................................................................................................................13

1.10.1 Part 1 (títol 3)..................................................................................................................................13

1.11 References...............................................................................................................................................13

1.12 Study plan to solve the exercise..............................................................................................................13

1.13 Topics and activities checklist................................................................................................................14

1.14 Grading grid............................................................................................................................................15

1.15 Questions in solving EX1........................................................................................................................15

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1.3 DescriptionIn this Section B of EX1, the basics of combinational circuits will be discussed. In Part 1 the process of analysing a given circuit until the specifications are determined. In Part 2 the design process is presented, from the initial specifications to the final circuit implementations. In Part 3, we will start the implementation of a variety of basic combinational building blocks using several of the techniques presented previously; the aim has to be the development of a library of components, which can be systematically enlarged in future terms.

The problem also introduces the installation and use of the latest computer aided design (CAD) software for analyse, design, simulate and synthesise combinational circuits into simple programmable logic devices (sPLD):

- WolframAlpha to deduce truth tables and equations from circuits or logic diagrams

- Minilog or Logic Friday (Espresso algorithm) to minimise logic equations

- ModelSim or ActiveHDL to simulate VHDL projects

- Proteus-ISIS, a complete virtual laboratory environment with includes SPLD models such as the GAL22V10

- ispLEVER Classic and ispVM System from Lattice Semiconductor and Synplify from Synplicity, to synthesise logic circuits into PLD.

Finally, you will have the opportunity to use word processors, spelling checkers, graphic tools and other auxiliary software in order to prepare documents which reflect the quality of your work.

1.4 Topics The following topics have been listed from the course’s specific and cross-curricular learning objectives1: #1, #2, #3, #5, #6, #7. After studying Chapter 1 and successfully completing all the assignments in this task, you will be able to:

------------- Part 1-------------

1. Use and explain the functionality of logic gates AND, NAND, OR, NOR, XOR, NXOR, NOT)

2. Analyze a logic circuit built using logic gates. Analysis concept map.

3. Use the application WolframAlpha to verify logic equations and determine the truth table of a combinational circuit.

4. Use the HADES JAVA-based platform2 to visualise and analyse the operation of digital circuits.

1 http://digsys.upc.es/ed//CSD/units/CSD_Guia_docent_esborrany.doc

2 http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/docs/tutorial.pdf

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5. Simulate a subcircuit, a digital circuit which is inside a black box or entity, using the virtual laboratory software Proteus-ISIS. Capture a logic schematic in Proteus-ISIS and run its simulation to verify how it is functioning.

6. Install the ispLEVER Classic from Lattice Semiconductor and follow its design flow to implement a schematic/VHDL project into a sPLD chip.

7. Search books and the Internet to find information about the basics of VHDL language.

8. Explain the design flow of a modern digital circuit: from the VHDL description to the PLD programming.

9. Explain the basic technological details of a SPLD like the GAL22V10 and the way it is programmed.

10. Explain the differences between the VHDL design styles: structural and behavioural.

------------- Part 2-------------

11. Explain and relate the following concepts for designing a logic circuit: truth table, Boolean algebra and logic functions, minimisation, SoP (sum of products) and PoS (product of sums), canonical algebraic equations, minterms and maxterms. Design concept map.

12. Simplify or minimize logic function using software like Minilog.exe.

13. Find the datasheets of the Small and Medium Scale of Integration (SSI and MSI) integrated circuits.

14. Explain the concepts of flat design and hierarchical design (build using signals and components and their instantiation in VHDL language).

15. Simulate a logic circuit using ModelSim or ActiveHDL

-------------- Part 3 ------------

16. Design and use standard combinational circuit building blocks (at least one of them): multiplexers (or data selectors), demultiplexers (or distributors), binary decoders and encoders, decoders for hexadecimal to seven-segment LED displays, code converters, adders, comparators, etc.

17. Produce a concept map (or a mind map) to explain a topic on the subject, for instance, explain the advantages of using hardware description languages instead of electronic gate-level schematics.

18. Organise a plan for developing the exercise and being able to work efficiently cooperating in a team of 3 members using the proposed methodology.

19. Analyse your own individual and group study time.

20. Produce a quality written solution; for example, document your work using a predefined word processor template and utilities: spelling and grammar, chapter enumeration, page headers and footers, hyperlinks, cross-references, figure captions, text styles, etc., for a given exercise, control or any other assignment, using the given instructions.

21. Assess the own or the group learning progression and the quality of the deliverables.

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1.5 Part 1: The basics (analysis) 1.5.1 Analysis of combinational circuit based on logic gates

Let’s start with the digital circuit in Fig. 1, a network of gates with 3 input signals and 2 output logic functions. As it can be seen, the circuit contains all kinds of gates. In this way, you’ll be able to study their functionality.

CC

CIRCUIT_1

a

b

c

s

r

a b c

S

R

Fig. 1 Circuit to be analysed.

a) Analysing the circuit network, obtain the circuit equations. These Boolean algebraic expressions constitute the starting point of the analysis process which can be found in the Unit 1.3: Analysis of a digital circuit (analysis concept map).

1.5.2 WolframAlpha

b) Obtain the truth table, the product of minterms and the sum of maxterms using WolframAlpha (Wolfram Research). This outstanding software that calculates everything is going to be your first electronic design automation (EDA) tool, because it will save you the task of minimising the algebraic expression by hand, in the same way a digital calculator spares you the need to solve logarithms,s square roots and other complicated mathematical stuff.

Fig. 2 WolframAlpha computational engine.

c) Find other software that could be used to analyse or design digital circuits, for example, examining the Software section in our web page.

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http://www.wolfram.com/

http://www.wolfram.com/


1.5.3 Installing and using Proteus-ISIS

d) Follow instructions in Unit 1.2 about installing and using Proteus-ISIS virtual laboratory. Open the tutorial exercise represented in Fig. 1 and run a simulation to analyse the way it works. Obtain its truth table and check if Proteus gives you the same result than WolframAlpha (Fig. 2). In the web pages will see several alternatives to the way of applying input signals, stimulus or test vectors. The idea behind the testing process is to verify all the truth table combinations.

e) Open the tutorial exercise represented in Fig. 1 and run a simulation to analyse the way it works. Obtain its truth table and check if Proteus gives you the same result than WolframAlpha. Thus, in this way you are going to be equipped with two very convenient software tools that will facilitate the design process of digital circuits. In the web pages will see several alternatives to the way of applying input signals, stimulus or test vectors. Fig. 3 shows an EasyHDL (Proteus scripting language) example, for inputting digital combinations to a circuit. The idea behind the testing process is to verify all the truth table combinations.

*SCRIPT GENERATOR TEST_SIGNALS

PIN X[0..2]

FLOAT BITTIME = 1000m

// Here you are all the truth table.

// A binary combination every 1 s

X = 000

SLEEP FOR BITTIME

X = 001

SLEEP FOR BITTIME

X = 010

SLEEP FOR BITTIME

X = 011

SLEEP FOR BITTIME

X = 100

SLEEP FOR BITTIME

X = 101

SLEEP FOR BITTIME

X = 110

SLEEP FOR BITTIME

X = 111

*ENDSCRIPT

Fig. 3 Example of a Proteus script file automatically to apply all the 8 input combinations to a given circuit.

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1.5.4 Installing and using ispLEVER Classic

Follow instruction in Unit 1.4 to install ispLEVER Classic for implementing projects into simple programmable logic devices (sPLD) like the GAL22V10. Check the software by running the following example design, which consist in a mix of schematics and VHDL files.

Basically, only two modules are needed to be installed, the software and the synthesiser Synplify:

isp7_0m1_classic_ispLEVER.exe (the name will change accordingly to the version)

SYN_p3.exe (Synplify Lattice version is a synthesiser tool from Synopsys)

One student of the group may also install the ispVMSystem in order to program the PROTOGAL board with the sPLD JED configuration file. A universal programmer3 like the TopMax is another alternative (see Fig. 11b).

ispLEVER Project Navigator and the GAL22V10 device

A sample project in a zip file at the E1 web will be provided for checking the correctness of the software installation before attempting any design: a basic HEX-7SEG decoder. This is project of a combinational circuit corresponding to a hexadecimal to 7-segment decoder. It is built using a mix of schematics in the classical way and VHDL modules. Our aim is to synthesise it and generate the configuration JED file prepared to be downloaded into the simple programmable logic device (sPLD) GAL22V10. This is the most elemental sPLD from Lattice and a classic that has become a standard circuit for many years. It has a capacity around 500 gates and also contains 10 D-type flip-flops.

Execute “Project Navigator” and load the already defined initial project HEX-7SEG.

Fig. 4 Tutorial project HEX-7SEG to be loaded into the Project Navigator

3 http://epsc.upc.edu/projectes/ed/Instruments/Instruments.html

9

http://epsc.upc.edu/projectes/ed/Instruments/Instruments.html

http://www.synopsys.com/


Fig. 5 and Fig. 6 show the HEX-7SEG entity and internal architecture. Check our web for more information and designs from previous terms or similar subjects [1].

Fig. 5 HEX_7SEG Symbol or entity

f) Run the design flow process and finally, print and write some explanations about the final “*.jed” configuration file.

Analysing some circuit details of the example circuit

g) Deduce the truth table for the HEX-7SEG circuit and explain the way to connect a 7-segment LED display to their outputs. If your circuit has to be powered at 5 V, calculate the values of the segments’ limiting resistors.

The example presented here is a structured design which consists of 3 simpler blocks and some logic, as represented in Fig. 6. Take a look into SC2 and SC3 to see their internal design using gates, and then go into SC1, which corresponds to a VHDL design. So, the idea is that you can mix schematics and VHDL files in order to produce a more complex design. However, our aim is to focus the course in projects based only in VHDL.

h) Deduce, applying WorframAlpha, the truth table for the SC2 and SC3. Why are the signals M0, C0 and C1 used for?

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Fig. 6 HEX_7SEG internal structure or architecture

i) Search Internet to read the GAL22V10 datasheet and study its architecture and the main technological characteristics. From the pdf, using the cut & paste tool, get 2 or 3 figures to document your work in addition to your own explanations. Which one of the seven different methods for implementing logic functions (NOT-OR-AND, NOT-AND-OR, NAND, NOR, method of decoders, method of multiplexers, ROM) is used in the GAL22V10? Which is the function of the programmable output logic macrocell?

Fig. 7 Device selector. Every project is associated to a programmable logic device. Select the GAL22V10 with the 24-pin package, the one which is included in Proteus-ISIS.

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Synthesising the project

Compile the HEX-7SEG design and examine the following files: a) the configuration JED for the programmer and for the simulator; and b) the report file RPT where you can see, among others, the synthesised logic equations and the chip pin assignment (see Fig. 8). Every time you compile, you may get a different pin assignment distribution, especially if the VHDL source files are modified. This problem is solved in the case of CPLD and FPGA devices using a constrain file (or a pin-assignment tool) specifying at which pins do you want to connect the entity ports while synthesising.

Fig. 8 Pin assignment as seen in the report output file (RPT)

Simulating the circuit using Proteus-ISIS

Fig. 9 shows the way the project looks like once the simulation has been launched in Proteus-ISIS. The sPLD configuration file *.JED from the ispLEVER must be assigned the GAL22V10 device which is placed inside the decoder block. Simulate the circuit to check if everything is alright.

SC

DESCODIFICADOR HEX-7SEG

B

A

b_L

c_L

d_L

e_L

f_L

g_L

a_LD

C

RBO_L

LT_L

BI_L

RBI_L

R1

330

Vcc

0010

111 1

Fig. 9 Proteus-VSM schematic which contains a single sPLD device GAL22V10 and the 7-segment display

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Programming the sPLD GAL22V10

Program the sPLD chip by means of the PROTOGAL board and the ispVM System (Fig. 10) and mount the laboratory prototype to verify whether it works accordingly to the specifications. MSE Microsystems Engineering (http://www.msebilbao.com) from Bilbao is the company that manufactures the PROTOGAL board seen in Fig. 11a. This is the fastest way to check the real functionality of the programmed chip. At the Electronics Laboratory of the EPSC we also have the universal ToolsMax programmer depicted in Fig. 11b. The key point here is that the configuration file (*.JED), already used in the simulator Proteus-VSM, is the same file which has to be processed by the programmer. Thus, when in the definitive prototyping stage, many of the common design errors already have been debugged and corrected, remaining generally only soldering, wiring and other practical issues. This is why the simulation stage speeds up the whole design process and enhances circuit’s reliability.

Fig. 10 The Lattice ispVM System for programming PLD chips using the “In System Programming” technique. A 4-wire programming bus makes unnecessary the use of a universal programmer.

a) b)

Fig. 11 a) PROTOGAL board for programming the ispGAL22V10 device. All the chip pins are available in the pin connector. b) Universal programmer TopMax from EETools (http://www.eetools.com)

j) Find in [1] the schematic of the “Micronator Lattice ispGAL Programmer” which is very similar to the PROTOGAL schematic in Fig. 11a. Analyse its schematic and try to explain their main features. Similar ideas found here, will also be present in the new USB-based programming boards. The key point for most of the new training boards is to use a USB interface instead of the old parallel port, which by the way, is not longer available in many PC’s.

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http://www.eetools.com/

http://www.msebilbao.com/


Your first application in VHDL

k) Study the basics of the Very High Speed Integrated Circuit Hardware Description Language (VHDL) using as many sources of information as possible [2]. Start a new VHDL-based project in ispLEVER Classic and implement the same circuit in Fig. 1 in a sPLD GAL22V10 following the design flow studied in the previous tutorial section. Consider the following two alternatives:

- Using a structural design based in the logic equations derived from the truth table.

- Using a high level description (or behavioural) architecture, directly stating the truth table, the circuit definition or its algorithm. The circuit is a 1-bit adder.

Be aware of documenting carefully your designs.

1.6 Part 2: The basics (design process) Our aim is to design the 2-bit adder4 shown in Fig. 12 and some alternatives will be proposed for the final implementations using classical chips or VHDL files synthesised into a sPLD.

?

?

ADDER2

CIRCUIT_2

Ci

A0

A1

S0

S1

B0

B1Co

Fig. 12 A 2-bit expandable adder

1.6.1 Truth table, sum of minterms and product of maxterms

l) Construct the truth table for the circuit. Write the equations for the:

- Sum of minterms

- Product of maxterms

1.6.2 Simplifying logic functions using Minilog

m) Install Minilog in your computer, and simplify the truth table to obtain the logic equations for the:

- Sum of products

- Product of sums

4 There is the possibility or option that each cooperative group has to analyse and design a different simple circuit.

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1.6.3 Circuits in CMOS technology

n) Draw a circuit in Proteus-ISIS using only NAND from CMOS technology and verify it.

1.6.4 Circuits in LS-TTL technology

o) Draw a circuit in Proteus-ISIS using only NOR from LS-TTL technology and verify it.

1.7 VHDL simulation using ModelSim or Active HDL An alternative way to Proteus-ISIS to simulate digital circuits is to use an industry standard VHDL simulator like Mentor Graphics ModelSim or Aldec Active HDL, which both have student editions, so, they are free to use, at least at this introductory level.

p) Download, install and license ModelSim, or Active HDL. To check your installation, to get used and learn about the simulation procedures, run the functional simulation of a simple example (like the one in Fig. 1) and compare to the previous ones obtained using the timing diagrams in Proteus ISIS. The simulation project has to be placed into a new folder under the upper general directory where other files from the exercise are located. Write down and explain the main issues concerning the simulation process: VHDL code, compilation, input activity generation using “do” macros, and simulation using wave timing diagrams to show input and output activity.

1.7.1 Flat design in VHDL

q) Make a new project using a single VHDL file (flat design, thus considering it as a small circuit) which will have the functionality of the entity in Fig. 12. Simulate your design in ModelSim or ActiveHDL, implement the circuit into a sPLD and verify it in Proteus ISIS.

- Using a structural design based in the logic equations (minimised or not) derived from the truth table.

- Using a high level description (the truth table itself) for the 2-bit adder entity.

1.7.2 Hierarchical design in VHDL

r) Make a new project consisting in many VHDL files (hierarchical design with instantiated components interconnected by signals) which will have again the functionality of the entity in Fig. 12. Implement the circuit into a sPLD and verify it in Proteus-ISIS.

- Firstly, produce the component SUM1 as a flat design and simulate it.

- And secondly, use it as a building block for the hierarchical design. Use a buffer for every input and output in the circuit. Your project probably will consist of two VHDL files: the entity top design with instantiated components, and the file for the SUM1 component.

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1.8 Part 3: Building a library of standard combinational circuitsOur aim is to start a library of components which are going to be implemented following different styles, like in the previous example of the 2-bit adder. Here you are different alternatives to the design that can be taken into account when designing combinational circuits:

- BUFFER/NOT – AND – OR

- BUFFER/NOT – OR– AND

- Only NOR

- Only NAND

- Flat design or a single structure

- Hierarchical design, chaining elemental blocks of the same kind among other components or logic.

- Only VHDL based projects

- CMOS technology schematics

- LS-TTL5 technology schematics

- Using classic commercial chips in CMOS or LS-TTL

s) Select a component from the following list and find a HADES java script to analyse the way it works. Such analysis implies drawing its symbol, writing its truth table and important equations. Every cooperative group have to choose a different device:

- Decoder DEC4:16 with enable

- A 16-channel data multiplexer MUX16 with enable

- Encoder for 10 keys ENC10:4 with key pressed signal

- A cascadable 4-bit comparator COMP4 (A<B, A=B, A>B)

- Hexadecimal to 7- segment decoder HEX-7SEG with blanking input and ripple blanking input and output (to blank leading zeroes in a chain).

- A quadruple data multiplexer of 4 channels 4MUX4

t) Select a component from the previous list and implement it in both versions: 1) using gates, and 2) using VHDL. Every cooperative group have to choose a different device and attempt different approaches.

5 The only reason for using these obsolete technologies is because the simulation models for all the devices and chips are available in Proteus.

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1.9 Another design example u) The idea: a combinational circuit to count the number of cars parked in a park of 40 slots.

When a particular slot is occupied, its ultrasonic sensor provides a ‘1’ signal, and a ‘0’ otherwise. A car park full signal is also provided when all slots are occupied. This project is essentially, a ones counter, a device to count de number of ‘1’ in any position.

Solve the problem as a VHDL project implemented in sPLD chips using a hierarchical structure of elemental components. The final circuit, which has to be verified in Proteus-ISIS, has to contain only GAL22V10 chips and the digits to show the parking car count.

A hint: start the problem solving a parking slot counter for only 4 cars.

Do not modify the text from page 3 to page 12

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1.10 Problem solution (títol 2)1.10.1 Part 1 (títol 3)

Part 1.1 (títol 4)

Start writing here your solution using the same template and conventions.

1.11 References Modify or add new references to this section. Follow the same format.

[1] http://digsys.upc.es . Comment: Course wed page where to find a lot of resources for the course. Specially, materials from previous editions. [retrieved July 2010]

[2] Brown,S., Vranesic, Z., “Fundamentals of digital logic with VHDL design”, McGraw-Hill, 2005. Comment: The Figure 1.7 contains an example of a design flow for logic circuits and Figure 2.29 the structure of a typical CAD/EDA system.

[3] (add here your own references)

[4]

1.12 Study plan to solve the exercise

Check the documentation in our web [1] to look at ways to establish a study plan, a task distribution scheme and other requirements to succeed in producing a good solution when working cooperatively: flux diagrams, concept maps, schematics, tables, pictures, etc.

(This section is mandatory. It must be filled in order to get a mark.)

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http://digsys.upc.es/


1.13 Topics and activities checklist

Topics Activities

Group member in

charge Comments

1 2 3

1. Explain the concept of a top-down design of a digital circuit.

a)

2. Explain the logic gates AND, NAND, OR, NOR, XOR, NXOR, NOT)

a)

3. Analyze a logic circuit built using logic gates. Analysis concept map.

a), g)

4. Use WolframAlpha to obtain a circuit’s truth table.

a)b), h)

5. Use the HADES JAVA-based platform simulate. c)

6. Simulate a digital circuit in Proteus-ISIS. d)

7. Install the ispLEVER Classic and follow its design flow to implement an example project into a sPLD.

e), f)

8. Explain the basics of a SPLD GAL22V10. i), j)

9. Search books and the Internet to learn about VHDL language.

k)

10. Explain the VDHL-based design flow of a modern digital circuit.

k)

11. Simulate projects in ModelSim or ActiveHDL

p)

12. Structural versus behavioural design styles in VHDL

k)

13. Relate the following concepts for designing a logic circuit: truth table, Boolean algebra and logic functions, minimisation, SoP (sum of products) and PoS (product of sums), canonical algebraic equations, minterms and maxterms. Design concept map.

l), m)

14. Simplify or minimize logic function using software like Minilog.exe.

m)

15. Find the datasheets of SSI and MSI chips. n), o)

16. Explain the concepts of flat and hierarchical designs using components and their instantiation in VHDL language.

r)

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17. Design and use standard blocks and apply combinational circuits.

s), t), u)

18. Produce a concept map (or a mind map) to explain a topic on the subject. List advantages of using VHDL

k)

19. Organise a plan to work in cooperative group for solving the exercises.

Sec. 1.12

20. Analyse your own individual and group study time.

Sec. 1.12

21. Produce a quality written solution using a word processor template:

a. spelling and grammar

b. chapter enumeration

c. page headers and footers

d. hyperlinks

e. cross-references

f. figure captions

g. text styles for technical reports

Sec. 1.11

22. Assessing Sec. 1.13, 1.14 and

1.15

1.14 Grading grid

Here you are the way the exercise could be grades.

Part 1 Part 2 Part 3

Total

Sections Sections Sections

Scores 2p 3p 5p

Self-assessment

Instructor’s grades

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1.15 Questions in solving EX1Reflect about the exercise development and about the way your cooperative group is coping with the task. Write down here your questions, comments, doubts, opinions, etc. Add more sheets if necessary to report your progress or comments through the exercise. Hand in the exercise before the due date uploading this “docx” file to your e-Portfolio Google site.

Aquests fulls de dubtes i d’explicació de com heu anat fent l’exercici són obligatoris. Si no és present, no es corregeix l’exercici i s’ha de tornar a lliurar. Abans de corregir i posar-vos qualificacions volem saber quin ha estat procés en què heu dissenyat els circuits i comparar-lo amb les nostres pròpies observacions de classe.

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Documents

EX1 - UPC Universitat Politècnica de Catalunyadigsys.upc.es/.../1011Q1/EX/EX1/EX1_10-11_Q1B.docx · Web viewIn this Section B of EX1, ... follow its design flow to implement a