Evolution of Si CMOS Technologies to Sub-10 nm Generation · Evolution of Si CMOS Technologies to Sub-10 nm Generation 10:10-10:40, June 4, 2012 Hiroshi Iwai, Tokyo Institute of Technology

Evolution of Si CMOS Technologies to Sub-10 nm Generation

10:10-10:40, June 4, 2012

Hiroshi Iwai, Tokyo Institute of Technology

Electron Devices Colloquium – Imec, Leuven, Belgium

1

First Computer Eniac: made of huge number of vacuum tubes 1946Big size, huge power, short life time filament

Today's pocket PCmade of semiconductor has much higher performance with extremely low power consumption

dreamed of replacing vacuum tube with solid‐state device

2

1960: First MOSFET by D. Kahng and M. Atalla

Top View

Al Gate

Source

Drain

Si

Si

Al

SiO2

Si

Si/SiO2 Interface is extraordinarily good

3

1970,71: 1st generation of LSIs

DRAM Intel 1103 MPU Intel 4004

4

2012Most recent SD Card

Most Recent SD Card

128GB (Bite) = 128G X 8bit = 1024Gbit= 1.024T(Tera)bit

1T = 1012 = １Trillion

Brain Cell：10～100 BillionWorld Population：7 Billion

Stars in Galaxy：100 Billion

Most Recent SD Card

2.4cm X 3.2cm X 0.21cm

Volume：1. 6cm³ Weight：2g

Voltage：2.7 - 3.6V

Old Vacuum Tube：5cm X 5cm X 10cm, 100g,100W

128 GB = 1Tbit

What are volume, weight, power consumption for 1Tbit

Old Vacuum Tube：5cm X 5cm X 10cm

1Tbit = 10,000 X 10,000 X 10,000 bitVolume = (5cm X 10,000) X (5cm X 10,000)

X (10cm X 10,000)= 0.5km X 0.5km X 1km

500 m

1,000 m

1Tbit

Burji KhalifaDubai, UAE(Year 2010)

828 m

Indian TowerMumbai, India(Year 2016)

700 m

700 m

Pingan IntenationalFinance CenterShanghai, China(Year 2016)

Old Vacuum Tube：100W

1Tbit = 1012bitPower = 0.1kWX1012=50 TW

Nuclear Power Generator1MkW=1BW We need 50,000 Nuclear Power Plant for

just one 128 GB memory

In Japan we have only 54 Nuclear Power Generator

Last summer Tokyo Electric Power Company (TEPCO) can supply only 55BW.

We need 1000 TEPCO just one 128 GB memory

Imagine how many memories are used in the world!

So progress of integrated circuits is extremely important for power saving.

12

Near future smart-society has to treat huge data.

Demand to high-performance and low power CMOS become much more stronger.

13

MemoryMemory[19%][19%]

MicrocompMicrocomp..[21%][21%]

Logic ICLogic IC[27%][27%]

Analog ICAnalog IC[15%][15%]

OthersOthers[18%][18%]

MemoryMemory[13%][13%]

MicrocompMicrocomp..[14%][14%]

Logic ICLogic IC[30%][30%]

Analog ICAnalog IC[10%][10%]

Emerging areasEmerging areas[33%][33%]

313 billion dollar (US) in 2011

1,528 billion dollar (US) in 2025

（Gartnerの市場予測）

Semiconductor Device Market will grow 5 times in 12 years!!

By K. Kim, CSTIC 2012

1900 1950 1960 1970 2000

VacuumTube

Transistor IC LSI ULSI

10 cm cm mm 10 µm 100 nm

In 100 years, the size reduced by one million times.There have been many devices from stone age.We have never experienced such a tremendous reduction of devices in human history.

10-1m 10-2m 10-3m 10-5m 10-7m

Downsizing of the components has been the driving force for circuit evolution

14

Downsizing1. Reduce Capacitance

Reduce switching time of MOSFETsIncrease clock frequency

Increase circuit operation speed2. Increase number of Transistors

Parallel processingIncrease circuit operation speed

Thus, downsizing of Si devices is the most important and critical issue.15

Downsizing contribute to the performance increase in double ways

16

(1970) 10 µm 8 µm 6 µm 4 µm 3 µm 2µm 1.2 µm

0.8 µm 0.5 µm 0.35 µm 0.25 µm 180 nm 130 nm 90 nm

Averaged downsizing rate (in the past 42 years): ~ 0.7X every 3 years

Total reduction in 19 generations: Gate Length ~ 1/500, Area ~ 1/250,000

65 nm 45 nm 32 nm 22 nm (2012)

Feature Size/Technology Node

Gate oxide

Gate metal

Source Drain

1V 0V0V

Substrate 0V DepletionRegion (DL)

1V

0V 0V

tox and Vdd have to be decreased for betterchannel potential control IOFF Suppression

0V < Vdep＜1V

0V

0V < Vdep＜1VChannel

0V

0V

0V0V

0.5V

Large IOFF

Region governed By drain bias

Region governed by gate bias

tOX thinning

DL touch with SRegion (DL)

Large IOFF

No toxthinning

Vdd

Vdd

17

Tunnelingdistance

3 nm

What would be the limit of downsizing!

Source DrainChannel

19

Vg (V)1

0.3 V

0.5 V 1.0 V

Ion

Ioff

Id (A/µm)

10-7

10-5

10-11

10-9

Vd

Vth

0.15 V

0 0.5

Subthreshold leakage current will limit the downsizing

20

Subthreshold Leakage (A/µm)

Ope

ratio

n Fr

eque

ncy

(a.u

.)

e)

100

10

1

Source: 2007 ITRS Winter Public Conf.

The limit is deferent depending on application

The down scaling of MOSFETs is still possible for at least another 10 years!

1. Thinning of high-k gate oxide thicknessbeyond 0.5 nm

2. Metal(Silicide) S/D

4. Wire channel

4 important technological items for down scaling.

New structures

New materials

3. III-V/Ge channel

1. High-k beyond 0.5 nm

Si-sub.

Metal

SiO2-IL

High-kSmall interfacial state density at high-k/Si

Oxygen diffusion control for prevention of EOT increase and oxygen vacancy formation in high-k

Thinning or removal of SiO2-IL for small EOT

Flat metal/high-k interface for better mobility

Issues in highIssues in high--k/metal gate stackk/metal gate stack

O

Workfunction engineering for Vth control

Interface dipole control for Vth tuning

Suppression of oxygen vacancy formation

Control of interface reaction and Si diffusion to high-k

Oxygen concentration control for prevention of EOT increase and oxygen vacancy formation in high-k

Suppression of metal diffusion

Endurance for high temperature process

Remove contaminationintroduced by CVD

Reliability: PBTI, NBTI, TDDB

Suppression of gate leakage current

Suppression of FLP

23

0 10 20 30 40 50Dielectric Constant

4

2

0

-2

-4

-6

SiO2

Ban

d D

isco

ntin

uity

[eV]

Si

XPS measurement by Prof. T. Hattori, INFOS 2003

Conduction band offset vs. Dielectric Constant

Band offset

Oxide

Leakage Current by Tunneling

24

R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)

Gas or liquidat 1000 K

H

Radio activeHe

Li BeB C N O F Ne

① Na Mg Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ① K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ① ① ① ① Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe ③ ① ① ① ① ① ① ① Cs Ba

HfTa W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn

Fr Ra Rf Ha Sg Ns Hs Mt

La Ce Pr Nd PmSmEu Gd Tb Dy Ho Er TmYｂ Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr

Candidates

Na Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ①

Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr

②

③

Unstable at Si interfaceSi + MOX M + SiO2①

Si + MOX MSiX + SiO2

Si + MOX M + MSiXOY

Choice of High-k elements for oxide

HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability

La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer

25

Direct highDirect high--k/Si by silicate reactionk/Si by silicate reaction

SiO2-ILHfSix (k~4)

VO

IO

IOVO

VO

IOIO

VOHfO2

Si substrate SiO2-IL(k~4)

LaSix

VO

IOVO

IO

VO

IOLa2O3silicate

La-rich Si-rich

Si substrate

High PO2Low PO2 High PO2Low PO2

SiO2 IL formation

Si substrate

silicate formation

Si substrate

HfO2 case La2O3 case

Direct contact can be achieved with La2O3 by forming silicate at interfaceControl of oxygen partial pressusre is the key for processing.

Our approach

K. Kakushima, et al., VLSI2010, p.69

27

1837184018431846Binding energy (eV)

Inte

nsity

(a.u

)

Si sub.

Hf SilicateSiO2

500 oC


Inte

nsity

(a.u

)

Si sub.

Hf SilicateSiO2

500 oC

SiOx-IL

HfO2

W

1 nm

k=4

k=16

SiOx-IL growth at HfO2/Si Interface

HfO2 + Si + O2→ HfO2 + Si + 2O*→HfO2+SiO2

Phase separator

SiOx-IL is formed after annealingOxygen control is required for optimizing the reaction

Oxygen supplied from W gate electrode

XPS Si1s spectrum

D.J.Lichtenwalner, Tans. ECS 11, 319

TEM image 500 oC 30min

H. Shimizu, JJAP, 44, pp. 6131

28

La-Silicate Reaction at La2O3/Si

La2O3

La-silicate

W

500 oC, 30 min

1 nm

k=8~14

k=23


Inte

nsity

(a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC


Inte

nsity

(a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC

La2O3 + Si + nO2→ La2SiO5, La2Si2O7,

La9.33Si6O26, La10(SiO4)6O3, etc.

La2O3 can achieve direct contact of high-k/Si

XPS Si1s spectraTEM image

Direct contact high-k/Si is possible

29

PMOS

High‐k gate insulator MOSFETs for Intel: EOT=1nm

HfO2 based high‐k

30Year

Pow

er p

er M

OSF

ET (P

)

P∝L

g 3

(Scaling)

EOT Limit0.7~0.8 nm

EOT=0.5nm

TodayEOT=1.0nm

Now

45nm node

One order of Magnitude

Si

HfO2

Metal

SiO2/SiON

Si

High-k

Metal

Direct ContactOf high-k and Si

Si

MetalSiO2/SiON

0.5～0.7nm

Introduction of High-kStill SiO2 or SiONIs used at Si interface

For the past 45 yearsSiO2 and SiON

For gate insulator

EOT can be reduced further beyond 0.5 nm by using direct contact to SiBy choosing appropriate materials and processes.

31

Substrate

Moving Mask

SourceElectron Beam

Flux

Deposited thin film

準備室

絶縁膜堆積室フラッシュランプアニール室

金属膜堆積室

ロボット搬送室

ALD室

RTA室

Robot

EB Evaporation Flash Lamp Anneal

ALD

RTA

Sputter

EB Evaporation

Flash Lamp Anneal

ALDRTAEntrance

Entrance

Sputter

High-k/metal gate stackfilm deposition cluster tool

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

0 0.5 1 1.5 2 2.5 3

EOT ( nm )

Cur

rent

den

sity

( A

/cm

2 )Al2O3HfAlO(N)HfO2HfSiO(N)HfTaOLa2O3Nd2O3Pr2O3PrSiOPrTiOSiON/SiNSm2O3SrTiO3Ta2O5TiO2ZrO2(N)ZrSiOZrAlO(N)

Gate Leakage vs EOT, (Vg=|1|V)

La2O3

HfO2

32

33

0.0E+00

5.0E-04

1.0E-03

1.5E-03

2.0E-03

2.5E-03

3.0E-03

3.5E-03

0 0.2 0.4 0.6 0.8 1

Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V

0 0.2 0.4 0.6 0.8 1

Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V

0 0.2 0.4 0.6 0.8 1

Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2VI d

(V)

W/L = 50µm /2.5µm

Vd (V) Vd (V) Vd (V)

EOT=0.37nm

Vth=-0.04VVth=-0.05VVth=-0.06V

EOT=0.37nm EOT=0.40nm EOT=0.48nmW/L = 50µm /2.5µm W/L = 50µm /2.5µm

0.48 0.37nm Increase of Id at 30%

La2O3 at 300oC process make sub-0.4 nm EOT MOSFET

34

2

1.5

1

0.5

0

Cap

acita

nce

[µF/

cm2 ]

-1 -0.5 0 0.5 1Gate Voltage [V]

10kHz 100kHz 1MHz

20 x 20µm2 1.5

1

0.5

0

Cap

acita

nce

[µF/

cm2 ]

-1.5 -1 -0.5 0 0.5Gate Voltage [V]

20 x 20µm2

10kHz 100kHz 1MHz

2

1.5

1

0.5

0

Cap

acita

nce

[µF/

cm2 ]

-1.5 -1 -0.5 0 0.5Gate Voltage [V]

20 x 20µm2

10kHz 100kHz 1MHz

FGA500oC 30min FGA700oC 30min FGA800oC 30min

A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC)

However, high-temperature anneal is necessary for the good interfacial property

35

① silicate-reaction-formedfresh interface

metal

Si sub.

metal

Si sub.

La2O3 La-silicateSi Si

Fresh interface with silicate reaction

J. S. Jur, et al., Appl. Phys. Lett., Vol. 87, No. 10, (2007) p. 102908

② stress relaxation at interface by glass type structure of La silicate.

La atomLa-O-Si bonding

Si sub.

SiO4tetrahedron network

FGA800oC is necessary to reduce the interfacial stress

S. D. Kosowsky, et al., Appl. Phys. Lett., Vol. 70, No. 23, (1997) pp. 3119

Physical mechanisms for small DitPhysical mechanisms for small Dit

36

No interfacial layer can be confirmed with Si/TiN/W

MIPSW TiN/W

Kav ~ 8 Kav ~ 12 Kav ~ 16

Si 2nm2nm2nm

HK

MG

La2O3Si/TiN/W

300

250

200

150

100

50

0

Elec

tron

Mob

ility

[cm

2 /Vse

c]

10.90.80.70.60.5EOT [nm]

at 1MV/cmT = 300K

Open : Hf-based oxides

Benchmark of LaBenchmark of La--silicate dielectricssilicate dielectrics

Gate leakage is two orders of magnitude lower than that of ITRS.

Electron mobility is comparable to record mobility with Hf-based oxides.

10-2

10-1

100

101

102

103

104

J g a

t Vg

= 1V

[A/c

m2 ]

0.80.750.70.650.60.550.5EOT [nm]

A = 10 x 10µm2

ITRS requirements

MIPS Stacks

This work (MIPS Stacks)

T. Ando, et al., (IBM) IEDM 2009, p.423

T. Kawanago, et al., (Tokyo Tech.) T-ED, vol. 59, no. 2, p. 269, 2012

37

substrate

①La gas feed ②Ar purge ③H2O feed ④Ar purge

Laligand H

O

substrate substrate substrate

1 cycle

ALD of LaALD of La22OO33

La

C 3H7

3

L a

C 3H7

3

L a

C 3H7

3

CLaN

NH

C3H7

C3H7

La(iPrCp)3 La(FAMD)3

Precursor (ligand)

ALD is indispensable from the manufacturing viewpoint- precise control of film thickness and good uniformity

K. Ozawa, et al., (Tokyo Tech. and AIST) Ext. Abstr. the 16th Workshop on Gate Stack Technology and Physics., 2011, p.107.

38

Why high mobility channel materials?Why high mobility channel materials?

S D

1) High injection Velocity of carriers

2) High mobility of carriers

Both 1) and 2) are important

Arming higher performance at lower supply voltage

Problems: Technologies and CostInterfacial properties at the gate insulator/semiconductor

Contact resistance at Source/Drain and semiconductor

Different semiconductors for n- and p- channel FETs

Integration on Si wafer

vinj

III-V (n-channel) or Ge (p-channel)

39

17

0.17

mHH: 0.44mLH: 0.016

850

0.014

77000

InSb

14.8

0.36

mHH: 0.57mLH: 0.35

500

0.023

40000

InAs

0.0820.067mt: 0.082ml: 1.467

mt: 0.19ml: 0.916

electron effectivemass (/m0)

2004001900430hole mob.(cm2/Vs)

5400920039001600electron mob.(cm2/Vs)

12.6121611.8permittivity

1.341.420.661.12band gap (eV)

mHH: 0.45mLH: 0.12

mHH: 0.45mLH: 0.082

mHH: 0.28mLH: 0.044

mHH: 0.49mLH: 0.16

hole effectivemass (/m0)

InPGaAsGeSi

17

0.17

mHH: 0.44mLH: 0.016

850

0.014

77000

InSb

14.8

0.36

mHH: 0.57mLH: 0.35

500

0.023

40000

InAs

0.0820.067mt: 0.082ml: 1.467

mt: 0.19ml: 0.916

electron effectivemass (/m0)

2004001900430hole mob.(cm2/Vs)

5400920039001600electron mob.(cm2/Vs)

12.6121611.8permittivity

1.341.420.661.12band gap (eV)

mHH: 0.45mLH: 0.12

mHH: 0.45mLH: 0.082

mHH: 0.28mLH: 0.044

mHH: 0.49mLH: 0.16

hole effectivemass (/m0)

InPGaAsGeSi

S. Takagi, et al., (Tokyo Univ) T-ED, vol. 55, no. 1, p. 21, 2008.

High mobility channel materialsHigh mobility channel materials

Better carrier transport

Higher drive current at low power supply40

ITRS 2011 for Si (HP: High Performance Logic)ITRS 2011 for Si (HP: High Performance Logic)

2012 2016 2018 2020 2022

Lg (nm)

Vdd (V)

EOT (nm)

Mobility enhancementfactor due to strain

CV/I (ps)

BulkFD SOI∗1: MG

Year of Production

∗1: Thicker EOT for MG(Multiple gate : Fin/Tri gate, nanowire)

2024 2026

Cg Ideal(fF/µm)

BulkFD SOI

MGBulk

FD SOIMGBulk

FD SOIMG

Vt,sat (mV)

2014

22 18 15.3 12.8 10.6 8.9 7.4 5.9

0.87 0.82 0.77 0.73 0.68 0.64 0.61 0.570.84 0.73 0.61

0.8 0.72 0.63 0.540.76 0.68 0.62 0.56 0.50 0.45

1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8

0.658 0.611 0.576

0.57 0.47 0.380.38 0.30 0.24 0.20

0.29 0.24 0.19 0.16 0.13 0.10

289 302 310222 227 234 242

217 223 225 228 231 237

0.529 0.429 0.3930.455 0.409 0.362 0.320 0.284 0.238

NMOS

Manufacturing solutionsexist or is being optimized

Manufacturing solutionsare known

Manufacturing solutionsare NOT known41

ITRS 2011 for Si (HP),contdITRS 2011 for Si (HP),contd

2012 2016 2018 2020 2022

Lg (nm)Equivalent

Injection velocity Vinj (107 cm/s)

BulkFD SOI

MG

Year of Production 2024 2026

Id,sat(mA/µm)

BulkFD SOI

MG

BulkFD SOI

MGBulk

FD SOIMG

Rsd (Ω-µm)

2014

CV2

(fJ/µm)

Isd,leak (nA/µm)

22 18 15.3 12.8 10.6 8.9 7.4 5.91.09 1.18 1.33

1.37 1.51 1.63 1.831.68 1.82 2.05 2.26 2.38 2.67

1.685 1.805 1.916 2.030 2.152 2.308

1.6701.367 1.4961.654 1.791 1.9421.530

100 100 100 100 100 100 100 100232 183 149

274 228 187 153257 218 186 160 133 104

0.47 0.38 0.32 0.260.38 0.31 0.25 0.21 0.17 0.14

0.490.68 0.57

Manufacturing solutionsexist or is being optimized

Manufacturing solutionsare known

Manufacturing solutionsare NOT known

42

ITRS 2011 for IIIITRS 2011 for III--V/GeV/Ge

2018 2022 2024 2026

Lg (nm)

Vdd (V)

EOT (nm)Mobility enhancement

factor due tochannel material

Year of Production 2020

14 11.7 9.3 7.4 5.80.63 0.61 0.58 0.56 0.540.68 0.62 0.56

8 8 8 8 80.50 0.45

4 4 4 4 4GeIII-V

0.28 0.24 0.20 0.16 0.130.41 0.36 0.30 0.25 0.21Ge

III-VCg Ideal(fF/µm)

229 230 238 245 251230 231 241 249 254Ge

III-VVt,sat (mV)

0.13 0.11 0.09 0.07 0.060.21 0.17 0.13 0.10 0.08Ge

III-VCV/I (ps)


43

ITRS 2011 for IIIITRS 2011 for III--V/Ge,ContdV/Ge,Contd

2018 2022 2024 2026

Lg (nm)

Year of Production 2020

14 11.7 9.3 7.4 5.84.29 4.58 5.32 5.93 6.642.26 2.44 2.86 3.19 3.63Ge

III-V

2.200 2.343 2.523 2.703 2.8841.769 1.932 2.121 2.330 2.555Ge

III-V

131 113 96 82 70149 126 105 85 72Ge

III-V

0.18 0.15 0.13 0.11 0.090.23 0.20 0.16 0.14 0.11Ge

III-V

Equivalent Injection velocity

Vinj (107 cm/s)

Id,sat(mA/µm)

Isd,leak (nA/µm) 100 100 100 100 100Rsd

(Ω-µm)

CV2

(fJ/µm)


44

45

2

1.5

1

0.5

0

Cap

acita

nce

[µF/

cm2 ]

-1 -0.5 0 0.5 1Gate Voltage [V]

10kHz 100kHz 1MHz

20 x 20µm2 1.5

1

0.5

0

Cap

acita

nce

[µF/

cm2 ]

-1.5 -1 -0.5 0 0.5Gate Voltage [V]

20 x 20µm2

10kHz 100kHz 1MHz

2

1.5

1

0.5

0

Cap

acita

nce

[µF/

cm2 ]

-1.5 -1 -0.5 0 0.5Gate Voltage [V]

20 x 20µm2

10kHz 100kHz 1MHz

FGA500oC 30min FGA700oC 30min FGA800oC 30min

A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC)

However, high-temperature anneal is necessary for the good interfacial property

Metal (Silicide) S/D

Extreme scaling in MOSFET Lphy

Dop

antC

onc. δ δGate

σ σ

Met

al C

onc.

Gate

Lphy = Leff- Atomically abrupt junction- Lowering S/D resistances- Low temperature process for S/D

Metal Schottky S/D junctions

- Dopant abruptness at S/D- Vt and ION variation- GIDL

Schottky Barrier FET is a strong candidate for extremely scaled MOSFET S DChannel

S DChannel

n+-Sin+-Si

Metal Silicide

Metal Silicide

48

Surface or interface controlDiffusion species:

metal atom (Ni, Co)Rough interface at silicide/Si- Excess silicide formation- Different φBn presented

at interface- Process temperature

dependent composition

Diffusion species: Si atom (Ti)Surface roughness increases- Line dependent

resistivity change

Line widthof 0.1 µm

H. Iwai et al., Microelectron. Eng., 60, 157 (2002).

Top view

Epitaxial NiSi2

O. Nakatsuka et al., Microelectron. Eng.,83, 2272 (2006).

Si(001) sub.Annealing: 650 oC

49

Si substrate

Ni-silicide

Si substrate

Si substrate

Ni-silicide

Si substrate

Deposition of Ni film

Deposition fromNiSi2 source Annealing Flat interface

Roughinterface

No Si substrateconsumption

Annealing

Deposition of Ni-Si mixed films from NiSi2 source

- No consumption of Si atoms from substrate- No structural size effect in silicidation process- Stable in a wide process temperature range

50

SEM views of silicide/Si interfaces

NiSi2 source

Ni source (50nm)

rough

rough

rough flat

flat

flat

STI 500nm

NiSi2 source (50nm)

500nm

500nm

STI

500nmSTI STI

500nmSTI500nmSTI600oC , 1min

700oC , 1min

800oC , 1min

- Rough interfaces- Consumed Si substrate - Thickness increase ~100 nm

Ni source

- Atomically flat interfaces- No Si consumption- Temperature-independent

Si substrate

Ni-silicide

Ni source

Ni-silicide

Si substrate

NiSi2 source

STI

51

Ideal characteristics (n = 1.00, suppressed leakage current)

Suppressed reverse leakage current- Flat interface and No Si substrate consumption- No defects in Si substrate

Ni

NiSi2

-0.8 -0.6 0.0 0.2Diode voltage (V)

-0.4 -0.210-5

10-4

10-3

10-2

Dio

de c

urre

nt (A

/cm

2 )

1.001.08

n

0.659NiSi2

0.676NiφBn (eV)Source

1.001.08

n

0.659NiSi2

0.676NiφBn (eV)Source

Generation current

RTA：500oC, 1min

Schottky diode structures

Leakage currentAl contact

Ni source

Al contact

NiSi2 source

Si substrate

Si substrate

NiSi2 source Applied Voltage (V)

Cur

rent

den

sity

(A/c

m2 )

52

Ni silicide Ni

200nm

Si Fin

Fins width：20nm50nm

Si Fin Ni silicide

Growth length

SiO2

NWs width：20nm

SiO2 Ni silicide

Ni silicide

Si NW

50nm

200nmGrowthlength

(a) (b)

Wire channel

54

1V0V

0V

S

0V

0V ＜V＜1V

1V0V

0V

0V

0VS D

G

G

G

Suppression of subthreshold leakage by surrounding gate structure

Planar Surrounding gate

Planar Ｆｉｎ Nanowire

Source DrainGate

Wdep

1

Leakage current

S D

Planar FETFin FET Nanowire FET

Because of off-leakage control,1V

0V

0V0V

0VS

D

GG

56

Fin Tri-gate Ω-gate All-around

G G G

G

GNanowire structures in a wide meaning

57

Si nanowire FET as a strong candidate

1. Compatibility with current CMOS process

2. Good controllability of IOFF

3. High drive current

1D ballisticconduction

Multi quantumChannel High integration

of wires

k

E

量子チャネル

量子チャネル量子チャネル量子チャネル

バンド図

Quantum channelQuantum channel


k

E

量子チャネル

量子チャネル量子チャネル量子チャネル

バンド図



Off電流のカットオフ

Gate:OFFDrain Source

cut-off

Gate: OFFdrainsource

Off電流のカットオフ

Gate:OFFDrain Source

cut-off

Gate: OFFdrainsource

Wdep

1

Leakage current

S D

Increase the Number of quantum channels

Energy band of Bulk Si

Eg

By Prof. Shiraishi of Tsukuba univ.

Energy band of 3 x 3 Si wire

4 channels can be used

Eg

58

59By Profs. Oshiyama and Iwata, U. of Tokyo

60

λ>>LDiffusive transport

λ<LBallistic transport

λ~LQuasi-Ballistic transport

Lλ ：Mean free pathsource drain

Mobility Theory

Real nanoscaleMOSFETs

Compact model for circuit designer is very important

Prof. K. Natori of TIT

61

0

10

20

30

40

50

0 0.1 0.2 0.3 0.4 0.5 0.6

300K VG-Vt=0.1V

300K VG-Vt=0.4V

300K VG-Vt=0.7V

300K VG-Vt=1.0V

4K VG-Vt=0.1V

4K VG-Vt=0.4V

4K VG-Vt=0.7V

4K VG-Vt=1.0V

Current (µA)

Drain Bias (V)


62

ポテンシャルプロファイル

チャネル

光学フォノン

初期弾性散乱域光学フォノン放出可能域

ε~kBT

ε*

ソース

キャリヤ透過確率 Ti

後方弾性散乱が支配後方弾性散乱＋（光学フォノン放出）

x00x

V(x)

F(0)

G(0)

( )0

(0) (0)( )

(0)F G

TF

ε=

− ⎞= ⎟

⎠ドレインからの入射透過確率

チャネル内の電子散乱導入の考え方チャネル内の電子散乱導入の考え方


63

F(x)/h は、正速度フラックス

G(x)/h は、負速度フラックス( )

( )

0

0

2 ( ) ( ) ( ) 0

2 ( ) ( ) ( ) 0

BdF xqEx F x G xm dx qEx

BdG xqEx G x F xm dx qEx

εε

εε

+ + − =+

− + + − =+

( )

( )

0 0

0 0

22 ( ) ( ) ( ) ( ) 0

22 ( ) ( ) ( ) ( ) 0

B DdF xqEx F x G x F xm dx qEx qEx

B DdG xqEx G x F x G xm dx qEx qEx

εε ε ε

εε ε ε

∗

∗

+ + − + =+ + −

− + + − + =+ + −

( )0

00 0 0 0 0

2( )

2 ln

D qET

qExB D D qE mD Bε

εε

=+⎛ ⎞+ + + ⎜ ⎟

⎝ ⎠

弾性散乱域

光学フォノン放出域

ソースからドレインへの透過確率（エネルギー εに対して）

散乱の導入に係る計算式散乱の導入に係る計算式

物理パラメータB0の値は移動度対応した値

物理パラメータD0の光学フォノンエネルギー緩和時間に対応した値


64

0

5

10

15

20

25

30

35

40

0 0.1 0.2 0.3 0.4 0.5

VG-Vt=0.1V, Bal.

VG-Vt=0.1V, Q-Bal.

VG-Vt=0.4V, Bal.

VG-Vt=0.4V, Q-Bal.

VG-Vt=0.7V, Bal.

VG-Vt=0.7V, Q-Bal.

VG-Vt=1.0V, Bal.

VG-Vt=1.0V, Q-Bal.

Current [µA]

Drain Bias [V]


65

0.E+00

2.E-05

4.E-05

6.E-05

8.E-05

0.0 0.5 1.0Vd (V)

Id (A

)

Vg – Vth = 1V

0.8V

0.6V

0.4V

0.2V

ExperimentQuasi ballistic

Device fabrication

Si/Si0.8Ge0.2superlatticeepitaxy on SOI

Anisotropicetchingof these layers

Isotropicetchingof SiGe

Gate depositions S/D implantationSpacer formationActivation annealSalicidation

BOXSi

SiGeSi

SiGeSi

SiGeSiN

BOX BOX

BOX

Gate

BOX

Gate

Gate etchingStandardBack-Endof-LineProcess

HfO2 (3nm)TiN (10nm)Poly-Si (200nm)

C. Dupre et al.,IEDM Tech. Dig., p.749, 2008

7

SiN HM

Process Details :

The NW diameteris controllabledown to 5 nm by self limited oxidation.

( )

Cross-section

50nm

SiN HM

Wire direction : <110>50 NWs in parallel3 levels vertically-stackedTotal array of 150 wires EOT ~2.6 nm

NWs

8

3D-stacked Si NWs with Hi-k/MG

BOX

500 nm

Sou

rce

Dra

in

Gate

Top view

<110>

C. Dupre et al.,IEDM Tech. Dig., p.749, 2008

SiNW FET Fabrication

Sacrificial Oxidation

SiN sidewall support formation

Ni SALISIDE Process (Ni 9nm / TiN 10nm)

S/D & Fin Patterning

Gate Oxidation & Poly-Si DepositionGate Lithography & RIE EtchingGate Sidewall Formation

30nm

30nm

30nm

Oixde etch back

Standard recipe for gate stack formationBackend

Lg=65nm, Tox=3nm

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

-1.0 -0.5 0.0 0.5 1.00

10 20 30 40 50 60 70

Dra

in C

urre

nt (µ

A)

Drain Voltage (V)

Vg-Vth=1.0 V

Vg-Vth= -1.0 V

0.8 V

0.6 V

0.4 V

0.2 V

(a)

10-12

Gate Voltage (V)

pFET nFET

(b)

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urre

nt (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

-1.0 -0.5 0.0 0.5 1.00

10 20 30 40 50 60 70

Dra

in C

urre

nt (µ

A)

Drain Voltage (V)

Vg-Vth=1.0 V

Vg-Vth= -1.0 V

0.8 V

0.6 V

0.4 V

0.2 V

(a)

10-12

Gate Voltage (V)

pFET nFET

(b)

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urre

nt (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

On/Off>106、60uA/wire

Recent results to be presented by ESSDERC 2010 next week in Sevile

Wire cross-section: 20 nm X 10 nm

010203040506070

1 10 100 1000Gate Length (nm)

I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V

括弧内は寸法を示す

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


(12)

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


(12)

本研究で得られたオン電流

(10x20)102µA

Our Work

Bench Mark

Y. Jiang, VLSI 2008, p.34H.-S. Wong, VLSI 2009, p.92S. Bangsaruntip, IEDM 2009, p.297C. Dupre, IEDM 2008, p. 749S.D.Suk, IEDM 2005, p.735G.Bidel, VLSI 2009, p.240

Si nanowireFET

Planer FETS. Kamiyama, IEDM 2009, p. 431P. Packan, IEDM 2009, p.659

1.2～1.3V

1.0～1.1V

Lg=500～65nm

IIONON/I/IOFF OFF Bench markBench mark

This work

72

0

2

4

0

2

40

5

10

15

x 1019

x (nm)y (nm)

Electron density (/cm3)

024681012

02

46

810

120

5

10

15

x 1019

x (nm)y (nm)

Electron density (/cm3)

(a) (b) width=12nmwidth=4nm

0

2

4

0

2

4500

550

600

650

x (nm)y (nm)

Mobility (cm2/Vs)

024681012

02

46

810

12700

750

800

850

900

x (nm)y (nm)

Mobility (cm2/Vs)


0

2

4

0

2

4500

550

600

650

x (nm)y (nm)

Mobility (cm2/Vs)

024681012

02

46

810

12700

750

800

850

900

x (nm)y (nm)

Mobility (cm2/Vs)


0 .E + 0 0

1 .E + 1 9

2 .E + 1 9

3 .E + 1 9

4 .E + 1 9

5 .E + 1 9

6 .E + 1 9

0 2 4 6 8Distance from SiNW Surface (nm)

6543210

角の部分

平らな部分

電子濃度(x1019cm-3)Electron Density

Edge portion

Flat portion

0

2000

4000

6000

8000

10000

12000

2008 2010 2012 2014 2016 2018 2020 2022 2024 2026

Year

I ON

(µA/µm

)

SiNW (12nm×19nm)

MGFDbulk

ION∝Lg-0.5×Tox

-1(20)

(11)

(33)

(15)

(26)

今回用いたIONの仮定

1µm当たりの本数

コンパクトモデルの完成

S/D寄生抵抗低減技術

pMOSの高性能化

低EOT実現技術

Compact model

Small EOT for high-k

P-MOS improvement

Low S/D resistance

# of wires /1µm

Assumption

ITRSNan

owire

Primitive estimation !

76

Conclusions

MOSFET is the most fundamental and smallest functional device available for manufacturing.

It is really amazing to keep the evolution for so many generations without being replaced by any other device.

77

The device downsizing of MOSFET will be ended within 10 - 20 years because many of the device parameters are now approaching the physical and manufacturing limits. Even after the end of MOSFET downsizing, CMOS technology will still be the mainstream IC technology for a long period, as no other device technology can be developed into a comparable integration scale as the present CMOS technology in foreseeable future.

Thank you for your attention!

78

Documents

Evolution of Si CMOS Technologies to Sub-10 nm Generation · Evolution of Si CMOS Technologies to Sub-10 nm Generation 10:10-10:40, June 4, 2012 Hiroshi Iwai, Tokyo Institute of Technology