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7/28/2019 evolution of processor
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It was introduced in November 15 1971. It had clock
rate of 740 kilohertz. It had bus width4 bits (multiplexed address/data due to limited pins)
Number of transistors present was 2,300 at 10 m.
Addressable memory was 640 bytes.program memory is 4 kb .
one of the earliest commercial microprocessors system
originally designed to be used in Busicom calculator.
It is a four bit processor.
INTEL 4004
http://en.wikipedia.org/wiki/Micrometrehttp://en.wikipedia.org/wiki/Micrometre7/28/2019 evolution of processor
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INTEL 8008It was introduced in April 1,1972.
It had clock rate of 500kilohertz. It had bus width of 8bits.
Number of Transistors present
was 3,500 at 10 mAddressable memory was 16 KB.
Typical in dumb terminals,
general calculators, bottlingmachinesDeveloped in tandem with 4004Originally intended for use in the
Data point 2200 terminal. It is aeight bit processor.
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INTEL 8086
Introduced June 8, 1978 Clock rates:
5 MHz with 0.33 MIPS 8 MHz with 0.66 MIPS 10 MHz with 0.75 MIPS
The memory is divided into odd and even banks. Itaccesses both the banks simultaneously in order to read16 bit of data in one clock cycle.
Bus Width 16 bits data, 20 bits address. Number of Transistors 29,000 at 3 m. Addressable memory 1 megabyte. Up to 10X the performance of 8080 (typically lower). Used in portable computing, and in the IBM PS/2 Model
25 and Model 30 Also used in the AT&T PC6300 / OlivettiM24, a popular IBM PC-compatible (predating the IBMPS/2 line.)
Used segment registers to access more than 64 KB of
data at once, which many programmers complainedmade their work excessively difficult.
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INTEL PENTIUM PRO Introduced November 1, 1995
Precursor to Pentium ii and iii
Primarily used in server systems
Socket 8 processor package (387 pins) (dual spa)
Number of transistors 5.5 million
Family 6 model 1
0.6 m process technology 16 kb l1 cache
256 kb integrated l2 cache
60 MHz system bus clock rate
0.35 m process technology ,r 0.35 m cup with 0.6 m l2 cache Number of transistors 5.5 million
512 kb or 256 kb integrated l2 cache
60 or 66 MHz system bus clock rate.
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INTEL PENTIUM 2
Introduced May 7, 1997
Pentium Pro with MMX and improved 16-bitperformance.
242-pin Slot 1 (SEC) processor package Number of transistors 7.5 million 32 KB L1 cache
512 KB bandwidth external L2 cache The only Pentium II that did not have the L2 cache at
bandwidth of the core was the Pentium II 450 PE. Klamath - 0.35 m process technology (233, 266, 300 MHz)
66 MHz system bus clock rate
Family 6 model 3 Variants
233 MHz Introduced May 7, 1997 266 MHz Introduced May 7, 1997 300 MHz Introduced May 7, 1997
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INTEL PENTIUM 3 Katmai - 0.25 m process technology Introduced February 26, 1999 Improved PII, i.e. P6-based core, now including Streaming SIMD
Extensions(SSE) Number of transistors 9.5 million 512 KB bandwidth L2 External cache 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor
package System Bus clock rate 100 MHz, 133 MHz (B-models) Slot 1 Family 6 model 7 Variants
450 MHz Introduced February 26, 1999 500 MHz Introduced February 26, 1999 550 MHz Introduced May 17, 1999 600 MHz Introduced August 2, 1999 533 MHz Introduced (133 MHz bus clock rate) September 27, 1999 600 MHz Introduced (133 MHz bus clock rate) September 27, 1999
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INTEL PENTIUM 4 Pentium 4 0.18 m process technology (1.40 and 1.50 GHz)
Introduced November 20, 2000 L2 cache was 256 KB Advanced Transfer Cache (Integrated) Processor Package Style was PGA423, PGA478 System Bus clock rate 400 MHz SSE2 SIMD Extensions
Number of Transistors 42 million Used in desktops and entry-level workstations
0.18 m process technology (1.7 GHz) Introduced April 23, 2001 See the 1.4 and 1.5 chips for details
0.18 m process technology (1.6 and 1.8 GHz) Introduced July 2, 2001 See 1.4 and 1.5 chips for details Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in
Battery Optimized Mode Power
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INTEL PENTIUM DUAL CORE Allendale - 65 nm process technology
Desktop CPU (SMP support restricted to 2 CPUs)
Two CPUs on one die Introduced January 21, 2007 SSSE3 SIMD instructions Number of Transistors 167 Million TXT enhanced security hardware extensions Execute Disable Bit EIST (Enhanced Intel Speed Step Technology) Variants
Intel Pentium E2220 - 2.40 GHz (1 MB L2, 800 MHz FSB) Intel Pentium E2200 - 2.20 GHz (1 MB L2, 800 MHz FSB) Intel Pentium E2180 - 2.00 GHz (1 MB L2, 800 MHz FSB) Intel Pentium E2160 - 1.80 GHz (1 MB L2, 800 MHz FSB) Intel Pentium E2140 - 1.60 GHz (1 MB L2, 800 MHz FSB)
Wolf dale 45 nm process technology Intel Pentium E6500 - 2.93 GHz (2 MB L2,1066 MHz FSB) Intel Pentium E6300 - 2.80 GHz (2 MB L2,1066 MHz FSB) Intel Pentium E5400 - 2.70 GHz (2 MB L2, 800 MHz FSB) Intel Pentium E5300 - 2.60 GHz (2 MB L2, 800 MHz FSB) Intel Pentium E5200 - 2.50 GHz (2 MB L2, 800 MHz FSB) Intel Pentium E2210 - 2.20 GHz (1 MB L2, 800 MHz FSB)
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INTEL PENTIUM CORE 2 DUO Conroe - 65 nm process technology Desktop CPU (SMP support restricted to 2 CPUs)
Two cores on one die Introduced July 27, 2006 Number of Transistors 291 Million 64 KB of L1 cache per core (32+32 KB 8-way) Intel VT multiple OS support TXT enhanced security hardware extensions
EIST (Enhanced Intel Speed Step Technology) iAMT2 (Intel Active Management Technology), remotely manage computers
Variants Core 2 Duo E6850 - 3.00 GHz (4 MB L2, 1333 MHz FSB) Core 2 Duo X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo X6850 - 2.54 GHz (4 MB L2, 1066 MHz FSB) Core 2 Duo E6750 - 2.67 GHz (4 MB L2, 1333 MHz FSB) Core 2 Duo E6700 - 2.67 GHz (4 MB L2, 1066 MHz FSB) Core 2 Duo E6600 - 2.40 GHz (4 MB L2, 1066 MHz FSB) Core 2 Duo E6550 - 2.33 GHz (4 MB L2, 1333 MHz FSB) Core 2 Duo E6420 - 2.13 GHz (4 MB L2, 1066 MHz FSB)
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INTEL CORE i7Bloomfield - 45 nm process technology 256 KB L2 cache 8 MB L3 cache Front side bus replaced with QuickPathup to 6.4GT/s Hyper-Threading is again included. This had previously been removed at the introduction of Core
line. 781 million transistors. Introduced November 17, 2008
Variants 920 - 2.66 GHz 940 - 2.93 GHz 950 - 3.06 GHz 965 (extreme edition) - 3.20 GHz 975 (extreme edition) - 3.33 GHz
Lynnfield - 45 nm process technology 8 MB L3 cache No Quick path, instead compatible with slower DMI interface Hyper-Threading is again included. This had previously been removed at the introduction of Core line Introduced September 8, 2009 Variants
860 - 2.80 GHz 870 - 2.93 GHz
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THANK YOUEVERYBODY.