Evaluation Board User Guide - Analog Devices · 2017-02-15 · Evaluation Board User Guide UG-200 OneTechnologyWay•P.O.Box9106•Norwood,MA 02062-9106,U.S.A.•Tel:781.329.4700•Fax:781.461.3113•

Evaluation Board User Guide UG-200

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the AD9467 16-Bit, 200 MSPS/250 MSPS ADC

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 28

FEATURES Full featured evaluation board for the AD9467 SPI and alternate clock options Internal and external reference options VisualAnalog and SPI Controller software interfaces

EQUIPMENT NEEDED Analog signal source and antialiasing filter 2 switching power supplies (6.0 V, 2.5 A) CUI EPS060250UH-

PHP-SZ, included PC running Windows® 98 (2nd ed.), Windows 2000,

Windows ME, or Windows XP USB 2.0 port, recommended (USB 1.1 compatible) AD9467 evaluation board HSC-ADC-EVALCZ FPGA-based data capture kit

DOCUMENTS NEEDED AD9467 data sheet HSC-ADC-EVALCZ data sheet, High Speed Converter

Evaluation Platform (FPGA-based data capture kit) AN-905 Application Note, VisualAnalog Converter Evaluation

Tool Version 1.0 User Manual AN-878 Application Note, High Speed ADC SPI Control Software AN-877 Application Note, Interface to High Speed ADCs via SPI

SOFTWARE NEEDED VisualAnalog SPI Controller

GENERAL DESCRIPTION This document describes the evaluation board for the AD9467, which provides all of the support circuitry required to operate the AD9467 in its various configurations. The application software used to interface with the device is also described.

The AD9467 data sheet, available at www.analog.com, which provides additional information, should be consulted when using the evaluation board. All documents and software tools are available at http://www.analog.com/fifo. For any questions, send an email to [email protected].

TYPICAL MEASUREMENT SETUP

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Figure 1. AD9467-250EBZ Evaluation Board and HSC-ADC-EVALCZ Data Capture Board

http://www.analog.com/AN-905



http://www.analog.com/

http://www.analog.com/fifo

mailto:[email protected]

UG-200 Evaluation Board User Guide

Rev. 0 | Page 2 of 28

TABLE OF CONTENTS Features .............................................................................................. 1 Equipment Needed ........................................................................... 1 Documents Needed .......................................................................... 1 Software Needed ............................................................................... 1 General Description ......................................................................... 1 Typical Measurement Setup ............................................................ 1 Revision History ............................................................................... 2 Evaluation Board Hardware ............................................................ 3

Power Supplies .............................................................................. 3

Input Signals...................................................................................3 Output Signals ...............................................................................3 Default Operation and Jumper Selection Settings ....................5

Evaluation Board Software Quick Start Procedures .....................6 Configuring the Board .................................................................6 Using the Software for Testing .....................................................6

Evaluation Board Schematics and Artwork ................................ 10 Ordering Information .................................................................... 25

Bill of Materials ........................................................................... 25

REVISION HISTORY 10/10—Revision 0: Initial Version



EVALUATION BOARD HARDWARE The AD9467 evaluation board provides all of the support circuitry required to operate the AD9467 in its various modes and configurations. Figure 2 shows the typical bench charac-terization setup used to evaluate the performance of the AD9467. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance (see the AD9467 data sheet).

See the Evaluation Board Software Quick Start Procedures section to get started and Figure 17 to Figure 31 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level.

POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2.5 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P700. Once on the PC board, the 6 V supply is fused and conditioned before connecting to low dropout linear regulators that supply the proper bias to each of the various sections on the board.

When operating the evaluation board in a nondefault condition, E704, E705, E706, E707 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P700 and P701 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current capability for 1.8 V AVDD1 and 1.8 V DRVDD;

however, it is recommended that separate supplies be used for both analog and digital domains. An additional supply is also required to supply 3.3 V to the DUT, 3.3 V AVDD2. This should also have a 1 A current capability. To operate the evaluation board using the SPI and alternate clock and amplifier options, a separate 3.3 V analog supply is needed in addition to the other supplies. The 3.3 V supply, or 3.3 V 3P3V_AVDD, should have a 1 A current capability.

INPUT SIGNALS When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMA or HP8644B signal generators or the equivalent. Use a 1 m shielded, RG-58, 50 Ω coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude (refer to the specifications in the AD9467 data sheet).

If a different or external ADC clock source is desired, follow the instructions in the Clock Circuitry section or use the on-board crystal oscillator, Y200. Typically, most Analog Devices, Inc., evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band band-pass filter with 50 Ω terminations. Analog Devices uses TTE and K&L Microwave, Inc., band-pass filters. The filter should be connected directly to the evaluation board.

OUTPUT SIGNALS The default setup uses the FIFO5 high speed, dual-channel FIFO data capture board (HSC-ADC-EVALCZ). For more information on this board and its optional settings, visit http://www.analog.com/fifo.

http://www.analog.com/fifo



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SIGNAL SYNTHESIZER

CLOCKINPUT

WALL OUTLET100V TO 240V AC

47Hz TO 63Hz SWITCHINGPOWERSUPPLY

SWITCHINGPOWERSUPPLY

PCRUNNING ADC

ANALYZEROR VisualAnalog

USER SOFTWARE

ANALOG INPUT

SIGNAL SYNTHESIZER

Figure 2. Evaluation Board Connection



DEFAULT OPERATION AND JUMPER SELECTION SETTINGS This section explains the default and optional settings or modes allowed on the evaluation board for the AD9467.

Power Circuitry

Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P700.

Analog Input Front-End Circuit

The evaluation board is set up for single-ended analog input connection with an optimum 50 Ω impedance match of 350 MHz of bandwidth. For a different bandwidth response, the input network needs to be changed or modified.

XVREF

XVREF is set to 1.25 V. This causes the ADC to operate with the default internal reference in the 2.5 V p-p full-scale range. A separate external reference option using the ADR130 is also included on the evaluation board. Populate R400 with a 0 Ω resistor. Note that ADC full-scale ranges from 2.0 V p-p to 2.5 V p-p are supported by the AD9467.

Clock Circuitry

The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.

The evaluation board can be set up to be clocked from the crystal oscillator, Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). If this clock source is desired, install C205 and C206 and remove C202. Jumper P200 is used to disable the oscillator from running.

A differential LVPECL or LVDS clock driver can also be used to clock the ADC input using the AD9517 (U300). Populate C304, C305, C306, and C307 with 0.1 µF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default clock path inputs. The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.

Dx+, Dx−

If an alternative data capture method to the setup shown in Figure 2 is used, optional receiver terminations, R500 to R509, can be installed next to the high speed backplane connector, P502.

http://www.analog.com/en/references/voltage-references/adr130/products/product.html

www.analog.com/AD9517



EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for using the AD9467, either on the evaluation board or at the system level design. Both the default and optional settings are described.

CONFIGURING THE BOARD Before using the software for testing, configure the evaluation board as follows:

1. Connect the evaluation board and the HSC-ADC-EVALCZ as shown in Figure 1 and Figure 2.

2. Connect one 6 V, 2.5 A switching power supply (such as the CUI, Inc., EPS060250UH-PHP-SZ included) to the evaluation board.

3. Connect one 6 V, 2.5 A switching power supply (such as the CUI EPS060250UH-PHP-SZ included) to the HSC-ADC-EVALCZ board.

4. Connect the USB cable to J6 on the HSC-ADC-EVALCZ board to the PC.

5. On the evaluation board, place jumpers on all four pin pairs of P600 to connect the SPI bus.

6. On the evaluation board, ensure that P200 is jumpered to the off setting to use the on-board 250 MHz Vectron VCC6 oscillator.

7. On the evaluation board, use a clean signal generator with low phase noise to provide an input signal to the desired channel. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable to connect the signal generator. For best results, use a narrow-band band-pass filter with 50 Ω terminations and an appropriate center frequency. (Analog Devices uses TTE, Allen Avionics, and K&L band-pass filters.)

USING THE SOFTWARE FOR TESTING Setting Up the ADC Data Capture

After configuring the evaluation board, set up the ADC data capture block using the following steps:

1. Open VisualAnalog® on a PC. AD9467 should be listed in the status bar of the New Canvas window. Select the template that corresponds to the type of testing to be performed (see Figure 3).

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Figure 3. VisualAnalog, New Canvas Dialog Box

2. After the template is selected, a message box opens, asking if the default configuration can be used to program the FPGA (see Figure 4). Click Yes, and the window closes.

If a different program is desired, follow Step 3.

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Figure 4. VisualAnalog, New Canvas Message Box

3. To view different channels or change features to settings other than the default settings, click the Expand Display button located on the top right corner of the VisualAnalog window, as shown in Figure 5 and Figure 6.

This process is described in the AN-905 Application Note, VisualAnalog Converter Evaluation Tool Version 1.0 User Manual. Once you are finished, click the Collapse Display button.

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EXPAND DISPLAY BUTTON

Figure 5. VisualAnalog Window Toolbar, Expand Display Button

http://www.analog.com/static/imported-files/application_notes/AN-905.pdf



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COLLAPSE DISPLAY BUTTON

Figure 6. VisualAnalog, Main Window Expanded Display

4. Program the FPGA of the HSC-ADC-EVALCZ board to a setting other than the default setting as described in Step 3. Then expand the VisualAnalog display and click the Settings button in the ADC Data Capture block (see Figure 6). The ADC Data Capture Settings box opens (see Figure 7).

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Figure 7. ADC Data Capture Settings, Capture Board Tab

5. Select the Capture Board tab and browse to the appropriate programming file. Next, click Program; the DONE LED, D6, in the HSC-ADC-EVALCZ board should then turn on.

6. Exit the ADC Data Capture Settings box by clicking OK.

Setting Up the SPI Controller

After the ADC data capture board setup has been completed, set up the SPI Controller:

1. Open the SPI Controller software by going to the Start menu or double-clicking the SPI Controller software desktop icon. If prompted for a configuration file, select the appropriate one. If not, check the title bar at the top of the SPI Controller window to determine which configura-tion is loaded. If necessary, choose Cfg Open from the File

menu and select the appropriate configuration. Note that the CHIP ID(1) field should be filled to indicate whether the correct SPI Controller configuration file is loaded (see Figure 8).

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Figure 8. SPI Controller, CHIP ID(1) Box

2. Click the New DUT button in the SPI Controller (see Figure 9).

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NEW DUT BUTTON

Figure 9. SPI Controller, New DUT Button

3. Click the Run button in the VisualAnalog toolbar (see Figure 10).

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RUN BUTTON

Figure 10. VisualAnalog Window Toolbar, Run Button



Applying Input Signal and Optimizing SFDR

Apply the input signal as follows:

1. Apply the input signal so that the fundamental is at the desired level (examine the Fund Power reading in the left panel of the VisualAnalog FFT window). See Figure 11 and Figure 12.

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Figure 11. VisualAnalog, FFT Graph, No Signal or Very Low Signal Applied

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Figure 12. VisualAnalog, FFT Graph, Full-Scale Signal Applied

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Figure 13. Typical FFT, AD9467 (No Buffer Current Optimization)

2. To optimize SFDR performance, use Register 36 and

Register 107 to change the buffer current setting. In the ADCBase 0 tab of the SPI Controller, find the BUFFER(36)/ BUFFER(107) box. Use the drop-down list box to select the best current, if necessary. See the AD9467 data sheet, the AN-878 Application Note, and the AN-877 Application Note for reference.

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Figure 14. SPI Controller, BUFFER(36)/BUFFER(107)

http://www.analog.com/static/imported-files/application_notes/575625536454413499145479332AN_878.pdf

http://www.analog.com/static/imported-files/application_notes/56755538964965031881813AN_877.pdf



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Figure 15. SPI Controller, SPI Controller, BUFFER(36)/BUFFER(107) Drop-

Down Setting

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Figure 16. Typical FFT, AD9467 (With Buffer Current Optimized)



EVALUATION BOARD SCHEMATICS AND ARTWORK

09436-017

ANALOG

INPUT

CIRCUITRY

LORR

ONAMP

LORR

AIN

ENABLE

OFF

AIN

DNI

B0310E5050A00

DNI

SMA-J-P-X-ST-EM1

SMA-J-P-X-ST-EM1

MABA-007159-000000

DNI

R132

R131

R134

R133

R130

R103

L105

6 42

3 1

T104

R129

1

210

95

4

3

7

8 6

T105

R128

R127

R125

R126

5 431

T103

54

32

1J102

R124

R123

R100

R101

R104

R108

R107

R110

R109

L100

R118

R117

C120

C119

L103

L104

L101

L102

R106

R105

C116

C115

R122

R116

R102

R115

C101

C100

C105

C106

321

P100

R114

R113

C113

R121

C114

C111

11 10

1 2 43

9

8765

PAD16151413

12

U100

54

32

1J101

54

32

1J100

C110

C107

C109C108

C104

C103

C102

NPC112

711C 811C

R120

R119

R112R111

6 4

2

3 1

T101

5

43

1

T102

5

431

T100

ADL5562_PRELIM

DNI

0.1UF

0.1UF

DNI

0.1UF

0.1UF

DNI

0.1UF

0.1UF

DNI

DNI

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

DNI

0.1UF

TBD0201

DNI

TBD0201

DNI

TBD0201

DNI

00

01515

120NH

33

10NH

30

ADT1-1WT+

00

MABA-007159-000000

DNI

30

DNI

DNI

AMPOUT-

AMPOUT+

33

DNI

00DNI

0

51

AMPOUT+

AMPOUT-

DNI

SMA-J-P-X-ST-EM1

DNI

51

DNI

AVDD_3P3V

10UF

0 0DNI

1.00K

DNI

15NH

DNI

36NH

FP93FP001

0 0

0 DNIAVDD_3P3V

DNI

5.6

36NH

15NH

INDIND

5.6

DNI

1.00K

DNI

0

00

0

ADT1-1WT+

DNI

DNI

0

MABA-007159-000000

AIN+

0

AIN-

TBD0201

TBD0201

0

0

SEC

PRI

AGND

SEC

PRI

AGND

AGND

AGND

AGND

AGND

AGND

AGNDGN

D

BAL_PORT2

DC

BAL_PORT1

DIFF_IN

NC

UNBAL

AGND

AGND

AGND

AGND

SEC PRI

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

PAD

GND

ENBL

VON

VOP

VCOM

VCC

VIN2

VIN1

VIP1

VIP2

AGND

AGND

AGND

Figure 17. DUT Analog Input Circuits



09436-018

CLK

CLK

(DEF

AULT

)

OPTIONAL

OSCILLATOR

CAPFORBALUN,

0OHMFORXFORMER

CLOCK

CIRCUITRY

OFF

ONOS

C

ENABLE

R202

R203

C205

C206

C201

R204

NPC200

R200

6 3

41

5Y200

R201

3 2 1

P200

R205

R208

C208

R207

R206

54

32

1J201 5

43

2

1J200

C204

C207

C203

C202

12

3

CR200

C210

C209

6 42

3 1

T201

5 431

T200

DNI

0.1UF

0.1UF

0.1UF

DNI

0.1UF

0.1UF

0.1UF

0.1UF

DNI

DNI

OPT_CLK_P

AVDD_3P3V

OPT_CLK_N

MABA-007159-000000

200

DNI

CLK+

CLK-

DNI

DNI

DNI

5151

SMA-J-P-X-ST-EM1

ADT1-1WT+

HSMS-2812BLK

DNI

SMA-J-P-X-ST-EM1

33 33

249

10K10K

10UF

249

0.1UF

0.1UF

DNI

DNI

0.1UF

OPT_CLK_P

OPT_CLK_N

AGND

AGND

AGND

CFO

VDD

FOE_D

GND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

SEC

PRI

Figure 18. DUT Passive (Default) Clock Circuit



09436-019

DECOUPLING

OPTIONAL

CLOCK

PATH

CIRCUIT

CHARGE

PUMP

FILTER

PECL

LVDS

AC

CR300

C323

C322

C307

C306

R308

R307

C304

C305

R303

321

P300

C302

C310

R311

C303

87654321J300

R300

R306

R305

R304

R310

R309

R302

R301

R315

C311

C312

C309

C308

R316

R314

R313

R312

4021

454337363130252410

3

7

5 151613

44

17

1

48 47

6

18

PAD

28 2926 2733 3235 3423222019383941428

2

14

46 4

1211

9

U300

C301

C300

C321

C320

C319

C318

C317

C316

C313

C315

C314

CP

SDO_USB

SDI_USB

SCLK_USB

LF

BYPASS_LDO

AGND

AD9517-4BCPZ

1500PF

0.1UF

0.1UF

DNI

0.1UF

0.1UF

DNI

0.1UF DN

I

0.1UF

OPT_CLK_N

0.1UF

0.1UFDNI

DNI

OPT_CLK_P

DNI

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

LNJ314G8TRA(GREEN)

1.00K

AD9517_CSB

0

249

DNI.22UF

4.12K

5.11K

249

249

1.00K

1.00K

1.00K

1.00K

0

200 .033UF

BYPASS_LDO

LF

AVDD_3P3V

AVDD_3P3V

AVDD_3P3V

AVDD_3P3V

CLK-

CLK+ CLK-

CLK+

DNI

0.1UF

OPT_CLK_P

0.1UF

AVDD_3P3V

OPT_CLK_N

0.1UF

0

CP

0

TSW-104-08-T-D

100

100

1800PF

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

OUT7_N_OUT7B

OUT7_OUT7A

OUT6_N_OUT6B

OUT6_OUT6A

OUT5_N_OUT5B

OUT5_OUT5A

OUT4_N_OUT4B

OUT4_OUT4A

OUT3_N

OUT3

OUT2_N

OUT2

OUT1_N

OUT1

OUT0_N

OUT0

STATUS

CPLD

CPRSET

REFMON

RSET

OD

SN

_S

CSDIO

SCLK

RESET_N

SYNC_N

PD_N

CLK_N

CLK

LFBYPASS

REFIN_N_REF2

REFIN_REF1

REF_SEL

PAD

VCP

VSVS_LVPECL

Figure 19. DUT Active Clock Circuit



09436-020

C457

C456

C455

C454

C432

C440

C446

C430

C439

C445

C433

C441

C447

C442

C450

C451

C452

C453

C448

C434

C443

C449

C435

C437

C444

C438

C404

C409

C414

C419

C403

C408

C413

C418

C402

C407

C412

C417

C422

C425

C400

C405

C410

C415

C420

C423

C426

C429

C401

C427

C424

C421

C416

C406

C411

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

AVDD1_DUT 0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

AVDD1_DUT

AVDD1_DUT

AVDD2_DUT

DRVDD_DUT

AGND

AGND

AGND

AGND

AGND

AD9447/AD9467

72PI

NLFCSP

DUT

CIRCUITRY

R400

C431

C428

43 5

2U400

66 67

47

51

4849

57 PAD

4039

65

45

43

41 14

46

44

42 13

37 1838 17

272830 29 26 25 24 23 22 2136 35 34 33 32 31 20 19

50

16

10

69686564

1211

987

43

7271706362

2

616059585655

545352

15

1

DUT1

1

TP401

C436

AIN-

AIN+

CSB_DUTSCLK_DUTSDIO_DUT

OR_TOR_C

DRVDD_DUT

D14/15_T

D14/15_C

D12/13_T

D12/13_C

D10/11_T

D10/11_C

D8/9_T

D8/9_C

DCO_T

DCO_C

D6/7_T

D6/7_C

D4/5_T

D4/5_C

D2/3_T

D2/3_C

D0/1_T

D0/1_C

DRVDD_DUT

CLK-

CLK+

AD9467BCPZ-250_PRELIM

AVDD1_DUT

AVDD1_DUT

AVDD1_DUT

AVDD2_DUTAVDD1_DUT

AVDD1_DUT

FU1.0F U1 .0

DNI

0

DNI0.1UF

ADR130AUJZ

AGND

AGND

AGND

AGND

AGND

AGND

GND

SET

VIN

VOUT

AGND

PADAVDD1AVDD1AVDD1AVDD2AVDD2

VIN_NEGVIN_POS

AVDD2AVDD2AVDD1AVDD1AVDD1AVDD1AVDD1AVDD1

REFERENCEAVDD1AVDD1

AVDD1AVDD1AVDD1

VDD3_SPICSB

SCLKSDIO

VDD8_SPIDVDDDVSSDVDDDVSSDVDDDVSSOR_TOR_C

DRGNDDRVDD

D14_15_TD14_15_CD12_13_TD12_13_CD10_11_TD10_11_CD8_9_TD8_9_CDCODCO_D6_7_TD6_7_CD4_5_TD4_5_CD2_3_TD2_3_CD0_1_TD0_1_C

DRVDDDRGNDAVSSAVDD1DVSSDVDDAVDD1AVDD1AVSSAVDD1AVDD1AVDD1ENC_ENCAVDD1AVDD1AVDD1AVDD1

Figure 20. DUT Circuitry



0943

6-02

1

OPTIONAL TERMINATION

R509

R508

R507

R506

R505

R504

R503

R502

R501

R500 DNI

100

100

DNI

100

DNI

100

DNI

100

DNI

100

DNI

100

DNI

100

DNI

100

DNI

100

DNI

C_51/41DT_51/41D

C_31/21DT_31/21D

C_11/01DT_11/01D

C_9/8DT_9/8D

C_7/6DT_7/6D

C_5/4DT_5/4D

C_3/2DT_3/2D

C_1/0DT_1/0D

C_OCDT_OCD

C_ROT_RO

BG9BG8BG7BG6BG5BG4BG3BG2

BG10

BG1

P501

DG9DG8DG7DG6DG5DG4DG3DG2

DG10

DG1

P501

C9C8C7C6C5C4C3C2

C10

C1

P501

D9D8D7D6D5D4D3D2

D10

D1

P501

B9B8B7B6B5B4B3B2

B10

B1

P501

A9A8A7A6A5A4A3A2

A10

A1

P501

DG9DG8DG7DG6DG5DG4DG3DG2

DG10

DG1

P502

BG9BG8BG7BG6BG5BG4BG3BG2

BG10

BG1

P502

C9C8C7C6C5C4C3C2

C10

C1

P502

D9D8D7D6D5D4D3D2

D10

D1

P502

B9B8B7B6B5B4B3B2

B10

B1

P502

A9A8A7A6A5A4A3A2

A10

A1

P502

AD9517_CSBCSB_USB

FPGA_CSBFPGA_SDIOFPGA_SCLK

SCLK_USBSDI_USB

6469169-1

DCO_C

D2/3_C

D4/5_C

D8/9_CD6/7_C

SDO_USB

D0/1_T

D14/15_C

D0/1_C

D12/13_C

OR_C

D6/7_T

D14/15_TD12/13_T

D10/11_CD10/11_T

D2/3_TD4/5_T

6469169-1

D8/9_T

OR_T

DCO_T

PLUG

HEAD

ER

PLUG

HEAD

ER

PLUG

HEAD

ERPL

UGHE

ADER

AGNDAGNDAGNDAGND

PLUG

HEAD

ERPL

UGHE

ADER

PLUG

HEAD

ER

PLUG

HEAD

ER

PLUG

HEAD

ER

PLUG

HEAD

ERPL

UGHE

ADER

PLUG

HEAD

ER

Figure 21. Digital Output Interface



0943

6-02

2

SPI CIRCUITRY

R605

4

6

5

2

3

1

U601

4

6

5

2

3

1

U600

R601

R600

C601

R604

C600

R603

R6028

7654321

P600

AVDD1_DUT

AVDD1_DUT

AVDD1_DUT

NC7WZ07P6X

TSW-104-08-G-D

10K

1.00K

0.1UF

1.00K

0.1UF

10K

10K NC7WZ16P6X

1.00K

AVDD_3P3V

AVDD_3P3V SCLK

CSB

CSB_USB

SCLK_USB

SDI_USB

SDO_USB

SDIO

Y2

Y1

A2

A1

GND

VCC

VCC

Y1A1

A2

GND

Y2

AGND

AGND

AGND

AGNDAGND

R611

R610

R609

R608

R607

R606

0

DNI0

0

DNI0

0

DNI0

SCLK_DUT

SDIO_DUT

SCLK

SDIO

CSB_DUT

CSB

FPGA_CSB

FPGA_SCLK

FPGA_SDIO

Figure 22. SPI Interface Circuitry



09436-023

WALWART

POWER

SUPPLY

CIRCUITRY

6VDC,

2A

MAX

OPTIONAL

POWER

CONN

ECTI

ONS

R704

R702

R701

R703

7

PAD

6543

2

1 8

U700

7

PAD

6543

2

1 8

U701

4321

P7014321

P700

R700

AC

CR701

ACCR700

21F700

3

21

J700

21E7072

1E705 2

1E704

21E706

87

PAD

6543

2

1U702

87

PAD

6543

2

1U703

C708

C715

C710

C717

C713

C720

C718

C719

C716

C709

21E702

21E701 2

1E700

21E703

AC

CR705

AC

CR704

AC

CR703

NPC714

A C

CR702

36 542

1

FL700

NPC707 NP

C704

NPC706

NPC705

C703C700

C701C702

ADP1706ARDZ-3.3-R7

ADP1708ARDZ-R7

ADP1708ARDZ-R7

0.01UF 0.01UF

0.1UF0.1UF

0.1UF0.1UF

750

45OHMS

4.7UF

1K

4.7UF

348

1K

PWR_IN2

Z5.531.3425.0

3P3V_AVDD

Z5.531.3425.0

DUT_AVDD2

DUT_DRVDD

45OHMS

45OHMS

DRVDD_DUT

10UF

AVDD2_DUT

10UF

AVDD_3P3V

AVDD1_DUT

DUT_AVDD1

45OHMS

10UF10UF

45OHMS

249

45OHMS

DUT_AVDD1

DUT_AVDD2

DUT_DRVDD

PWR_IN3

4.7UF

4.7UF

45OHMS

PWR_IN2

S2A-TP

S2A-TP

2A

RAPC722X

10UF

BNX016-01

S2A-TP

S2A-TP

S2A-TP

4.7UF

4.7UF

4.7UF45OHMS

3P3V_AVDD

3N

I_

RW

P2

NI

_R

WP

0N

I_

RW

PPWR_IN1

PWR_IN3

4.7UF

ADP1706ARDZ-1.8-R7

PGND

AGND

PAD

ADJ

IN GND1

SENSE

OUT

EN IN2

OUT2

PAD

ADJ

IN GND1

SENSE

OUT

EN IN2

OUT2

SIG

SH2

SH1

AGND

AGND

AGND

AGND

AGND

AGNDAGND

AGND

AGND

PAD

SSIN GND1

SENSE

OUT

EN IN2

OUT2

PAD

SSIN GND1

SENSE

OUT

EN IN2

OUT2

AGND

AGND

Figure 23. Power Supply Circuitry



0943

6-02

4

Figure 24. Top (Layer 1)



0943

6-02

5

Figure 25. Ground (Layer 2)



0943

6-02

6

Figure 26. Power Plane (Layer 3)



0943

6-02

7

Figure 27. Ground Plane (Layer 4)



0943

6-02

8




0943

6-02

9

Figure 29. Power Plane (Layer 6)



0943

6-03

0




0943

6-03

1

Figure 31. Bottom Side (Layer 8)



ORDERING INFORMATION BILL OF MATERIALS

Table 1. Item Qty Reference Designator Description Manufacturer Part Number 1 1 9467CE01A PCB 2 38 C101, C102, C104, C105, C106, C107, C108,

C109, C110, C111, C201, C202, C204, C207, C208, C209, C210, C302, C303, C313, C314, C315, C316, C317, C318, C319, C320, C321, C322, C323, C428, C431, C600, C601, C700, C701, C702, C703

Capacitor, 0.1 µF, 0402, X7R, ceramic

Murata GRM155R71C104KA88D

3 7 C112, C200, C704, C705, C706, C707, C714 Capacitor tantalum, 10 µF, 10 V, 10%, SMD

AVX TAJA106K010RNJ

4 1 C308 Capacitor, 1800 pF, 25 V, ceramic, 0402, SMD

Panasonic ECJ-0EB1E182K

5 1 C309 Capacitor, ceramic, 0.033 µF, 10%, 16 V, X5R, 0402

Panasonic 0402YD333KAT2A

6 1 C310 Capacitor, 1500 pF, 0402, 25 V, ceramic, X7R

Panasonic ECJ-0EB1E152K

7 55 C400, C401, C402, C403, C404, C405, C406, C407, C408, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C419, C420, C421, C422, C423, C424, C425, C426, C427, C429, C430, C432, C433, C434, C435, C437, C438, C439, C440, C441, C442, C443, C444, C445, C446, C447, C448, C449, C450, C451, C452, C453, C454, C455, C456, C457

Capacitor, ceramic, 0.1 µF, 6.3 V, X5R, 0201

Murata GRM033R60J104KE19D

8 8 C708, C709, C710, C715, C716, C717, C718, C720

Capacitor, ceramic, 4.7 µF, 6.3 V, X5R, 0603

Murata GRM188R60J475KE19D

9 2 C713, C719 Capacitor, 10,000 pF, 0402, 16 V, ceramic, X7R

Panasonic ECJ-0EB1C103K

10 1 C116 Capacitor, ceramic, 1.8 pF, 25 V, C0G 0201

Murata GRM0335C1E1R8CD01D

11 2 CR300, CR702 LED green USS type 0603 Panasonic LNJ314G8TRA 12 5 CR700, CR701, CR703, CR704, CR705 Rectifier SIL 2A 50 V DO-

214AA Micro Commercial Components Corp

S2A-TP

13 1 CR200 Diode Schottky dual series Avago HSMS-2812BLK 14 8 E700, E701, E702, E703, E704, E705, E706,

E707 Bead core 3.2 × 2.5 × 1.6 SMD T/R, 45 Ω @ 100 MHz

Panasonic EXCCL3225U1

15 1 F700 Polyswitch 1.10 A reset fuse SMD

Tyco/Raychem NANOSMDC110F-2

16 1 FL700 EMI filter LC block choke coil Murata BNX016-01 17 3 J100, J102, J201 SMA, end launch, COAX Samtec SMA-J-P-H-ST-EM1 18 2 J300, P600 CONN-PCB header 8-pin

double row Samtec TSW-104-08-T-D

19 1 J700 Power supply connector Switchcraft RAPC722X 20 1 L105 Inductor SM, 10 nH Coilcraft 0603CS-10NXJLW 21 3 P100, P200, P300 Conn-PCB BERG HDR ST

male 3P Samtec TSW-103-08-G-S

22 2 P501, P502 CONN_PCB 60-pin RA connector

Tyco 6469169-1

23 13 R107, R110, R123, R124, R125, R129, R310, R312, R314, R315, R606, R608, R610

Resistor, 0 Ω, 0402, 1/16 W, 1%

Panasonic ERJ-2GE0R00X



Item Qty Reference Designator Description Manufacturer Part Number 24 2 R117, R118 Resistor, 5.60 Ω, 1/16 W, 1%,

0402, SMD Vishay/Dale CRCW04025R60FNED

25 2 R119, R120 Resistor, 15 Ω, 1/20 W, 5%, 0201, SMD

Panasonic ERJ-1GEJ150C


Panasonic ERJ-2GEJ330X

27 4 R105, R106, R111, R112 Resistor, 33 Ω, 1/10 W, 5%, 0402, SMD


28 5 R200, R201, R600, R601, R602 Resistor, 10.0 kΩ, 0402, 1/16 W, 1%

Panasonic ERJ-2RKF1002X

29 2 R127, R128 Resistor, 0.0 Ω, 1/20 W, 0201, SMD

Panasonic ERJ-1GE0R00C

30 6 R204, R205, R303, R307, R308, R700 Resistor, 249 Ω, 0402, 1/16 W, 1%


31 10 R300, R304, R305, R306, R309, R603, R604, R605, R701, R702

Resistor, 1.00 kΩ, 0402, 1/16 W, 1%


32 1 R704 Resistor, 750 Ω, 1/10 W, 5%, 0402, SMD


33 1 R703 Resistor, 316 Ω, 0402, 1/16 W, 1%


34 1 R301 Resistor, 4.12 kΩ, 0402, 1/10 W, 1%


35 1 R302 Resistor, 5.1 kΩ, 0402, 1/16 W, 5%


36 1 R316 Resistor, 200 Ω, 1/10 W, 1%, 0402, SMD



Panasonic ERJ-1GEJ200C



39 2 T101, T104 XFMR, 1:1 impedance ratio Minicircuits ADT1-1WT+ 40 2 T103, T200 Balun, 1:1 impedance ratio Macom MABA-007159-000000 41 1 T105 Balun, 1:1 impedance ratio Anaren BD0205F5050A00 42 1 DUT1 IC-ADI LFCSP 10 mm ×

10 mm plus EPAD Analog Devices AD9467BCPZ-250

43 1 U100 IC 2.6 GHz ultralow distortion differential IF/RF amplifier

Analog Devices ADL5562ACPZ-R7

44 1 U300 IC-ADI 12-output CLK GEN with INT 1.6 GHZ VCO

Analog Devices AD9517-4BCPZ

45 1 U400 IC, voltage ref, precision series, SOT23_6

Analog Devices ADR130AUJZ

46 1 U600 IC tinylogic UHS dual buffer Fairchild NC7WZ07P6X 47 1 U601 IC tinylogic UHS dual buffer Fairchild NC7WZ16P6X 48 2 U700, U701 IC, regulator 0.8 V to 5.0 V,

low dropout CMOS, SO8 Analog Devices ADP1708ARDZ-R7

49 1 U702 IC-ADI low dropout CMOS linear regulator

Analog Devices ADP1706ARDZ-3.3-R7

50 1 U703 IC-ADI low dropout CMOS linear regulator

Analog Devices ADP1706ARDZ-1.8-R7

51 1 Y200 250 MHz, XTAL 3.3 V LVPECL OSC

Vectron VCC6-QCD-250M000



Item Qty Reference Designator Description Manufacturer Part Number 52 7 MP101, MP102, MP103, MP104, MP105,

MP106, MP107 Part of assembly, 100 mil jumpers, place into P100 (Pin 2 to Pin 3), P200 (Pin 1 to Pin 2), J300 (Pin 3 to Pin 4), P600 (Pin 1 to Pin 2, Pin 3 to Pin 4, Pin 5 to Pin 6, Pin 7 to Pin 8)

SAMTEC SNT-100-BK-G-H

53 4 MP111, MP112, MP113, MP114 Part of assembly, insert/ snap into the large holes from the bottom side of board, 14 mm height, dual locking standoffs for circuit board support

RICHCO CBSB-14-01



NOTES

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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