EVALUATION BOARD FLEXRAY-FPGA-EVA-KIT-369 · 2006. 9. 13. · 2005-05-23 V1.0, MSt First release 2005-07-14 V1.1, MSt FLEXRAY address area added; Access to LED port and IOPort at

Fujitsu Microelectronics Europe User Guide

FMEMCU-UG-910011-15

FLEXRAY EVALUATION BOARD

FLEXRAY-FPGA-EVA-KIT-369

USER GUIDE

FLEXRAY-FPGA-EVA-KIT-369 Revision History

FMEMCU-UG-910011-15 - 2 - © Fujitsu Microelectronics Europe GmbH

Revision History

Date Issue 2005-05-23 V1.0, MSt

First release 2005-07-14 V1.1, MSt

FLEXRAY address area added; Access to LED port and IOPort at FlexRay Main board added; Flash Programming added

2005-08-11 V1.2, MSt COMMSTACK naming corrected, Chapter Trouble shooting added Chapter FlexConfig added

2005-10-19 V1.3, MSt FlexPL Modules, Workaround Note added in chapter trouble shooting, New CUST register meaning added in chapter 9.7 ERAY version (beta) information added in chapter 9.8

2006-02-21 V1.4, MSt ERAY version information (beta2) added in chapter 9.8

2006-05-19 V1.5, MST ERAY version information added in chapter 9.8

This document contains 87 pages.

FLEXRAY-FPGA-EVA-KIT-369 Warranty and Disclaimer

© Fujitsu Microelectronics Europe GmbH - 3 - FMEMCU-UG-910011-15

Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for “FLEXRAY-FPGA-EVA-KIT-369” (eg. software include or header files, application examples, target boards, evaluation boards, engineering samples of IC’s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. The “FLEXRAY-FPGA-EVA-KIT-369” Board and all its deliverables are intended and must only be used in an evaluation laboratory environment.

1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer.

2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability and the customer´s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer´s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.

3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated.

4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s and its suppliers´ liability is restricted to intention and gross negligence.

NO LIABILITY FOR CONSEQUENTIAL DAMAGES

To the maximum extent permitted by applicable law, in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product.

Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect

FLEXRAY-FPGA-EVA-KIT-369 Contents


Contents

REVISION HISTORY............................................................................................................ 2

WARRANTY AND DISCLAIMER ......................................................................................... 3

CONTENTS .......................................................................................................................... 4

2 OVERVIEW...................................................................................................................... 8 2.1 Abstract................................................................................................................... 8 2.2 Features.................................................................................................................. 8 2.3 General Description................................................................................................. 9

3 INSTALLATION ............................................................................................................. 10 3.1 Hardware Installation............................................................................................. 10

3.1.1 Power-Supply configuration ..................................................................... 10 3.1.2 FlexRay-FPGA-Eva-Kit-369 configuration................................................ 11 3.1.3 Use as Emulation Target Board for Emulator MB2198-01........................ 12

3.2 Software Installation .............................................................................................. 12 3.2.1 Installation of Softune Workbench ........................................................... 12

4 QUICK PROJECT START-UP / TEST “FLEXRAY-FPGA-EVA-KIT-369”..................... 14

5 DECOMSYS::COMMSTACK LIBRARY ........................................................................ 16 5.1 Usage of the library ............................................................................................... 16 5.2 Documenation ....................................................................................................... 16 5.3 Software Samples on FlexRay CD ........................................................................ 16 5.4 Creating Applications ............................................................................................ 17 5.5 License Agreement ............................................................................................... 17

6 FLEXCONFIG CONFIGURATION TOOL....................................................................... 19 6.1 Installing FlexConfig .............................................................................................. 19 6.2 Project files for FlexRay Software-examples ......................................................... 19 6.3 License Agreement ............................................................................................... 19

7 FLEXRAY EVALUATION BOARD................................................................................. 21 7.1 Overview ............................................................................................................... 21

7.1.1 Features FlexRay Evaluation Main Board................................................ 21 7.1.2 Features FlexRay Evaluation Daughter Board ......................................... 22 7.1.3 Board Configuration................................................................................. 22

7.2 Jumpers and Switches .......................................................................................... 23 7.2.1 Main board............................................................................................... 23



7.2.1.1 Power Supply Voltage.............................................................. 23 7.2.1.2 Reset ....................................................................................... 25 7.2.1.3 Level Converter (BUS Switch) ................................................. 25 7.2.1.4 Bus Driver Interface (channel Ach) .......................................... 25 7.2.1.5 Bus Driver Interface (Bch)........................................................ 28 7.2.1.6 Reserved Switch...................................................................... 32

7.2.2 FlexRay Evaluation Daughter Board Settings .......................................... 32 7.2.2.1 Operating Mode Jumper .......................................................... 32 7.2.2.2 FPGA Configuration Jumper .................................................... 33

7.3 Header for Debug Signals ..................................................................................... 33 7.3.1 FlexRay Evaluation Main Board Check Pins ............................................ 33

7.3.1.1 Power supply voltage............................................................... 33 7.3.1.2 Mon 1 (J54) Connector (External Bus Interface) ...................... 34 7.3.1.3 Mon 2 (J55) Connector ............................................................ 36 7.3.1.4 Mon 3 (J56) connector ............................................................. 37

7.3.2 Daughter Board 1 .................................................................................... 38 7.3.2.1 Power supply voltage............................................................... 38 7.3.2.2 IOPORT Monitor J15 (masked part)......................................... 38 7.3.2.3 Configuration Monitor J16 (masked part) ................................. 39

7.4 Connectors............................................................................................................ 40 7.4.1 Power Connector (J30)............................................................................ 40 7.4.2 FlexRay Bus Connector P1, P2 ............................................................... 40 7.4.3 Daughter Board 1 Connectors J2, J3, J4, J5............................................ 40 7.4.4 Daughter Board 2 Connectors J6, J7, J20, J21........................................ 43 7.4.5 SMA Connector (J53) .............................................................................. 45 7.4.6 JTAG Connector J6 (JTAG of Daughter Board 1 for FPGA) .................... 45 7.4.7 CPU Board Connectors J50, J51 ............................................................. 45

7.5 Programming the FPGA ........................................................................................ 48

8 CPU369 BOARD............................................................................................................ 49 8.1 Overview ............................................................................................................... 49 8.2 Features................................................................................................................ 49 8.3 Jumpers and Switches .......................................................................................... 49

8.3.1 Power Supply Voltage (SW1, JP11, JP12, JP13, JP14, JP15, JP25)....... 49 8.3.2 Operating Mode (SW2) settings............................................................... 50 8.3.3 UART (JP21, JP22) settings .................................................................... 50 8.3.4 Chip select enable for FLASH (JP10) ...................................................... 51 8.3.5 Hardware Standby (JP16)........................................................................ 51



8.3.6 Clock Select (JP17, JP18, JP19, JP20) ................................................... 51 8.3.7 CAN controller interface (JP23, JP24) ..................................................... 52 8.3.8 Solder Bridges JP1 and JP2 on MCU top module.................................... 52

8.4 Header for Debug Signals ..................................................................................... 52 8.4.1 Power supply voltage (JP1, JP2, JP3, JP4, JP5, JP6) ............................. 52 8.4.2 MCU Peripheral Signals........................................................................... 53

8.4.2.1 Peripheral_1 (JH1) and Peripheral_2 (JH2) Header................. 53 8.5 Connectors............................................................................................................ 55

8.5.1 Power Connector J1 ................................................................................ 55 8.5.2 Serial Interface Connector P1.................................................................. 55 8.5.3 CAN Interface Connector......................................................................... 56

9 GETTING STARTED...................................................................................................... 57 9.1 Introduction to Softune Workbench ....................................................................... 57 9.2 Project Start-up ..................................................................................................... 59 9.3 Using the MB91F369 CPU-module........................................................................ 64 9.4 Softune Workbench Monitor Debugger.................................................................. 65

9.4.1 General Description ................................................................................. 65 9.4.2 Basic Debugger Features ........................................................................ 67 9.4.3 Advanced Monitor Debugger Features .................................................... 68

9.5 Provided Examples ............................................................................................... 70 9.6 Flash Programming ............................................................................................... 71

9.6.1 Programming MB91F369G series............................................................ 71 9.6.1.1 Fujitsu Flash MCU Programmer for FR series.......................... 71 9.6.1.2 Fujitsu MB91360 Flash Programmer........................................ 72

9.6.2 Programming external 1MByte Flash on CPU369 board.......................... 73 9.7 Memory Mapping of external Components ............................................................ 75

9.7.1 External SRAM ........................................................................................ 75 9.7.2 External Flash.......................................................................................... 75 9.7.3 ERAY (FlexRay communication Controller) ............................................. 75

9.8 ERAY Customer Register...................................................................................... 76 9.8.1 Customer Register description................................................................. 76

9.8.1.1 Information for CD1.0 .. 1.3...................................................... 76 9.8.1.2 Information since CD1.4 .......................................................... 77

9.8.2 Accessing the LED00..15 at FlexRay Main board .................................... 78 9.8.3 Reading FPGA ERAY version.................................................................. 78

9.8.3.1 Information for CD1.0 .. 1.3...................................................... 79 9.8.3.2 Information since CD1.4 .......................................................... 79



10 SILK-PLOTS OF THE BOARDS.................................................................................... 80 10.1 Silk-Plot of CPU369 board..................................................................................... 80 10.2 Silk-Plot of FPGA Main Board ............................................................................... 81 10.3 Silk-Plot of FlexRay Daughter Board 1 .................................................................. 82

11 TROUBLE SHOOTING .................................................................................................. 83

12 RELATED PRODUCTS ................................................................................................. 85

13 APPENDIX..................................................................................................................... 86 13.1 Figures 86 13.2 Tables 86

FLEXRAY-FPGA-EVA-KIT-369 Chapter 2 Overview


2 Overview

2.1 Abstract The FLEXRAY-FPGA-EVA-KIT-369 Evaluation board is a multifunctional Evaluation board for the Fujitsu 32-bit Flash microcontroller MB91F369G and Fujitsu FlexRay controller. It can be used standalone for software development and testing using Softune Workbench Monitor debugger or together with the emulator system. The board enables the designer to start immediately with the Software before his own target system is available.

The FLEXRAY-FPGA-EVA-KIT-369 Evaluation board comes with following parts

- Cremson-Starterkit-CPU369 board

- FlexRay Evaluation board, FPGA based

- Power Supply

- Printed version of the user guide “Flexray-MB91369 Evaluation board”

- FLEXRAY-FPGA-EVA-KIT-369 Evaluation board CD-ROM

- Microcontroller CD3.6 or higher

- Addendum sheet with latest important instructions

2.2 Features CPU-369 board

• Supports MB91F369G series

• 2MB external Debugging RAM

• 4MHz crystal

• DC Power supply circuit (incl. Test pins for VCC, GND, power LED and switch)

• 1 MB external Flash available for user code and constant data

• External Reset Button for MCU

• 2 Buttons for ext. Interrupt (USER_0 = ext. Interrupt0, USER_1 = ext. Interrupt1)

• MAX232 + DB9 (female) connector for internal UART

• CAN transceiver and DB9 (male) for internal CAN0

• 2 LEDs (on Port N)

• All peripheral pins are available by the connectors ‘Peripheral_1’ and ‘Peripheral_2’

• Sub board support

o 96pin + 48pin VG connector

FlexRay Main board

• DC Power-supply circuit for the entire system

• Supports FlexRay Controller FPGA and stand-alone version via Daughter Board 1 exchange.

• Flexible transceiver selection

o RS485 Transceiver on the board (default)

o FlexRay transceiver via “Daughter Board 2"

FLEXRAY-FPGA-EVA-KIT-369 Chapter 2 Overview


• Terminal layout of Daughter board 2 has compatible terminal layout of “FlexPL Module TJA1080/UJA1081” manufactured by TZM

• The switch control of "WAKE, EN, STBN signal" between CC and Bus Driver can be done.

• 2 Channel carries the outside interface Dsub-9 (male) for FlexRay Bus.

• External bus connector for the CPU Board Interface connection.

• BUS Level Converter (3.3V-5.0V) that does the change of all the signals of External bus Connector.

• All the pins (except for the power supply) of External bus connector are connected with Daughter Board 1.

• Various jumpers for individual configuration

• SPI Interface between DaughterBoard1 and DaughterBoard2

• 16 LEDs by the control of Daughter Board 1.

• Header pin of 32 I/O Ports by the control of Daughter Board 1

• The reset circuit between FlexRay Evaluation Board and CPU Board can be divided.

FlexRay Evaluation daughter board

• Hosted on FlexRay Evaluation Main Board

• The interface of all the pins (except for the power supply) of External bus connector for CPU Board Interface is possible

• FPGA: ALTERA Device Stratix EP1S25F672C

• Hosted Configuration FLASHROM: ALTERA Device EPC16QC100

• Configuration FLASHROM can be written in via JTAG


• 16 LEDs on Main Board connected to FPGA

• 32 IOPORTs on Main Board connected to FPGA

2.3 General Description

The “FlexRay-FPGA-Eva-Kit-369” supports the MB91F369 microcontroller series and the FPGA based FlexRay Communication Controller (E-Ray). It can be used as a standalone evaluation board or together with an emulator system.

The Evaluation board support following package at CPU board: FPT-160P-M15.

On CPU board the microcontroller is supplied with a 4MHz crystal; via the internal PLL the max. CPU frequency of 64MHz can be achieved. The FPGA based communication controller is supplied with a 80 MHz oscillator at the FlexRay daughter board.

For an easy start-up, a driver library and a code generator for initialisation is inside the delivery package.

The DECOMSYS:COMMSTACK driver library enables an easy access to the FlexRay Communication Controller.

The Configuration Tool FlexConfig enables an easy generation of the initialisation Code for the FlexRay Communication Controller.

FLEXRAY-FPGA-EVA-KIT-369 Chapter 3 Installation


3 Installation

3.1 Hardware Installation

3.1.1 Power-Supply configuration The Flexray-FPGA-MB91F389 Evaluation board contains a universal AC/DC power-supply adapter. Use power-supply plug on FPGA FlexRay controller board. Before connecting the power-supply to the evaluation board ensure the correct configuration of the power-supply:

1. Voltage selection to 12V

2. Appropriate DC plug is plugged into the socket.

3. Connect CPU board and FPGA board via the two VG-connectors.

4. Power-on the FLEXRAY-FPGA-EVA-KIT-369 via SW6 at FPGA board. On FPGA board the red ‘power’ LED, on Daughter board the green LED D1 should be lightning. At CPU369 board, the five green power LED’s D4, D7, D10, D13 and D16 should lightning. Following picture will illustrate the LED position.

Figure 1: LED lightning after power-on



3.1.2 FlexRay-FPGA-Eva-Kit-369 configuration

Carefully remove the board from the shipping carton. Check if there are any damages first before power on the Starter kit.

For the power supply a DC input voltage of 12V-18V / >1A is recommended The positive voltage (+) must be connected to the centre pin, and ground (GND) must be connected to the shield X1! The following picture shows the default jumper settings as a short reference. For details please check the chapter 5.2 Jumpers and Switches or 6.3 Jumpers and Switches

Figure 2: CPU369 default Jumper setting

Figure 3: FPGA-board jumper setting



3.1.3 Use as Emulation Target Board for Emulator MB2198-01 The “Flexray-FPGA-MB91F389 Evaluation board” can also be used as an emulator target board. In this case the user must remove the MCU-adapter-board with MB91F369 Flash MCU, U1 and plug in the Starterkit91360-ADA160, including a socket, instead. The probe cable must be mounted to the socket; no MCU must be inserted in this case. Take care of pin 1 marking onto the socket and fix the probe cable with screws.

Do not use other probe cable than FR360-PROBE-160 only!

Connect the probe cable to the emulation pod. Check all DIP-switch-settings of the evaluation board and the emulation pod.

For the power on sequence the emulator system must be switched on first. Then switch on the evaluation board. Please look at the corresponding user manuals for the emulator how to set up the emulator system. After the power on the Reset-LED of the emulator must be off and the Vcc-LED (D22) must be on. If the Reset-LED is still on, check the Vcc voltage switch-settings of the emulator system and the power supply of the evaluation board.

For more details please check the following application notes for MB2198-01

MB2198-01 Installation Guide MB2198-01 AN-910026-11-MB2198INST.pdf

MB2198-01 Getting Start AN-910027-10-MB2198Start.pdf

MB2198-01 Emulation and Debugging with Softune AN-910028-10-MB2198emu.pdf

3.2 Software Installation

3.2.1 Installation of Softune Workbench Fujitsu supplies a full working 32bit development environment with the “Flexray-FPGA-MB91F369 Evaluation board” called Softune Workbench V6. The Softune Workbench also supports a monitor debugger, which is pre-programmed into the external Flash memory of the “Flexray-FPGA-MB91F369 Evaluation board” on CPU369 board. To develop own software and to work with the Monitor Debugger of “Flexray-FPGA-MB91F369 Evaluation board” the Softune Workbench development environment must be installed first. Follow the instructions for successful installation of the Softune Workbench.

1. Before starting the installation setup ensure that you are logged in with administrator or power user permissions, otherwise the Softune installation will fail! Be aware that Softune does not support multi-user support. Therefore install- and user login must be the same.

2. Browse on the Microcontroller CD-ROM CD2 (V3.6 or later) into the directory “FME_36_Tools\pdf” and start the FRSTAPACK600005FME01.exe

You can also start the installation using a browser by opening the start.html of the CD-ROM. Use the link “Software\Softune WB-32\” in the left side frame and start the “Softune Workbench Version Propack600005” (FRSTAPACK600005FME01.exe)

3. Follow the installation instructions

4. For the default installation path it is recommended to use c:\Softune32

5. After the installation is finished, Softune Workbench for FR can be started via the Windows “Start” menu



6. When Softune Workbench is started the following window will be shown

FLEXRAY-FPGA-EVA-KIT-369 Chapter 4 Quick Project Start-up / Test “FLEXRAY-FPGA-EVA-KIT-369”


4 Quick Project Start-up / Test “FLEXRAY-FPGA-EVA-KIT-369”

To open a project with Softune Workbench and to work with the monitor debugger, Softune Workbench must be started first. To open a project the following steps must be taken.

5. Ensure that no other windows application is using the COM1 port

6. Ensure correct jumper setting of SW11 position of CPU369 board (MCU Operating Mode)

7. Ensure that the “FlexRay Evaluation Kit” is connected via serial cable (P1, UART0 of CPU369 board) with COM1 of the PC.

Open the test-project using the <File>, <Open Workspace> dialog. Browse into the sample folder: e.g.: c:\..\software\examples\StarterkitMB91302_Test\ and select the file StarterkitMB91302_Test.wsp

8. Ensure that the configuration “MONDEBUGGER” is selected! Start the Monitor Debugger by double click on MonDeb 57K6 COM1 in the following menu.

MonDeb 57K6 COM1.sup

Select Configuration MONDEBUG

FLEXRAY-FPGA-EVA-KIT-369 Chapter 4 Quick Project Start-up / Test “FLEXRAY-FPGA-EVA-KIT-369”


If a different COM port is used please use MonDeb 57K6 COM2.sup for COM2 or right-click on the “MonDeb 57K6 COM1” and select change. Follow the wizard to modify settings.

9. Now the debugger starts and a download progress bar is shown indicating that the application program is downloaded to the “FLEXRAY-FPGA-EVA-KIT-369”.

10. After downloading the application successfully into the external SRAM of the “FLEXRAY-

FPGA-EVA-KIT-369” the following Softune Workbench screen is shown. The debugger offers now versatile features as “Run continuously, Step-In, Step-over, Step-out, ...” which can be used via the Icon list. Using the right mouse button opens a context menu offering more settings as “Set Breakpoints, …”.

11. Use the button “Run Continuously” to start the application and use the “USER_0” button on the “FLEXRAY-FPGA-EVA-KIT-369” to abort the Continuous program execution. Be aware for FlexRay communication two Nodes are necessary.

Note:

The command “Abort” to stop program execution is not supported by the Softune Workbench monitor debugger and might cause malfunction of the debugger if used. To “Abort” program execution, use the button “USER_0I” on the “FLEXRAY-FPGA-EVA-KIT-369”.

12. For more details about Softune Workbench monitor debugger please check chapter 9.4

Right mouse click Context dialog

FLEXRAY-FPGA-EVA-KIT-369 Chapter 5 DECOMSYS::COMMSTACK Library


5 DECOMSYS::COMMSTACK Library

5.1 Usage of the library The DECOMSYS::COMMSTACK Library can be used to access the FlexRay Communication Controller register. The Library must be installed, before usage.

Browse to “Software\Commstack\” folder at FlexRay “FlexRay-FPGA-Eva-Kit-369” CD and execute the commstack-lib.exe

On FlexRAy CD V1.3 the DECOMSYS::COMMSTACK version V1.3 is used. This version supports ERAY V1.0.1 (PrebetaII) and ERAY V1.1 (PrebetaII-update).

Debug possibilities of DECOMSYS::COMMSTACK:

It is possible to use the UART interface to output message via the library functions.

- ttPrintf()

- dcsHALMsg(DCSHAL_DEBUG, "ttShutdownHook (0x%x)", error );

-

It is possible to use a Debug pin via the library function.

- dcsHALDebugpinHigh(0);

- dcsHALDebugpinLow(0);

To enable/disable to debug output of the DECOMSYS::COMMSTACK library

check in the settings of

U8 nEnableRS232_Output = ;

U8 nEnableDebugpinOutput = ;

In your application.

Set this switches to

1 to enable or

0 to disable

the appropriate functionality.

5.2 Documenation After extracting the library, a folder ‘Additional Information’ is available. The description of the library functionscon be found in the Commstack_API_Manual.pdf documentation..

5.3 Software Samples on FlexRay CD The Samples “Gateway” and “Keyboard” are using the DECOMSYS::COMMSTACK library. (“Software\Samples” folder)

Install the Library into the root folder of these examples, in case of modifying these examples.



5.4 Creating Applications

When crating own Application using DECOMSYS::COMSTACK library following should be considered.

Check carefully the Gateway example. Within the ‘generated code’ folder there are several required files.

- The library must know the address offset of the ERAY CC.

o In the Gateway example this is done in the file dcsdriver-ctrlhandles.c via TDDLL_CtrlHandleType aCtrlHandles[]

- Decide if using Debug output function of the Library

o In the Gateway example this is done in the file dcsdriver-ctrlhandles.c via U8 nEnableRS232_Output = 0; nEnableDebugpinOutput = 0;

- Assign RX and TX buffers

o In the Gateway example this is done in the file dcsdriver-conf_GatewayNode1.c via TDDLL_FixedTxBufferAssignment and TDDLL_FixedRxBufferAssignment.

- Include initialisation code (chi file)

o In the Gateway example this is done in the file chi_GatewayNode1.c via ttStatusType ttInitCHIOfController0(void)

5.5 License Agreement

DECOMSYS::COMMSTACK Library License Agreement

The DECOMSYS::COMMSTACK Library is provided by DECOMSYS. It is the property of that company. Fujitsu Microelectronics Europe GmbH expressly disclaims all warranty, expressed, implied or statutory, including but not limited to any implied warranty of merchantability, fitness for a particular purpose or non-infringement.

The DECOMSYS::COMMSTACK Library must be used with Fujitsu Evaluation boards, only.

For any other purposes, including but not limited to licensing issues, technical problems contact DECOMSYS.

Contact Details:

DECOMSYS - Dependable Computer Systems,

Hardware und Software Entwicklung GmbH

Stumpergasse 48/28

A-1060 Vienna, Austria



Web: http://www.decomsys.com

FLEXRAY-FPGA-EVA-KIT-369 Chapter 6 FlexConfig Configuration Tool


6 FlexConfig Configuration Tool The FlexConfig Tool is a configuration tool for FlexRay communication controllers. With FlexConfig, all necessary parameters are set via a convenient Windows application. Every parameter is checked against general limits or specific constraints so no faulty configuration is possible.

This special version for the FLEXRAY-FPGA-EVA-KIT-369 is limited to 4 ID’s for each cluster. Find the version at FlexRay CD (since CD1.3) in Software/FlexConfig folder.

The FlexConfig Tool is provided by the company TransferZentrum Mikroelektronik (TZM).

6.1 Installing FlexConfig The Flexconfig Software is on FlexRay CD at FlexConfig folder. Before installing the Tool read the readme.txt file inside the installation folder.

Execute the setup.exe in the installation folder and follow the wizard.

6.2 Project files for FlexRay Software-examples Find the project files (*.pro) for the FlexConfig Tool at FlexRay CD in ‘FlexConfig/projects’ folder.

For following examples a project file exist:

- Gateway

- Gateway-dyn

6.3 License Agreement

DISCLAIMER OF FUJITSU MICROELECTRONICS EUROPE GMBH

FLEXCONFIG SOFTWARE LICENSE AGREEMENT

THE FLEXCONFIG SOFTWARE IS THE INTELLECTUAL PROPERTY OF TRANSFERZENTRUM MIKROELEKTRONIK AND WILL BE EXCLUSIVELY PROVIDED BY TRANSFERZENTRUM MIKROELEKTRONIK. FUJITSU MICROELECTRONICS EUROPE GMBH EXPRESSLY DISCLAIMS ALL WARRANTY, EXPRESSED, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY’S INTELLECTUAL PROPERTY.

FOR ANY OTHER PURPOSES, INCLUDING BUT NOT LIMITED TO LICENSING ISSUES AND/OR TECHNICAL PROBLEMS PLEASE CONTACT TRANSFERZENTRUM MIKROELEKTRONIK.

CONTACT DETAILS:

TRANSFERZENTRUM MIKROELEKTRONIK

FLEXRAY-FPGA-EVA-KIT-369 Chapter 6 FlexConfig Configuration Tool


ROBERT-BOSCH-STRAßE 6

D-73037 GÖPPINGEN, GERMANY

WEB: HTTP://WWW.TZM.DE

FLEXRAY-FPGA-EVA-KIT-369 Chapter 7 FlexRay Evaluation Board


7 FlexRay Evaluation Board

7.1 Overview The FlexRay Evaluation Board is a Sub board of FLEXRAY-FPGA-EVA-KIT-369 Evaluation Kit. It is used by the combination with MB91F369CPU board.

The FlexRay board consists of several boards.

- Main board

- FlexRay Evaluation daughter board

The FlexRay Evaluation Main Board is used as baseboard providing plug in for the FlexRay Evaluation Daughter Board with the FlexRay controller and two physical layer modules with FlexRay transceiver. The physical layer modules are optional components that need to be ordered separately from third party (i.e. TZM). The FlexRay Evaluation Main Board carries the power supply for all secondary voltages and provides the connectivity to the host processor and both FlexRay channels.

The FlexRay Evaluation Daughter Board is currently using an FPGA as FlexRay controller device. The default physical layer for FlexRay communication is provided by two RS485 transceivers. These transceivers can be bypassed with physical layer modules that plug into the provided terminals on the FlexRay Evaluation Main Board. Instead of the default RS485 transceiver a true physical layer representation can be established then.

7.1.1 Features FlexRay Evaluation Main Board

• DC Power-supply circuit for the entire system

• Supports FlexRay Controller FPGA and stand-alone version via Daughter Board 1 exchange.

• Flexible transceiver selection

o RS485 Transceiver on the board (default)

o FlexRay transceiver via “Daughter Board 2"

• Terminal layout of Daughter board 2 has compatible terminal layout of “FlexPL Module TJA1080/UJA1081” manufactured by TZM

• The switch control of "WAKE, EN, STBN signal" between CC and Bus Driver can be done.

• 2 Channel carries the outside interface Dsub-9 (male) for FlexRay Bus.

• External bus connector for the CPU Board Interface connection.

• BUS Level Converter (3.3V-5.0V) that does the change of all the signals of External bus Connector.

• All the pins (except for the power supply) of External bus connector are connected with Daughter Board 1.


• SPI Interface between DaughterBoard1 and DaughterBoard2

• 16 LEDs by the control of Daughter Board 1.

• Header pin of 32 IOPORTs by the control of Daughter Board 1



• The reset circuit between FlexRay Evaluation Board and CPU Board can be divided.

• Board size is 250mm * 178mm.

7.1.2 Features FlexRay Evaluation Daughter Board

• Hosted on FlexRay Evaluation Main Board

• The interface of all the pins (except for the power supply) of External bus connector for CPU Board Interface is possible

• FPGA: ALTERA Device Stratix EP1S25F672C

• Hosted Configuration FLASHROM: ALTERA Device EPC16QC100

• Configuration FLASHROM can be written in via JTAG


• 16 LEDs on Main Board connected to FPGA

• 32 IOPORTs on Main Board connected to FPGA

• Board size is 90mm * 90mm

7.1.3 Board Configuration

This section shows the available board configuration for this system.

CPU BoardFlexRay Evaluation Board

Daughter Board1

Main Board

level

Conve

rter

DaughterBoard 2

Option

This connector has compatible terminallayout of “ FlexPL Module TJA1080/UJA1081” manufactured by TZM .

Ach

BchRS485

RS485

Figure 4:FlexRay Evaluation kit configuration



Available FlexRay Evaluation Board Available CPU Board

Main Board Daughter Board1

MB91F369 Daughter Board1 for FPGA

MB91F460 series (planning)

Main Board

Daughter Board1 for ASSP (planning)

Table 1: Available boards

7.2 Jumpers and Switches This chapter describes all jumpers and switches, which can be modified, on the “FlexRay Evaluation Kit”. The default setting is shown with a grey shaded area. All jumpers and switches are named directly on the board, so it is very easy to set the jumpers according to the features.

7.2.1 Main board

7.2.1.1 Power Supply Voltage

No. Item PartNo. Setting Description AXIS

1-2 Power ON 1 Power supply voltage

(switch) SW6 2-3 Power OFF

F1

ON (Closed) selected 1.2V 2 J37

OFF (Open) unselected 1.2V E5



ON (Closed) selected 1.8V 4

VccINT_1 power supply(jumper)

J35 OFF (Open) unselected 1.8V

E5



ON (Closed) selected 2.5V 6

VccINT_2 power supply(jumper)

J38 OFF (Open) unselected 2.5V

E6

ON (Closed) When VccINT_1 was selected in 1.2V or 1.5V.

7VccINT_1 supply voltage Monitor (jumper)

J41 OFF (Open) When VccINT_1 was

selected in 1.8V.

E1

8 PullUp Voltage for Daughter J76 1-2 selected 3.3V E1




Board1 (jumper) 2-3 selected 5.0V

1-21 selected 3.3V 9 PullUp Voltage of Bus Switch

for CPU Board (jumper) J71 2-3 selected 5.0V

A8

1-2 selected 3.3V 10 PullUp Voltage of Bus Switch

for Daughter Board1 (jumper) J72 2-3 selected 5.0V

A8

ON (Closed) unified digital VCC 11 A_VccINT_1 Analog Power

supply for FPGA (jumper) J31 OFF (Open) separated analog VCC

A7

ON (Closed) unified digital GND 12 A_GND Analog Grand for

FPGA (jumper) J33 OFF (Open) separated analog GND

A7

ON (Closed) connected Vbat 13 Vbat Power for Daughter

board2 (jumper) J32 OFF (Open) unconnected Vbat

E3

ON (Closed) connected 5V0 14 Vcc Power for Daughter

board2 (jumper) J42 OFF (Open) unconnected 5V0

E2

1-2 connected 3V3 15 Vio Power for Daughter board2

(jumper) J73 2-3 connected 5V0

E2

1-2 connected 3V3 16 V3V3 Power for Daughter

board2 (jumper) J74 2-3 connected 5V0

E2

1-2 connected VccINT_1 17 V1V8 Power for Daughter

board2 (jumper) J75 2-3 connected VccINT_2

E1

ON (Closed) Power supply 18 Power supply for LED of Power

supply Monitor (jumper) J29 OFF (Open) No Power supply

F2

ON (Closed) Power supply 19 Power supply for LEDs

(jumper) J28 OFF (Open) No Power supply

A3

Table 2: FlexRay board power supply jumper settings

1 Select 5.0V when ICE by the CPU board is used.



7.2.1.2 Reset This chapter describes the Reset connection of FlexRay board and the CPU board.

By default the Reset signal of the CPU board is connected to the FlexRay Main board reset signal. To ensure proper reset signal of all components.


1 Reset Switch (switch) SW7 OFF ON / OFF A4

ON (Closed) CPU Board reset enable 2 Reset signal from/to CPU

Board (jumper) J34OFF (Open) CPU Board reset disable

F2

Table 3: FlexRay main board, reset settings

7.2.1.3 Level Converter (BUS Switch)


ON (Closed) forced connect Mode 1 Bus Enable of BUS Switch

(jumper) J1OFF (Open) CPU Board supply Monitor Mode

A7

Table 4: FlexRay main board, BUS Switch

7.2.1.4 Bus Driver Interface (channel Ach)

In this chapter the Jumper settings of transceiver settings are listed.

By default RS485 jumper settings are set. When using FlexRay transceiver using daughter board 2 interface, see chapter 7.2.1.4.2. Changes are highlighted in red colour.

7.2.1.4.1 Bus Driver device using onboard RS485


WAKE signal (SW1/1) OFF WAKE ON/OFF

EN signal (SW1/2) OFF EN ON/OFF

RSTN/STBN signal (SW1/3) OFF RSTN/STBN ON/OFF 1

Reserved (SW1/4)

SW1

OFF Reserved

A2

ON (Closed) TxD of RS485 enable 2 TXD of RS485 Transceiver

(jumper) J67OFF (Open) TxD of RS485 disable

E3

ON (Closed) RxD of RS485 enable 3 RXD of RS485 Transceiver

(jumper) J64OFF (Open) RxD of RS485 disable

E3




ON (Closed) TxEN of RS485 enable 4 TXEN of RS485 Transceiver

(jumper) J65OFF (Open) TxEN of RS485 disable

E3

ON (Closed) BP of RS485 enable 5 BP of RS485 Transceiver

(jumper) J45OFF (Open) BP of RS485 disable

C2

ON (Closed) BM of RS485 enable 6 BM of RS485 Transceiver

(jumper) J46OFF (Open) BM of RS485 disable

C2

ON (Closed) Termination of RS485 enable 7

Termination of RS485 Transceiver

(jumper) J47

OFF (Open) Termination of RS485 disable C1



(jumper) J48


ON (Closed) WAKE enable 9 WAKE between Daughter

Board 1 and BD (jumper) J8 OFF (Open) WAKE disable

D3

ON (Closed) INH1 enable 10 INH1 between Daughter Board

1 and BD (jumper) J10OFF (Open) INH1 disable

D3

ON (Closed) EN enable 11 EN between Daughter Board 1

and BD (jumper) J11OFF (Open) EN disable

D3

ON (Closed) RSTN/STBN enable 12

RSTN/STBN between Daughter Board 1 and BD

(jumper) J12

OFF (Open) RSTN/STBN disable D3

ON (Closed) SDI enable 13 SDI between Daughter Board 1

and BD (jumper) J13OFF (Open) SDI disable

D3

ON (Closed) SDO enable 14 SDO between Daughter Board

1 and BD (jumper) J14OFF (Open) SDO disable

D3

ON (Closed) SCK enable 15 SCK between Daughter Board

1 and BD (jumper) J15OFF (Open) SCK disable

D3

ON (Closed) SCSN enable 16 SCSN between Daughter

Board 1 and BD (jumper) J16OFF (Open) SCSN disable

E3

ON (Closed) Power supply 17 Power supply for LED of WAKE

(jumper) J9 OFF (Open) No Power supply

D3

Table 5: Flexray board RS485 Bus Driver device jumper settings (Ach)



7.2.1.4.2 Bus Driver device select the Daughter Board 2 using FlexRay transceiver (Ach)





Reserved (SW1/4)

SW1

OFF Reserved

A2

ON (Closed) TxD of RS485 enable 2 TXD of RS485 Transceiver

(jumper) J67OFF (Open) TxD of RS485 disable

E3

ON (Closed) RxD of RS485 enable 3 RXD of RS485 Transceiver

(jumper) J64OFF (Open) RxD of RS485 disable

E3

ON (Closed) TxEN of RS485 enable 4 TXEN of RS485 Transceiver

(jumper) J65OFF (Open) TxEN of RS485 disable

E3

ON (Closed) BP of RS485 enable 5 BP of RS485 Transceiver

(jumper) J45OFF (Open) BP of RS485 disable

C2

ON (Closed) BM of RS485 enable 6 BM of RS485 Transceiver

(jumper) J46OFF (Open) BM of RS485 disable

C2



(jumper) J47




(jumper) J48


ON (Closed) WAKE enable 9 WAKE between Daughter

Board 1 and BD (jumper) J8 OFF (Open) WAKE disable

D3

ON (Closed) INH1 enable 10 INH1 between Daughter

Board 1 and BD (jumper) J10OFF (Open) INH1 disable

D3

ON (Closed) EN enable 11 EN between Daughter Board

1 and BD (jumper) J11OFF (Open) EN disable

D3

ON (Closed) RSTN/STBN enable 12

RSTN/STBN between Daughter Board 1 and BD

(jumper) J12

OFF (Open) RSTN/STBN disable D3

ON (Closed) SDI enable 13 SDI between Daughter Board

1 and BD (jumper) J13OFF (Open) SDI disable

D3

ON (Closed) SDO enable 14 SDO between Daughter

Board 1 and BD (jumper) J14OFF (Open) SDO disable

D3

ON (Closed) SCK enable 15 SCK between Daughter

Board 1 and BD (jumper) J15OFF (Open) SCK disable

D3




ON (Closed) SCSN enable 16 SCSN between Daughter

Board 1 and BD (jumper) J16OFF (Open) SCSN disable

E3

ON (Closed) Power supply 17

Power supply for LED of WAKE

(jumper) J9

OFF (Open) No Power supply D3

Table 6: FlexRay board: Bus Driver device jumper settings for daughter board 2 (Ach)

NOTE:

When using FlexRay transceiver via daughter board 2 check also power supply jumpers in Table 2: FlexRay board power supply jumper settings

7.2.1.5 Bus Driver Interface (Bch)

By default RS485 jumper settings are set. When using FlexRay transceiver using daughter board 2 interface, see chapter 7.2.1.5.2. Changes are highlighted in red colour.

7.2.1.5.1 Bus Driver device using onboard RS485





Reserved (SW2/4)

SW2

OFF Reserved

A3

ON (Closed) TxD of RS485 enable

2 TXD of RS485 Transceiver (jumper) J70

OFF (Open) TxD of RS485 disable C3

ON (Closed) RxD of RS485 enable

3 RXD of RS485 Transceiver (jumper) J68

OFF (Open) RxD of RS485 disable C3

ON (Closed) TxEN of RS485 enable

4 TXEN of RS485 Transceiver(jumper) J69

OFF (Open) TxEN of RS485 disable C3

ON (Closed) BP of RS485 enable

5 BP of RS485 Transceiver (jumper) J58

OFF (Open) BP of RS485 disable A2

6 BM of RS485 Transceiver (jumper) J59 ON

(Closed) BM of RS485 enable A2




OFF (Open) BM of RS485 disable

ON(Closed) Termination of RS485 enable

7Termination of RS485

Transceiver (jumper)

J49OFF (Open) Termination of RS485 disable

A1

ON (Closed) Termination of RS485 enable



J57OFF (Open) Termination of RS485 disable

A1

ON (Closed) WAKE enable

9 WAKE between Daughter Board 1 and BD (jumper) J25

OFF (Open) WAKE disable B3

ON (Closed) INH1 enable

10 INH1 between Daughter Board 1 and BD (jumper) J22

OFF (Open) INH1 disable B3

ON (Closed) EN enable

11 EN between Daughter Board 1 and BD (jumper) J24

OFF (Open) EN disable B3

ON (Closed) RSTN/STBN enable

12 RSTN/STBN between

Daughter Board 1 and BD (jumper)

J27OFF (Open) RSTN/STBN disable

B3

ON (Closed) SDI enable

13 SDI between Daughter Board 1 and BD (jumper) J23

OFF (Open) SDI disable B3

ON (Closed) SDO enable

14 SDO between Daughter Board 1 and BD (jumper) J17

OFF (Open) SDO disable B3

ON (Closed) SCK enable

15 SCK between Daughter Board 1 and BD (jumper) J18

OFF (Open) SCK disable B3

ON (Closed) SCSN enable

16 SCSN between Daughter Board 1 and BD (jumper) J19

OFF (Open) SCSN disable B3

ON (Closed) Power supply

17 Power supply for LED of WAKE(jumper) J26

OFF (Open) No Power supply B3

Table 7: FlexRay board RS485 Bus Driver device jumper settings (Bch)



7.2.1.5.2 Bus Driver device select the Daughter Board 2 using Flexray transceiver (Bch)





Reserved (SW2/4)

SW2

OFF Reserved

A3

ON (Closed) TxD of RS485 enable

2 TXD of RS485 Transceiver (jumper) J70

OFF (Open) TxD of RS485 disable

C3

ON (Closed) RxD of RS485 enable

3 RXD of RS485 Transceiver (jumper) J68

OFF (Open) RxD of RS485 disable

C3

ON (Closed) TxEN of RS485 enable

4 TXEN of RS485 Transceiver(jumper) J69

OFF (Open) TxEN of RS485 disable

C3

ON (Closed) BP of RS485 enable

5 BP of RS485 Transceiver (jumper) J58

OFF (Open) BP of RS485 disable

A2

ON (Closed) BM of RS485 enable

6 BM of RS485 Transceiver (jumper) J59

OFF (Open) BM of RS485 disable

A2




J49OFF

(Open) Termination of RS485 disable A1




J57OFF

(Open) Termination of RS485 disable A1

ON (Closed) WAKE enable

9 WAKE between Daughter Board 1 and BD (jumper) J25

OFF (Open) WAKE disable

B3

ON (Closed) INH1 enable

10 INH1 between Daughter Board 1 and BD (jumper) J22

OFF (Open) INH1 disable

B3




ON (Closed) EN enable

11 EN between Daughter Board 1 and BD (jumper) J24

OFF (Open) EN disable

B3

ON (Closed) RSTN/STBN enable

12 RSTN/STBN between

Daughter Board 1 and BD (jumper)

J27OFF

(Open) RSTN/STBN disable B3

ON (Closed) SDI enable

13 SDI between Daughter Board 1 and BD (jumper) J23

OFF (Open) SDI disable

B3

ON (Closed) SDO enable

14 SDO between Daughter Board 1 and BD (jumper) J17

OFF (Open) SDO disable

B3

ON (Closed) SCK enable

15 SCK between Daughter Board 1 and BD (jumper) J18

OFF (Open) SCK disable

B3

ON (Closed) SCSN enable

16 SCSN between Daughter Board 1 and BD (jumper) J19

OFF (Open) SCSN disable

B3

ON (Closed) Power supply

17 Power supply for LED of WAKE(jumper) J26

OFF (Open) No Power supply

B3

Table 8: Bus Driver device jumper settings for daughter board 2 (Bch)

NOTE:

When using FlexRay transceiver via daughter board 2 check also power supply jumpers in Table 2: FlexRay board power supply jumper settings



7.2.1.6 Reserved Switch


1 INT Push Switch (Reserved) SW3 OFF

ON / OFF (This Switch is connected with

FlexRay Evaluation Daughter Board)A6

2 SWA Push Switch (Reserved) SW4 OFF



3 SWB Push Switch (Reserved) SW5 OFF



Table 9: Reserved Switches

7.2.2 FlexRay Evaluation Daughter Board Settings

7.2.2.1 Operating Mode Jumper The mode of operation for FPGA is selected with four jumpers. Their function is listed in the table below. The jumpers are located on the FlexRay Evaluation Daughter Board.


ON (Closed) 0 (Low) 1 MOD0

(jumper) J13OFF (Open) 1 (High)

A3



A3



A3

1-2 selected a SMA connector of Main Board4 Clock Select

(jumper) J12-3 selected an OSC of Daughter Board 1

B3

Table 10: FPGA operation mode setting



7.2.2.2 FPGA Configuration Jumper Change settings when updating the FPGA content. By default Jumper set for run mode.


ON (Closed) Flash ROM 0Page setting 1 PGM0

(jumper) J10OFF (Open) Flash ROM 1Page setting

C2

ON (Closed) JTAG disable 2 TRST

(jumper) J7 OFF (Open) JTAG enable

C2

ON (Closed) 100mS setting 3 PORSEL

(jumper) J8 OFF (Open) 2mS setting

C2

ON (Closed) serial data mode 4 MSEL1

(jumper) J9 OFF (Open) parallel data mode

C2

Table 11: FlexRay Evaluation Daughter Board: FPGA configuration jumper

7.3 Header for Debug Signals

7.3.1 FlexRay Evaluation Main Board Check Pins

All pins provided to check the board functionality are described in this chapter.

7.3.1.1 Power supply voltage

No. Item PartNo. Description AXIS

1 Checker pin (Vbat) TP25 Vbat (DCin) E3

2 Checker pin (9V) TP26 9V E7

3 Checker pin (5V) TP27 5V E3

4 Checker pin (3.3V) TP28 3.3V E4

5 Checker pin (VccINT_2) TP30 VccINT_2 (1.8/2.5V) E6

6 Checker pin (VccINT_1) TP29 VccINT_1 (1.2/1.5/1.8V) E5

7 Checker pin (GND) TP31 GND B4

8 Checker pin TP32 GND A8




(GND)

9 Checker pin (GND) TP33 GND E8

10 Checker pin (GND) TP34 GND E4

11 Header pin (GND) J40 GND A3

12 Checker pin (analog VccINT_1) TP35 Analog VccINT_1 ( 1.2/1.5/1.8V) A7

13 Checker pin (analog GND) TP37 Analog GND A7

14 Checker pin (analog GND) TP38 Analog GND A7

15 Header pin (analog GND) J43 Analog GND A6

16 Power supply for LED D26 5V F2

Table 12: FlexRay Main board: Power supply check pins

Via above listed pins it is possible to check correct power supply of the FPGA main board.

7.3.1.2 Mon 1 (J54) Connector (External Bus Interface) At Connector J54 the Address and Data lines of the external Bus Interface are routed. Via this pins it is possible to check / monitor the external Bus Interface. Additionally I/O port pins PS[7:0] are connected.

PIN No Description

PIN No Description

1 Ext. BUS Data0 41 Ext. BUS Address8













PIN No Description

PIN No Description














25 Ext. BUS Data24 65 IOPort PS0








33 Ext. BUS Address0 73 B01








Table 13: FPGA Main board: Mon 1 (J54) Connector (Bus I/F) pins



7.3.1.3 Mon 2 (J55) Connector At MON 2 (J55) Signal pins of external Bus Interface and additionally I/O ports of FPGA are connected.

PIN No Description PIN

No Description

1 B09 41 IOPORT2

2 B10 42 IOPORT3

3 B11 43 IOPORT4

4 C11 44 IOPORT5

5 B12 45 IOPORT6

6 B13 46 IOPORT7

7 C16 47 IOPORT8

8 BCLK 48 IOPORT9

9 CS0 49 IOPORT10

10 CS1 50 IOPORT11

11 CS2 51 IOPORT12

12 CS3 52 IOPORT13

13 CS4 53 IOPORT14

14 CS5 54 IOPORT15

15 CS6 55 IOPORT16

16 RDY 56 IOPORT17

17 BGRNT 57 IOPORT18

18 BRQ 58 IOPORT19

19 RDX 59 IOPORT20

20 WR0 60 IOPORT21

21 WR1 61 IOPORT22

22 WR2 62 IOPORT23

23 WR3 63 IOPORT24

24 AS 64 IOPORT25

25 ALE 65 IOPORT26

26 DREQ0 66 IOPORT27

27 DACK0 67 IOPORT28

28 DEOP0 68 IOPORT29

29 InterruptA 69 IOPORT30

30 I2C(SDA) 70 IOPORT31

31 InterruptB 71 SWBDA

32 I2C(SCL) 72 SWBDB




No Description

33 Uart-RxD 73 SWINT

34 Uart-TxD 74 GND

35 Uart-Clock 75 GND

36 Reset 76 GND

37 SCLK 77 GND

38 GND 78 GND

39 IOPORT0 79 GND

40 IOPORT1 80 GND


7.3.1.4 Mon 3 (J56) connector Via Mon 3 (J56) connector it is possible to monitor the FlexRay bus signals.


No Description

1 WAKE_A 21 ERRN/INTN_B

2 MT_A 22 INH1_B

3 BGT_A 23 TXD_B

4 ERRN/INTN_A 24 RXD_B

5 INH1_A 25 BGE_B

6 TXD_A 26 RXEN_B

7 RXD_A 27 TXEN_B

8 BGE_A 28 EN_B

9 RXEN_A 29 RSTN/STBN_B

10 TXEN_A 30 ARM_B

11 EN_A 31 SDI_B

12 RSTN/STBN_A 32 SDO_B

13 ARM_A 33 SCK_B

14 SDI_A 34 SCSN_B

15 SDO_A 35 GND

16 SCK_A 36 GND

17 SCSN_A 37 GND

18 WAKE_B 38 GND

19 MT_B 39 GND

20 BGT_B 40 GND




7.3.2 Daughter Board 1

Following functionality at daughter board are routed to pins / connectors enabling monitoring of these functions/signals.

7.3.2.1 Power supply voltage Following pins at daughter board 1


1 Checker pin(5V) TP53 5V A3

2 Checker pin(3.3V) TP54 3.3V B3

3 Checker pin(1.5V) TP55 1.5V A1

4 Checker pin(GND) TP50 GND A1

5 Checker pin(GND) TP51 GND C3

6 Checker pin(analog 1.5V) TP56 Analog 1.5V A1

7 Checker pin(analog GND) TP52 Analog GND A3

5 Checker pin(GND) TP51 GND C3

6 Checker pin(analog 1.5V) TP56 Analog 1.5V A1

7 Checker pin(analog GND) TP52 Analog GND A3

Table 16: FlexRay daughter board 1: Power supply monitor pins

7.3.2.2 IOPORT Monitor J15 (masked part)


No Description

1 n.c 11 CONF_DONE

2 DATA0 12 NCONFIG

3 DATA1 13 INIT_DONE

4 DATA2 14 NCEO

5 DATA3 15 TDI

6 DATA4 16 TRST

7 DATA5 17 M_SEL1

8 DATA6 18 PORSEL

9 DATA7 19 GND

10 NSTATUS 20 GND

Table 17: FlexRay daughter board 1: IO Port Monitor (J15) pins



There are no connectors soldered at J15. At this Connector additional I/O ports of the FPGA are connected which are not connected to the main board via Jumper J2, J3, J4 or J5.

These ports are unused.

7.3.2.3 Configuration Monitor J16 (masked part)


No Description

1 IOPORT32 17 IOPORT48













14 IOPORT45 30 GND

15 IOPORT46 31 GND

16 IOPORT47 32 GND

Table 18: FlexRay daughter board 1: J16 pins There are no connectors soldered at J15. At this Connector additional I/O ports of the FPGA are connected which are not connected to the main board via Jumper J2, J3, J4 or J5.

These ports are unused.



7.4 Connectors

7.4.1 Power Connector (J30)

The DC Jack J30 is used to connect an external regulated DC power supply voltage (12V-20V DC) to the evaluation board. (It is recommended to use 12V to keep the power dissipation to a minimum.)

＋ー 12

Figure 5: Power Connector (J30) (EIAJ RC5320A Type5) Centre is connected to Positive Voltage supply (+).

Shield is connected to ground (GND)

7.4.2 FlexRay Bus Connector P1, P2

FlexRay Bus Connector P1 and P2 are used for FlexRay BUS Interface through the 9-pin D-Sub male connector. The following diagram shows the connection of the 9-pin D-Sub male connector.

1 5

6 9

BM

BP

GND common

Figure 6: 9-pin D-Sub male Connector (Top View) Note:

On the FPGA main board terminal resistors are onboard for RS485 level transmission.

Select / unselect the terminal resistor via Jumper (Ach: J47, J48 / Bch: J49, J57).

7.4.3 Daughter Board 1 Connectors J2, J3, J4, J5

Via the Daughter board 1 Connectors J2, J3, J4 and J5 the connection between FPGA Main board and FPGA daughter board 1 is established.

Jumper J2, J3 and J4 includes all pins related to CPU board connection.

Jumper J5 includes all pins related to FlexRay transceiver side. RS385 or FlexRay transceiver via FlexRay daughter board 2 connectors.



PIN No Connector No1

J2

Connector No2

J3

Connector No3

J4

Connector No4

J5

1 Ext. BUS Data0 IOPort PS0 GND IOPORT00

2 Ext. BUS Data1 IOPort PS1 GND IOPORT0１

3 Ext. BUS Data2 IOPort PS2 WAKE_A IOPORT02

4 Ext. BUS Data3 IOPort PS3 MT_A IOPORT03

5 GND GND BGT_A GND

6 5.0V 5.0V GND 3.3V

7 Ext. BUS Data4 IOPort PS4 GND IOPORT04

8 Ext. BUS Data5 IOPort PS5 ERRN/INTN_A IOPORT05

9 Ext. BUS Data6 IOPort PS6 INH1_A IOPORT06

10 Ext. BUS Data7 IOPort PS7 TXD_A IOPORT07

11 Ext. BUS Data8 CS0 RXD_A IOPORT08

12 Ext. BUS Data9 B01 BGE_A IOPORT09

13 Ext. BUS Data10 GND RXEN_A IOPORT10

14 Ext. BUS Data11 3.3V TXEN_A IOPORT11

15 GND CS1 EN_A GND

16 3.3V CS2 RSTN/STBN_A 5.0V

17 Ext. BUS Data12 B02 GND IOPORT12

18 Ext. BUS Data13 CS3 GND IOPORT13

19 Ext. BUS Data14 CS4 ARM_A IOPORT14

20 Ext. BUS Data15 B03 SDI_A IOPORT15

21 Ext. BUS Data16 GND SDO_A IOPORT16

22 Ext. BUS Data17 5.0V SCK_A IOPORT17

23 Ext. BUS Data18 CS5 SCSN_A IOPORT18

24 Ext. BUS Data19 CS6 GND IOPORT19

25 GND B04 GND GND

26 5.0V RDY WAKE_B 3.3V

27 Ext. BUS Data20 BGRNT MT_B IOPORT20

28 Ext. BUS Data21 B05 BGT_B IOPORT21

29 Ext. BUS Data22 GND GND IOPORT22

30 Ext. BUS Data23 3.3V GND IOPORT23

31 Ext. BUS Data24 BRQ ERRN/INTN_B IOPORT24

32 Ext. BUS Data25 RDX INH1_B IOPORT25

33 Ext. BUS Data26 B06 TXD_B IOPORT26

34 Ext. BUS Data27 WR0 RXD_B IOPORT27




J2

Connector No2

J3

Connector No3

J4

Connector No4

J5

35 GND 5.0V BGE_B GND

36 3.3V WR1 RXEN_B 5.0V

37 Ext. BUS Data28 B07 TXEN_B IOPORT28

38 Ext. BUS Data29 WR2 EN_B IOPORT29

39 Ext. BUS Data30 5.0V RSTN/STBN_B IOPORT30

40 Ext. BUS Data31 WR3 GND IOPORT31

41 Ext. BUS Address0 B08 GND VccINT_2

42 Ext. BUS Address1 AS ARM_B VccINT_2

43 Ext. BUS Address2 3.3V SDI_B VccINT_2

44 Ext. BUS Address3 ALE SDO_B VccINT_2

45 GND B09 SCK_B VccINT_2

46 5.0V GND SCSN_B VccINT_2

47 Ext. BUS Address4 CLK GND VccINT_2

48 Ext. BUS Address5 5.0V GND VccINT_2

49 Ext. BUS Address6 DREQ0 LED0 VccINT_2

50 Ext. BUS Address7 B10 LED1 VccINT_2

51 Ext. BUS Address8 DACK0 LED2 VccINT_2

52 Ext. BUS Address9 3.3V LED3 VccINT_2

53 Ext. BUS Address10 DEOP0 LED4 VccINT_2


55 GND C11 LED6 VccINT_1

56 3.3V InterruptA LED7 VccINT_1

57 Ext. BUS Address12 GND GND VccINT_1

58 Ext. BUS Address13 B12 GND VccINT_1

59 Ext. BUS Address14 I2C(SDA) LED8 VccINT_1

60 Ext. BUS Address15 InterruptB LED9 VccINT_1

61 Ext. BUS Address16 GND LED10 VccINT_1


63 Ext. BUS Address18 I2C(SCL) LED12 VccINT_1




J2

Connector No2

J3

Connector No3

J4

Connector No4

J5

64 Ext. BUS Address19 Uart-RxD LED13 VccINT_1

65 GND VccINT_2 LED14 VccINT_1

66 5.0V VccINT_2 LED15 GND

67 Ext. BUS Address20 Uart-TxD GND GND

68 Ext. BUS Address21 VccINT_2 GND AGND

69 Ext. BUS Address22 VccINT_2 VccINT_1 A_VccINT_1

70 Ext. BUS Address23 Uart-Clock VccINT_1 AGND


72 Ext. BUS Address25 Reset VccINT_1 AGND


74 Ext. BUS Address27 C16 VccINT_1 AGND

75 GND VccINT_2 VccINT_1 A_VccINT_1

76 3.3V GND VccINT_1 GND

77 Ext. BUS Address28 MCLK VccINT_1 GND

78 Ext. BUS Address29 GND VccINT_1 SWB

79 Ext. BUS Address30 VccINT_2 VccINT_1 SWA

80 Ext. BUS Address31 VccINT_2 VccINT_1 SWINT

Table 19: Daughter Board 1 Connectors J2, J3, J4, J5

7.4.4 Daughter Board 2 Connectors J6, J7, J20, J21

The Daughter board 2 Connectors (Ach: J6, J7; Bch: J20,J21) have pin compatible layout as the “FlexPL Module TJA1080/UJA1081” manufactured by TZM.

When using FlexRay transceiver instead of RS485 transceiver, remove Jumper to RS485 transceiver, plug FlexRay module to main board.



Pin Signal Name Description Remark

1 WAKE Local wake output VBAT level

2 BP Transceiver bus line 1 Flexray-BUS

3 BM Transceiver bus line 2 Flexray-BUS

4 Vio IO voltage level output 3.3V supply

5 BGT BG tick signal 3.3V level

6 MT BG Macrotick signal 3.3V level

7 ERRN/INTN Error/Interrupt intput 3.3V �evel

8 INH1 Inhibit intput VBAT level

9 n.c. - -

10 TxD Transmit intput 3.3V level

11 INH2 Inhibit intput unused

12 RxD Receive data intput 3.3V level

13 Vcc Supply voltage +5V

14 GND Ground transceiver -

15 Vbat Battery supply -

Table 20: Daughter Board 2 Connectors J6, J20


1(30) RES Reserved -

2(29) SCSN SPI slave select output 3.3V level

3(28) SCK SPI clock output 3.3V level

4(27) SDO SPI data output 3.3V level

5(26) SDI SPI data input 3.3V level

6(25) ARM Arm signal input 3.3V level

7(24) RSTN/STBN BG reset output /STBN output to TJA1080 for power modes

3.3V levelUJA1081:RSTN -> Bus Guardian

ResetTJA1080:STBN -> Standby

8(23) EN BD enable output (used for power modes) 3.3V level

9(22) TXEN Transmit enable output 3.3V level

10(21) RXEN Receive enable input 3.3V level

11(20) BGE BG enable output 3.3V level

12(19) GND Ground -

13(18) V1V8 1.8V supply unused

14(17) GND Ground -




15(16) V3V3 3.3V I/O supply -

Table 21: Daughter Board 2 Connectors J7, J21

7.4.5 SMA Connector (J53)

Via SMA Connector (J53) a Function Generator, etc, can be connected. E.g. as clock monitor function.

7.4.6 JTAG Connector J6 (JTAG of Daughter Board 1 for FPGA)

Via JTAG Connector (J6) of Daughter Board 1 it is possible to update FPGA configuration.

1

2

3

4

5

6

7

8

9

10

Figure 7: JTAG Connector J6 (TOP View)

7.4.7 CPU Board Connectors J50, J51

The CPU board interface signals are connected to J50 and J51. Two connectors are used, 96-pin VG-connector (J50) and 48-pin VG-connector (J51).

Pin Name Description Pin Name Description Pin Name Description

A1 2.5V B1 2.5V C1 2.5V

A2 3.3V B2 3.3V C2 3.3V

A3 5.0V B3 5.0V C3 NC.

A4 GND B4 GND C4 GND

A5 D0 Ext. Bus DATA bit0 B5 D1 Ext. Bus DATA bit1 C5 D2 Ext. Bus DATA bit2













A15 D30 Ext. Bus DATA bit30 B15 D31 Ext. Bus DATA bit31 C15 GND


A17 A0 Ext. Bus Address bit0 B17 A1 Ext. Bus Address bit1 C17 A2 Ext. Bus Address bit2




A21 A12 Ext. Bus Address bit12 B21 A13 Ext. Bus Address bit13 C21 A14 Ext. Bus Address

bit14


bit17


bit20


bit23


bit26


bit29

A27 A30 Ext. Bus Address bit30 B27 A31 Ext. Bus Address bit31 C27 GND

A28 PortS0 IO Port PS0 B28 PortS1 IO Port PS1 C28 PortS2 IO Port PS2

A29 PortS3 IO Port PS3 B29 PortS4 IO Port PS4 C29 PortS5 IO Port PS5

A30 PortS6 IO Port PS6 B30 PortS7 IO Port PS7 C30 GND

A31 2.5_2V B31 2.5_3V C31 GND


Table 22: CPU Board Connector J50 (96-pin DIN Connector)

ABC

32 1･･････････････････････････････････

Figure 8: Pin Layout of the 96-polar DIN Connector




A01 CS0 Ext. Bus: Chip Select0 B01 Res. C01 CS1 Ext. Bus: Chip Select1



A04 CS6 Ext. Bus: Chip Select6 B04 Res. C04 RDY Ext. Bus : Bus Ready

A05 BGRNT

Ext. Bus: Bus Grant B05 Res. C05 BRQ Ext. Bus: Bus Request

A06 RDX Exit. Bus: Read Enable B06 Res. C06 WR0 Exit Bus: Write Enable0

A07 WR1 Exit Bus: Write Enable1 B07 Res. C07 WR2 Exit Bus: Write Enable2

A08 WR3 Exit Bus: Write Enable3 B08 Res. C08 AS Ext. Bus: Addres strobe

A09 ALE Exit Bus: Address Latch Enable(It isn't uesd with 91360 series)

B09 Res. C09 CLK Ext. Bus: Bus Clock

A10 DREQ0

Ext. Bus: DMA Request0

B10 Res. C10 DACK0 Ext. Bus: DMA ACK

A11 DEOP0

Ext. Bus: DMA EOP0 B11 Res. C11 Res.

A12 InterruptA

InterruptA B12 Res. C12 I2C(SDA) I2C SDA

A13 InterruptB

InterruptB B13 Res. C13 I2C(SCL) I2C SCL

A14 Uart-RxD

Uart-RxD B14 9.0V Power Supply(9V) to the CPU board

C14 Uart-TxD Uart-TxD

A15 GND B15 9.0V Power Supply(9V) to the CPU board

C15 Uart-Clock

Uart-Clock

A16 Reset B16 9.0V Power Supply(9V) to the CPU board

C16 Res.

Table 23: CPU Board Connector J51 (48-polar DIN Connector)

ABC

16 1･････････････････

Figure 9: Pin Layout of the 48-pin DIN Connector



7.5 Programming the FPGA

This section explain s how to update FPGA content. To program the Altera FPGA the Software Quartus II 4.2 is required. This software is available at Alteras Webpage. Additionally a programmer is needed:

• ByteBlaster II / ByteBlasterMV (Parallel Port TYPE) • USB-Blaster (USB TYPE) • MasterBlaster (RS-232 TYPE / USB TYPE)

Programming steps

a. Connect the Programmer via JTAG Connector J6 at Daughter Board 1 with FPGA

b. Open the TRST of Daughter Board 1 (disconnect J7 jumper) the enable JTAG mode

c. Power-on FPGA Main board d. Start Programmer Software (QuartusII) at PC e. To select the FPGA Programmer type use “Hardware Setup” button and

select Hardware Settings TAB (5.1) Select Programmer in Currently selected Hardware field (5.2) A list of installed Programmer is shown in Available Hardware Items (5.3) If no Hardware is already installed, add Hardware via “Add Hardware” button

f. Use “Auto detect button” to detect FPGA and Configuration device i. EPC16 Configuration Device and EP1S25 FPGA should be detected

g. Load new *.pof file to program the configuration device (EPC16) i. Double click in “File” entry or use “Add File” button

h. Check “Program”, “Verify” and “Blank check” i. Use “Start button” to start reprogramming

FLEXRAY-FPGA-EVA-KIT-369 Chapter 8 CPU369 board


8 CPU369 board

8.1 Overview

The Fujitsu CPU369-Modul is a low cost multifunctional evaluation board for Fujitsu’s 32-Bit Flash microcontroller MB91F369 that makes it easy to evaluate and demonstrate almost all features of the microcontroller. It can be used stand alone for software development and testing as a simple target board. It gives you the possibility to develop and evaluate applications the new FlexRay-controller family. Its modular concept makes it available to use with FlexRay Communication Controller sub boards or one of several graphic device sub boards just by plugging them to the CPU board.

The board allows the designer immediately to start the software development and perform debugging before his own final target system is available.

8.2 Features • MCU MB91F369

• 2MB external Debugging RAM

• 4MHz crystal

• DC Power supply circuit (incl. Test pins for VCC, GND, power LED and switch)

• 1 MB external Flash available for user code and constant data

• External Reset Button for MCU

• 2 Buttons for ext. Interrupt (USER_0 = ext. Interrupt0, USER_1 = ext. Interrupt1)

• MAX232 + DB9 (female) connector for internal UART

• CAN transceiver and DB9 (male) for internal CAN0

• 2 LEDs (on Port N)

• All peripheral pins are available by the connectors ‘Peripheral_1’ and ‘Peripheral_2’

• Sub board support

o 96pin + 48pin VG connector

8.3 Jumpers and Switches This chapter describes all jumpers and switches, which can be modified on the evaluation board. The default setting is shown with a grey shaded area. All jumpers and switches are named directly on the board by its meaning, so it is very easy to set the jumpers according to the features. For more information please refer to the Hardware Manual of the microcontroller and the Data Sheet of the Flash-ROM 29LV400TC.

8.3.1 Power Supply Voltage (SW1, JP11, JP12, JP13, JP14, JP15, JP25)

Switch setting Description

1 - 2 Power ON Power supply voltage (SW1)

2 - 3 Power OFF

Table 24: CPU369 board: Power supply Switch setting (SW1)



Jumper setting Description

ON (closed) Power supply 3V3 power supply (JP11)

OFF (open) NO Power supply

ON (closed) Power supply 5V0 power supply (JP12)


ON (closed) Voltage regulator enable Bypass Capacitor Pin (JP13)

OFF (open) Voltage regulator disable

ON (closed) Power supply Power supply for SMT (JP14)


ON (closed) Analogue Power supply 5V0 Power supply (JP15)

OFF (open) NO Analogue Power supply

ON (closed) Power supply Power supply voltage (SW1)


Table 25: CPU369 board: Power Supply Jumper settings

NOTE: The supply voltage for the core and the IO Pins must be set. Otherwise it could happen that the controller does not work correctly!

8.3.2 Operating Mode (SW2) settings

Jumper setting SW2 DIP switch setting Logical value Description

Boot signal (SW2/1) ON 0 (low) Boot signal

MD2 (SW2/2) ON 0 (low)



Boot signal (SW2/1) ON 0 (low)

Internal ROM mode

Table 26: CPU369 board: Operation mode settings

8.3.3 UART (JP21, JP22) settings


ON (closed) UART0 Output enable SOT_0 (JP21)

OFF (open) UART0 Output disable

ON (closed) UART0 Input enable SIN_0 (JP22)

OFF (open) UART0 Input disable

Table 27: CPU369 board: UART Jumper setting



Reserved Jumpers for future extensions:

Description

SIN_2 (JP7) UART2 Input enable

SOT_2 (JP8) UART2 Output enable

UART2 clock (JP9) UART2 clock enable

Table 28: CPU 369 board: reserved UART settings

8.3.4 Chip select enable for FLASH (JP10)

CS Jumper setting Description

CS2 closed 1-2 Ext. Flash – Chip-Select2

CS3 closed 2-3 Ext. Flash – Chip-Select3

Table 29: CPU 369 board: external Flash CS setting

8.3.5 Hardware Standby (JP16)


HSTX(JP16) 1-2 HSTX request is released

2-3

Table 30: CPU369 board: Hardware standby jumper setting

8.3.6 Clock Select (JP17, JP18, JP19, JP20)

Select which clock signals on CPU board should be connected to MCU.

Signal Jumper setting Description

1-2 Clock enable SELCLK (JP17)

2-3 Clock disable

1-2 4MHz clock enable 4MHz clock

(JP18) 2-3 4MHz clock disable

1-2 32kHz clock enable 32kHz clock

(JP19) 2-3 32kHz clock disable

1-2 Low pass filter for clock enable Low pass filter

(JP20) 2-3 Low pass filter for clock disable

Table 31: CPU369 board: Clock selection jumper



8.3.7 CAN controller interface (JP23, JP24)

When using CAN interface close this jumpers to connect MCU CAN RX-,TX-signals to CAN transceiver onboard.


ON (closed) Transmit data enable CAN transmit

(JP23) OFF (open) Transmit data disable

ON (closed) Receive data enable CAN receive

(JP24) OFF (open) Receive data disable

Table 32: CAN interface Jumper (JP23, JP24)

8.3.8 Solder Bridges JP1 and JP2 on MCU top module

Close solder jumper JP1 and JP2 at CPU module, to connect SOT3 and SCK3 port to onboard LED0 and 1. By default jumpers are open.


ON (closed) LED0,1 on port N enabled LED / SIO3 select(JP1,2)

OFF (open) SIO3 (SOT3,SCK3) enabled

Table 33: CPU369 board: MCU module URAT / LED selection

8.4 Header for Debug Signals

8.4.1 Power supply voltage (JP1, JP2, JP3, JP4, JP5, JP6)

All power supply voltage levels can be checked via these jumpers. Two pins of the jumpers are connected to GND the other two to the mentioned power supply level.

NOTE:

In case of voltage supply via FlexRay Main board, voltage at Jumper JP1 is 9V !



No. Item PartNo. Description

1 Checker pin (12V) JP1 12V – GND header

2 Checker pin (5V) JP2 5V – GND header

3 Checker pin (3.3V) JP3 3.3V – GND header

4 Checker pin (2.5V) JP4 2.5_1V – GND header



Table 34: CPU369 board: power supply header

8.4.2 MCU Peripheral Signals

8.4.2.1 Peripheral_1 (JH1) and Peripheral_2 (JH2) Header

Peripheral_1 Pin MB91F369 Pin Peripheral_2 Pin MB91F369 Pin 2 PH0 AN0 2 PM0 SGO

3 PH1 AN1 3 PM1 SGA 4 PH2 AN2 4 PN0 SOT4

5 PH3 AN3 5 PN1 SIN4 6 PH4 AN4 6 PN2 SCK4

7 PH5 AN5 7 PN3 SIN3

8 PH6 AN6 8 PN4 SOT3 (or LED0) 9 PH7 AN7 9 PN5 SCK4 (or LED1)

10 PG0 AN8 10 PO0 OCPA0 11 PG1 AN9 11 PO1 OCPA1

12 PG2 12 PO2 OCPA2

13 PG3 13 PO3 OCPA3 14 PG4 14 PO4 OCPA4

15 PG5 15 PO5 OCPA5 16 PG6 16 PO6 OCPA6

17 PG7 17 PO7 OCPA7 18 PI3 ATGX 18 PP2 TX1



Peripheral_1 Pin MB91F369 Pin Peripheral_2 Pin MB91F369 Pin 19 DA0 DA0 19 PP3 RX1 20 DA1 20 PP4

21 ALARM ALARM 21 PP5

22 PK4 INT4 22 PQ2 23 PK5 INT5 23 PQ3

24 PK6 INT6 24 PQ4 25 PK7 INT7 25 PQ5

26 PL0 26 PR0

27 PL1 27 PR1 28 PL2 28 PR2

29 PL3 29 PR3 30 PL4 30 PR4

31 PL5 31 PR5 32 PL6 32 PR6

33 PL7 33 PR7

Table 35: CPU369 board: Pin Assignment of Peripheral Jumpers (JH1, JH2)

Note:

Some of the Pins of Peripheral_1 and Peripheral_2 are not connected! This is because the original CPU board was designed for the MCU MB91F362 and this MCU has some additional resources (e.g. stepper-motor drivers, more ADC channels etc.). Please refer to the attached schematics which pins are left open.

Figure 10: CPU369 board: Pin Assignment of Peripheral Jumpers



8.5 Connectors

8.5.1 Power Connector J1

The following figure shows the power connection jack J1. This connector is used to connect an external unregulated DC power supply voltage (6V-9V DC) to the evaluation board.

Power Connector J1:

8.5.2 Serial Interface Connector P1

The following diagram shows the connection of the 9-pin D-Sub female connector P1, which is used for the serial interfaces.

Figure 11: CPU369 board: Serial Interface Connector P1

TXD is the transmit output, RXD is the receive input. The DTR signal is used as an input, which can be connected to generate a reset.

Note: CTS and RTS must be connected to each other because of the serial monitor debugger communication protocol – if you have problems with the monitor communication, please check if these two signals are connected to each other!

GND DTR RxD TxD

CTS RTS DSR

1

6

5

9

Shield is connected to positive voltage supply

Centre is connected to ground (GND)



8.5.3 CAN Interface Connector

The following diagram shows the connection of the 9-pin D-Sub male connector P2 which is used for the CAN interface.

For the CAN interface the resistor trimmer R18 is used to adjust the slew rate. Take care that the slew rate is adjusted according to the local environment (CAN network configuration, transfer rate)

CANL

CANH

1

6

5

9

FLEXRAY-FPGA-EVA-KIT-369 Chapter 9 Getting Started


9 Getting Started Make sure Softune Workbench for FR is installed on your PC and the “FLEXRAY-FPGA-EVA-KIT-369” is ready to use (power-on (J30/J52), serial connection (P1) to COM1 of the PC). Refer to Chapter 3 for details on the hardware and software installation.

9.1 Introduction to Softune Workbench Start Softune Workbench. Select <File> <Open Workspace> to load the first example “FPGA_standalone_flexray_demo.wsp”. All examples can be found in the folder \software\examples on FlexRay CD-ROM. It is recommended to copy this folder to the local hard-drive. In the project tree on the left side, you can open the “source”-folder, which contains the source-files registered to this project. A double-click on one of the files will invoke the built-in editor, which supports syntax highlighting, tags and various other functions.

Figure 12: Softune Workbench main window

Note:You may customize the editor by a right-click on the editor window.

Whenever you modify the source-files, you have to re-compile and link the related files to produce a valid load-module (ABS-file). This is done using the MAKE-function. MAKE invokes the assembler, C-compiler and linker for FR whenever necessary (only modified files will be re-compiled).

If you wish to re-compile the entire project regardless of any changes, you can use the BUILD-function. To check for syntax-errors on a specific source-file, use the COMPILE/ASSEMBLE function.



These three functions are available on the button-bar or from the main menu (Project – Compile / Make / Build / Abort).

Click on MAKE or BUILD. Messages from the individual language tools will be fed into the output window at the bottom of the main screen. If the tool chain (C-compiler → Assembler → Linker) was completed successfully, the message “No Error” will appear.

If you get any errors during compilation, an appropriate message will be generated. Try this with a simple syntax-error (e.g. delete a semicolon “;” from the end of a C-line) and click on MAKE again. You will now see a message like this: Now Making... --------------------Configuration: Node2.prj - MONDEB-------------------- MAIN_coldstart_node2.c *** C:\Softune\sample\FPGA_standalone_flexray_demo\Src\MAIN_coldstart_node2.c(89) E4065B: expected a ";" *** C:\Softune\sample\FPGA_standalone_flexray_demo\Src\MAIN_coldstart_node2.c(104) W1012B: warning: parsing restarts here after previous syntax error 1 error detected in the compilation of "C:\Softune\sample\FPGA_standalone_flexray_demo\Src\MAIN_coldstart_node2.c". ------------------------------ Error detected. ------------------------------

To locate the position in the source-file, where the error has occurred, double-click on the message. The editor will open the appropriate source-file, indicating the error highlighted in red, depending on the customise settings of the editor. Correct the error and re-compile the project as explained above.

If more errors occurred, you can go through the error list step by step using the menu “Edit – Top/Previous/Next/Bottom Error” or using the appropriate buttons, which have the same functions:

Note:To get on-line help about a specific error, select the error message and press F1. In many cases, you can get some useful hints how to solve the problem. Of course, you can also use the HELP-menu anytime during development or debugging.



9.2 Project Start-up In order to allow a quick and smooth project start-up Fujitsu Microelectronics Europe supplies a template project as a reference. The easiest way to start a new project is to make a copy of the template project and use this copy as a start-up. The template includes the latest startup.asm file, MCU header file, IRQ table, basic linker and C-Compiler settings.

Note:

Create a new project: 1. In order to start a new user-project use the “Template” project 2. Copy the folder Template and rename the folder to e.g. my_application

3. Enter the folder “my_application” Rename “template.prj” into “my_application.prj” Rename “template.wsp” into “my_application.wsp”

4. Edit “my_application.prj” Rename “template” -> “my_application”

5. Edit “my_application.wsp” Rename “template” -> “my_application”

In any case the settings done in the template must be checked and have to be adjusted to the specific needs and settings of the final application. The template is providing an example for building up a new project. THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR/ELIGIBILITY FOR ANY PURPOSES. (C) Fujitsu Microelectronics Europe GmbH



6. Start Softune Workbench and open your project

Rename “Template” into “my_application”



7. Select Active Configuration “MONDEBUG”

Use Active Configuration MONDEBUG With this selection the project is linked to be used with the Softune Workbench monitor debugger. Corresponding linker settings are done for the memory map in order to avoid overwriting of the sections, which are used by the monitor debugger. The code is linked in this configuration for external SRAM, otherwise it is not possible to debug code with the Softune Workbench monitor debugger. Additionally the MACRO SWBMonDeb is switched on in the assembler settings. This affects settings in startup.asm, which are mandatory to work with the Softune Workbench monitor debugger.

Note:Always check the memory map of the linker settings and ensure that this memory map is suitable for the application and target system in use. Additionally the .mp1 file should be checked to ensure correct settings.

8. Check MCU settings in the module startup.asm. Be careful regarding any modifications. If the peripheral clock speed is modified it can happen that the communication between Softune Workbench and monitor debugger is lost. In the module startup some basic MCU settings are done and some initial data copy transfers are performed for specific data sections e.g INIT. Check if the macro “ABORT” is enabled (default) in the Assember options (<Project>, <Setup Project>, <Assembler>, category <Define Macro>.

9. Check module intvects.inc if any interrupts are used for proper vector table set-up.

10. Write application code in the module main.c or add any other module to the project.

11. Write and modify source code and settings corresponding to the needs of the application. Finally use “Make”, or “Build” to compile and link the project. The



generated output files can be found in the sub-folder MONDEBUGGER of the project folder. The *.mhx file (Motorola S-Record) is located in the ABS sub-folder.

Note:Always check the memory map of the linker settings and ensure that this memory map is suitable for the application and target system in use. Additionally the *.mp1 file should be checked to ensure correct settings.

Check linker mapping list in the*.mp1 file by right-click on “my_application.abs”, Open List File, *.mp1.



12. Start Softune Monitor Debugger via the “Debug” Command

13. After the project is built and debugged successfully switch to the active configuration STANDALONE

Use Active configuration STANDALONE 14. With this selection the project is linked to work in internal flash memory. Check that

the macro “ABORT” is switched off (default) in the Assembler options (<Project>, <Setup Project>, <Assembler>, category <Define Macro>.

This configuration will not work with the Softune Workbench monitor debugger In this configuration the code is linked to work in internal Flash memory, only.

15. Use “Make”, or “Build” to compile and link the project for external Flash memory. The generated output files can be found in the sub-folder STANDALONE of the project folder. The *.mhx file (Motorola S-Record) is located in the ABS sub-folder.

Note:Always check the memory map of the linker settings and ensure that this memory map is suitable for the application and target system in use. Additionally the *.mp1 file should be checked to ensure correct settings.

16. Program the generated *.mhx file (Motorola S-Record) with the Flash programming utility into the internal Flash. See Chapter x “Programming the internal Flash Memory” for more details.

Note:It is not possible to use the Softune Workbench monitor debugger with this configuration because no code can be debugged which is located in internal Flash. Also this configuration does not support special debugger settings, which are disabled for this configuration.



9.3 Using the MB91F369 CPU-module If you have a system with the MB91F369 CPU module, you are able to use the monitor debugger of Softune Workbench. Hence, the examples are linked for the additional debugging RAM of the F369 CPU-module (88:0000…8F:FFFF). Your application will be downloaded to the debugging RAM automatically by starting the debugger.

Alternatively, you can also program the application to the embedded flash of the MB91F369 to create a stand-alone application which starts immediately after a reset. To do so, you have to re-link the application to the internal flash area (08:0000..0F:FFFF).

Creating applications for this board configuration can follow this sequence:

1. Modify an existing project for the F369 CPU board and the FlexRay sub-board.

2. Compile and link (Build) the project to create a valid ‘loadmodule‘ for the external RAM.

3. Start the debugger to download the application to the external RAM.

4. Test and debug the application.

5. Return to the development area of Softune Workbench to apply changes.

6. Continue at step 2 as long as the project needs changes.

7. Change the linker settings in order to run the program from internal flash (for details refer to the appendix).

8. Use the MB91360 flash programmer tool to program the embedded flash memory.

9. Test the application.

10. If necessary continue at step 1, but be aware to change the linker-settings beforehand.

NOTE: Make sure to not overwrite the “security vector” (0x0FFEF4) – see hardware manual

Use the provided templates to make sure the sections are located correctly



9.4 Softune Workbench Monitor Debugger

9.4.1 General Description

Whenever you have successfully created a valid load module, you may switch from the development mode to the debugging mode of Softune Workbench.

Basically, there are 3 types of debugging systems supported:

The software simulator: This type of debugger is always present and does not require any special hardware extensions. The simulator will cover the FR-core features, but no peripheral functions. Therefore, you can use the simulator to verify program flow, check for dynamic errors, look at the generated assembler code and so on.

The monitor debugger: This debugger type requires an evaluation board like the modular Starter kit (MB91F369 module) connected to one of the COM-ports of your PC. Therefore, make sure you have the evaluation board connected and powered-up as described before. Explanations in this manual refer to the monitor debugger only.

The emulator debugger: The in-circuit-emulator (ICE) is a system, which allows a connection to any target system using a probe-cable. The appropriate system for the MB91360 series is the MB2198-01 system. More information about this system can be found on the Fujitsu website.

Which debugger is used for the actual project can be configured in the Project tree as shown below or in the “Project – Setup Project – Debug” menu. By default, the monitor debugger is selected for MB91F369 project examples:

The default settings for the monitor debugger are : COM-Port 1 at 57600Baud. If you wish to change the COM-port, please right-click on the “MonDeb 57k6 COM1” entry and select change.

Note : If you wish to change the Baud rate, you have to change the UART-settings in the debugging kernel source project, re-compile and flash the new kernel to your MB91F369 first before you can use another baud rate.

If these settings are correct, start your debugging session:

First please make sure you are using the F369 CPU-board and your monitor-kernel is stored in the flash memory of the MB91F369. Then please power up and reset the starter kit.

Start the debugger by double clicking the “MonDeb 57k6 COM1” entry in the project/debug tree - or by using “Debug – Start Debug” from the menu. You should see a progress bar indicating the download process.

If nothing happens, there will be an error message after some time (“Invalid communication status”). Double-check the settings again as explained above. Also make sure the



evaluation-board is powered on, ready to use and the RS232-cable is connected properly. Also see the trouble-shooting section in the appendix.

After starting the debugger, additional windows will appear which contain locate-arrows for each (possible) source-line, the original source-code,

Figure 13: SWB Debugging window breakpoint-indicators and the assembler code (in “mixed view”). A yellow line indicates the actual program position.

Note:You can choose “mixed view” from the context menu (right-click) to display source and assembly code at the same time. To easily locate the actual line, use “go to current”!



9.4.2 Basic Debugger Features

GO: Executes the program continuously from the memory location pointed to by the current program counter (PC) until a termination factor occurs.

STEP IN: Executes the program stepwise according to the listing in the source window (steps in C- or ASM). Note that interrupts are disabled during step execution !

STEP OVER: Executes the program stepwise except call-instructions (which will be executed until return). Interrupts are not disabled during a continuous CALL...RETURN execution.

STEP OUT: Executes the program continuously to the parent function (until RETURN). Interrupts are enabled. Note, that debug information is required for this function.

EXECUTE UNTIL CURSOR: Automatically sets a breakpoint at the actual cursor position and executes continuously until this breakpoint, which will be deleted afterwards.

Each valid code line in a debugger window automatically has a locator (blue arrow) and a breakpoint-option (circle). Note that some C-lines may not be displayed with locators and breakpoints, because the compiler has created “optimized” assembler-code. Select “mixed view” in order to check the compiler output.

Instead of single-steps, you may also use the arrows to directly execute your program until a certain line of your source-code:

ABORT: Forcibly terminates execution. This button is not fully supported by the monitor debugger and may cause malfunction if used to abort “continuous operation” of the MCU.

This command button can only be used to abort single code line operations Example: for(k=DELAY_CONSTANT; k>0; k--);

Use the button USER_0 on the “CPU369 board” for ABORT function.

To ABORT continuous execution on the “CPU369 board”, you have to use the USER_0 button on the “CPU369 board”.



9.4.3 Advanced Monitor Debugger Features

TOGGLE BREAKPOINT: Sets or deletes breakpoint at the current source line:

To set or delete a breakpoint, click the circles at the beginning of a source-line.

A indicates an active breakpoint. Hit “Run Continuously” to execute code until reaching this line. A list of all breakpoints can be found under the “Debug – Breakpoint” menu. 255 Software-Breakpoints (using TRAP replacement) are possible.

Note:To set breakpoints at positions which are currently not visible (e.g. because the source window of that module is not open), you can also enter a symbolic label directly in the “Breakpoint” menu. Example: Enter “main” in the address-field and confirm. The new breakpoint will automatically be assigned to the address of the “main()”-function.

REGISTER WINDOW: Displays the CPU-register window. Updated registers appear in red. Setup in context menu defines which Registers should be displayed.

WATCH WINDOW: Displays the current variables to „watch“. Double-click on any variable in your code then specify watch in context menu to add to watch window. All listed variables in a watch window can be displayed in any number format. Use Edit to directly change the

contents.

MEMORY WINDOW: Displays memory areas in various formats defined by Setup (context menu). Changing of address/data is possible when debugger is not executing.

Note:If you modify the ROM-area (200.0000’H to 27F.FFFF’H) it can affect the currently loaded program!

The memory window can be very helpful to check the registers or the frame memory of the connected graphic controller!

DISASSEMBLER: Disassembles the content of the code memory beginning from actual PC position and displays the result in a separate window. Individual assembler-lines can be changed using the „inline assemble“-function.

DEBUG - STACK: Displays the current stack contents in terms of function calls. Parameters, if any, are displayed in brackets.

DEBUG - VECTOR: Reads out and displays the actual interrupt-vector table. Use the „jump“ function to display any code areas pointed to by an interrupt vector (e.g. interrupt service routines used in your program).

DEBUG - CALL: This function can be used to „call“ any routine defined in your code when the debugger is on hold.

DEBUG – LOAD TARGET FILE: Starts a new download of the current load module (ABS file). Usually this function will be executed automatically after starting the debugger (defined in debug



settings; see „Project-Setup-Debug“). However, this function can be useful to re-initialize the debugger for the current debug session.

VIEW - SYMBOL: This function displays all (global) symbols of the current project. Information about the type (char, integer etc.) and the location (address in RAM or register) can be shown using „detail“.

VIEW - LOCAL: Similar to View-Symbol, but only local variables of the current function are shown.

VIEW - COMMAND: From this window, the debugger can be controlled using a command line input. All GUI functions are available as individual commands.

Example:

Run continuously

Step

examine PDRG

set break main

Dump/Halfword 0x2000000..0x20000FF Shortcuts to complex commands can be defined (“alias”) and parameter strings can be substituted by variables. Example: mydump = Dump/Halfword 2000000..20000ff

A set of commands can be combined to a “macro”. Aliases and macros can be defined using the command window context menu.

Example: restart: set register PC=2000000 set break main

run continuously

In order to document or save debugging details such as memory contents, all outputs fed to the command console can be written to a file (“logging”).

A whole “program” of commands (incl. flow control) can be written to a PRC-file and executed. Procedure-files are simple text-files with the extension “PRC” and can be created by the Softune Workbench editor or any other text editor. To execute a procedure-file, use the command window menu or the “file-open” menu during debugging.

Note:Procedure-files can be very helpful to configure the debug-environment automatically, perform automated tests (e.g. when a new C-module has to be tested) or to enhance basic emulator functions such as breakpoints. Using a procedure file, breakpoints can be defined dynamically depending on program conditions. See the “Command Reference Manual” (on-line help) for detailed information about the available command and parameter syntax. Some procedure files exist already included in the example project directory.



9.5 Provided Examples On the “FlexRay Evaluation Kit” CD-ROM and on the MCU website some example projects are provided. The projects can be found in \Software\Examples and are regularly updated on the website. Please check http://www.fme.gsdc.de/gsdc.htm for latest information and version.

Use the “Template” project as a reference to start your own application software. The “Template” project offers a quick start-up and includes basic MCU initialisation files and tools settings (e.g. linker memory map).

Note:In any case all settings must ALWAYS be checked and corrected corresponding to specific application requirements. Be aware that the Softune Workbench monitor debugger is only able to debug code located in RAM! It is not possible to debug code located in Flash memory!

http://www.fme.gsdc.de/gsdc.htm



9.6 Flash Programming

9.6.1 Programming MB91F369G series

To program the Application into the internal Flash of MB91F369 series a Flash Programmer must be used. Fujitsu provide Flash Programmer Application Software for PC based on Windows Operation Systems.

- Fujitsu Flash MCU Programmer for FR series

- Fujitsu MB91360 series Flash Programmer

Both are available at Fujitsu Microelectronics Europe GmbH Microcontroller CD-ROM or Internet. Browse to following location: Software -> Utilities

9.6.1.1 Fujitsu Flash MCU Programmer for FR series

After installation of the Fujitsu Flash MCU Programmer for FR series on PC start the programmer, via the Windows Start menu “Programs -> Fujitsu Flash Programmer -> FR “

1. Select in Target Microcontroller field: MB91F369

2. Select in Crystal Frequency field: 4MHz

3. In Hexfile file enter your *.mhx file to program into internal Flash of MB91F369. Via ‘Browse’ button set the location path of the file.

4. Check correct COM port usage via ‘Set Environment’ button in options field.

5. Reset FLEXRAY-FPGA-EVA-KIT-369 board and do not assert reset or power off the board

6. Start automatic programming via ‘Full Operation’ button.

7. Release reset or power on FLEXRAY-FPGA-EVA-KIT-369 board.

Note: It is also possible to start the programming steps manually. Instead of using ‘Full Operation’ button proceed as following:

Download Flash Programming Kernel via ‘Download’ button.

Release reset or power on FLEXRAY-FPGA-EVA-KIT-369 board

Check if device is blank via ‘Blank check’ button

Erase flash Memory via ‘Erase’ button

Check if device is blank via ‘Blank check’ button

Program the selected mhx file via ‘Program & Verify’ button.



Figure 14: Fujitsu Flash Programmer for FR series

9.6.1.2 Fujitsu MB91360 Flash Programmer

After installation of the Fujitsu MB91360 Flash Programmer on PC start the programmer.

1. Select in ‘Device type’ field: MB91F365,6,7,8,9Gx

2. Check correct COM port usage via ‘COM-Port’ box.

3. Select Automatic tab.

4. In Hexfile file enter your *.mhx file to program into internal Flash of MB91F369. Via ‘Browse’ button set the location path of the file.


6. Start automatic programming via ‘Automatic Mode’ button.




Figure 15: Fujitsu MB91360 Flash Programmer

9.6.2 Programming external 1MByte Flash on CPU369 board

To program the external Flash on CPU369 board, the Fujitsu MB91360 Flash Programmer can be used. The Fujitsu MB91360 Flash Programmer program the external Flash via MB91F369g series. The flow is similar to MB91F369 internal Flash programming.

1. Select in ‘Device type’ field: external Flash 1MB

2. Check correct COM port usage via ‘COM-Port’ box.

3. Select Automatic tab.

4. In Hexfile file enter your *.mhx file to program into external Flash on CPU369 board. Via ‘Browse’ button set the location path of the file.




6. Start automatic programming via ‘Automatic Mode’ button.


Figure 16: External Flash programming with Fujitsu MB91360 Flash Programmer



9.7 Memory Mapping of external Components

At the FLEXRAY-FPGA-EVA-KIT-369 the MB91F369G MCU can access three components.

- external SRAM (CPU369 board)

- external Flash (CPU369 board)

- ERAY FlexRay Communication Controller (FlexRay board)

The provided Software examples and also the Monitor debugger using following internal Clock frequencies:

- CPU-Clock: 32MHz

- Peripheral clock: 16MHz

- Ext. Bus Clock: 16MHz

Within the template project or examples, find the function:

static void InitCPUExtraRegs(void)

In this function the three external areas are set up. Settings are calculated with above mentioned clock settings.

9.7.1 External SRAM

The external SRAM is used to replace the internal Flash, when using Monitor debugger.

It is connected to CS0.

NOTE: Do not change CS0 settings when also using Monitor debugger, otherwise communication between Monitor Debugger and PC might be lost

9.7.2 External Flash

The external Flash can be used as Memory extension, in case the Application size exceeds the internal Memory area. Via Jumper 10 on CPU369 board CS2 or CS3 can selected.

By default CS2 is set. Do not change this, because the FlexRay communication controller (CC) is using CS3.

Address range: 0030:0000 ... 003F:FFFF

9.7.3 ERAY (FlexRay communication Controller)

The FlexRay Communication Controller, called ERAY, is connected to CS3.

Address range: 0050:0000 ... 0050:FFFF



9.8 ERAY Customer Register

The ERAY CC includes 4 Customer specific interface registers. These Register are inside the 2K address range of the register set.

CUST[0..3] (size: 32-bit)

Address: 0 .. 0x0F

9.8.1 Customer Register description

9.8.1.1 Information for CD1.0 .. 1.3

For the FPGA Version the registers are used as following:

CUST0: Address 0x00:

Read only access

Bosch IP version information


Read only access

Fujitsu FPGA version

CUST2: Address 0x08

Read/Write access

IOPORT/LED15-00 Control (at FlexRay Main board)

CUST3: Address 0x0C

Reserved

[CUST1]

bit31-24: Reserved

bit23-16: Bosch FlexRay IPmacro Version

bit15-8 : Fujitsu Major Version

bit7 -0 : Fujitsu Miner Version



9.8.1.2 Information since CD1.4


Read only access

version information


Read only access

Reserved (read value: 0)

CUST2: Address 0x08

Read/Write access

IOPORT/LED15-00 Control (at FlexRay Main board)

CUST3: Address 0x0C

Reserved

[CUST0] detailed description:

bit31-24: Vendor ID

Fujitsu's JEDEC Manufacturer ID code = 0x04

bit23-16: Internal Version = 0x0X

- FPGA : 0.X

FPGARTL004.pof: 0.0 = 0x00

FPGARTL006.pof: 0.1 = 0x01

bit15-8 : Customer Interface Version = 0x00

bit7 -0 : E-RAY Core Releases delivered by BOSCH = 0x06

- 0x04 : Pre-beta2

- 0x05 : Pre-beta2 Update

- 0x06 : beta

- 0x07 : beta2

- 0xFF : E-Ray version information in CREL register

Note:

In the latest E-Ray cores Releases a Core Release Register (CREL: Address 0x03F0) is included. This register contains the actual E-Ray Core relkase. Because of the reason the CUST0 register have the value 0xFF at bit7-0.



9.8.2 Accessing the LED00..15 at FlexRay Main board

CUST2 Register of ERAY CC is used to control the LED00 to LED15 and IOPort00 to 15 at FPGA board.

CUST2 Register: ERAY Register address 0x08

bit31-16: IOPORT15-00 output

bit15-0 : LED15-00 control

Description:

The upper 16 bits are used to set the value of the IO Port at FPGA.

Bit 31 = IOPort15

Bit 16 = IOPort00

Bit 31 – 16:

Value Description

0 Output L-Level at port

1 Output H-Level at port

The lower 16 bits are used as control the LED ports.

Bit15 = LED15

Bit 00 = LED00

Bit 15-0:

Value Description

0 LED OFF

1 LED ON

For MB91F369G series CUST2 Register is visible at address 0x50.0008

9.8.3 Reading FPGA ERAY version

The FPGA bitstream version can be read in the ERAY customer Register

The Register has changed since CD1.4 in order to use the same Register as it is used for the standalone FlexRay Communication Controller MB88121.



9.8.3.1 Information for CD1.0 .. 1.3 The CUST1 Register contains the version of the ERAY Communication Controller.

Use the getCCversion example in samples folder at FlexRay CD.

Download the file via the Monitor debugger. Activate the watch at Variable a.

The function get_CC_version() reads out the CUST1 register and returns the value to variable a.

A further possibility is to call this function manually in debug mode.

Start the Call menu via Debug/Call. Enter the function which you want to call manually and enable return value. In the case enter: get_CC_version(0x500000,0x04). The CUST1 register content will be displayed.

ERAY versions:

In case pre-beta2 version (1.0.1) is programmed, CUST1 register contains value: 0x00020004

In case pre-beta2-update version (1.1) is programmed, CUST1 register contains value: 0x00020100

If ‘0’ is read out check customer register 0.

9.8.3.2 Information since CD1.4

The CUST0 Register contains the version of the ERAY Communication Controller.

Use the getCCversion example in samples folder at FlexRay CD.

Change the function call value (function get_CC_version() ) from CUST1 register to CUST0 register.

Download the file via the Monitor debugger. Activate the watch at Variable a.

The function get_CC_version() reads out the CUST0 register and returns the value to variable a.

A further possibility is to call this function manually in debug mode.

Start the Call menu via Debug/Call. Enter the function which you want to call manually and enable return value. In the case enter: get_CC_version(0x500000,0x00). The CUST0 register content will be displayed.

ERAY versions:

In case beta version (1.1) is programmed, CUST0 register contains value: 0x04010006

In case beta2 version is programmed, CUST0 register contains value: 0x04010007.

In case 1.0 RC1 version is programmed, CUST0 register contains value: 0x040100FF. CREL = 0x07260412

FLEXRAY-FPGA-EVA-KIT-369 Chapter 10 Silk-Plots of the boards


10 Silk-Plots of the boards

10.1 Silk-Plot of CPU369 board

Figure 17: CPU369 board: Silk-plot



10.2 Silk-Plot of FPGA Main Board

TP26

SW7

J41

J34SW

6PO

WER

J52J30

FlexRay Bus I/ F Ach

J40

TP25

J32J42

J73J74

J75

J31

J33

J76

115

115

D26

SW1

SW2

J29

J28

SW3

SW4

SW5

U55

U46

U69

U68

D6D4

A1B1C1

A1B1C1

A16B16C16

A32B32C32

TP31

TP32

TP33

TP34

U52 U59

3016

3016

J43TP37

TP38

TP35J71

J72

J1

U47

J53

D1

GND

+DC

INON

OFF

power

LEDPW

RESET

D33

VccA

5V

3.3V

Vbat Vbat

Vcc5VVio

V3V3V

1V8

J6 J7

P1

J46J45J47J48

J21

BMBPterminalterminal

FlexRay Bus I/ F AchP2

J59J58J49J57

BMBPterminalterminal

AchBch

123

WAKE

ENRSTN/STBN

J56 MON3

140

D8D9

D2D7

LED16

J64J67J65J16J15J14J13J12J11J10J9J8

RXDTXDTXENSC

SNSC

KSDOSDIRSTN/STENENINH1W

AKEW

AKE

J68J70J69J19J18J17J23J27J24J22J26J25

RXDTXDTXENSC

SNSC

KSDOSDIRSTN/STENENINH1W

AKEW

AKE

GND

8079

J55M

ON2

FlexRayEvaluation

Main

Board

D10D11

D12D

13D

14D15

D16D

17D18

D19

D20D21

D22

D23

D24D25

RESETSW

BSW

AINT

LED00LED01

LED02LED03

LED04LED05

LED06LED07

LED08LED09

LED10LED11

LED12

LED13LED

14LED15

J5CN4

J4C

N3

1 2

79 80

1

2

79

80

J3CN2

1

2

79

80

J2C

N1

8079

21

J54 MON1

A_GND

AGND_JP

AVCC_JP

A_VccINT_1

BUS_OE

A_GND

A_GND

GND

3.3V5V

3.3V5V

GND

12

7980

GND

9VTP30

VccINT_2TP29

VccINT_1TP283.3V

TP275V

J39 J38

1.8V2.5V

1.2V1.5V1.8V

J35J36J37

J50J51

A B C D E F

12

34

56

78

9

A B C D E F

12

34

56

78

9

J20

Figure 18: Main Board Silk-Plot



10.3 Silk-Plot of FlexRay Daughter Board 1

J12

MO

D2J1

1M

OD1

J13

MO

D0J14

J7 J8J9J10

TRST

PORS

ELM

SEL1

PGM

0

U2 J61 30

31

50

518081

100

12910

A1

J1EXT OSC

1 3

U48

D1DO

NE

J1512

3132

J16

1 219 20

A

123

B

C

A

B

C

123

TP53VCC5V0

TP54VCC3V3

TP55VCC1V5

TP50GND

TP51GND

TP56A_VCC1V5

TP52A_GND

U1

FlexRay Evaluation Daughter Board

Figure 19: Daughter Board 1 Silk-Plot

FLEXRAY-FPGA-EVA-KIT-369 Chapter 11 Trouble Shooting


11 Trouble Shooting

Problem Solution

Evaluationboard does not power-on correctly. Some or all of the power LEDs (D4,D7,D10,D13, D16) on the CPU module do not light up.

Check voltage supply and jumpers :

∗ The voltage on DC-Power plug should be in the range of 9-12V. The plug should have + on shield and – on the center. The power supply should be able to supply 1200mA to support both, the CPU-module and the graphic subboard.

* The LEDs should light up after switching on the board. Use a multimeter to see whether 5V,3.3V and 2.5V are present on the Vcc/Gnd terminals (JP2,3,4,5,6).

∗ Check jumper positions according to table 1 (Esp. : JP11 – JP15) !

∗ Remove all user extensions on the CPU module and on the subboard

Evaluationboard stays in reset.

LED D25 (Reset indicator) ligths up permanently.

∗ LED D25 (Reset) should flash. If D25 lights up permantantly, the voltage is too low (below 4.25V) - Increase the voltage to solve the problem.

∗ Remove all user extensions on the board to avoid shorts or leakage currents !

The communication from Softune Workbench to the evaluation board fails (Communication errors)

∗ Make sure your COM-port number and the baudrate settings are correct (see debugger introduction). The default COM-port is 1 and the default baudrate is 57600Baud.

∗ Make sure no other programs are using the same COM-port on your PC. Close all other applications (e.g. Flash programmer utilities, terminals etc.)

* Check if RTS/CTS is closed on the CPU module (check if pin 7-8 are connected). * Use only an RS232 extension 1:1 cable

The program stops at the label „uninitialized interrupt !“

∗ Before downloading a new project to the evaluation board, re-initialize your CPU-board using the reset button. This will erase all valid interrupt definitions from previous programs executed on the starterkit.

The abort switch (USER0) does not work correctly.

* make sure you are using a debugging kernel which is configured for using the USER0-button as abort switch. See the description of the monitor debugger project for more details how to configure the kernel software.

FLEXRAY-FPGA-EVA-KIT-369 Chapter 11 Trouble Shooting


Problem Solution

* make sure not to mask the interrupts

The windows of the debugger are empty. * This is due to a wrong (maybe old) path information. Closing all windows in the debugger should fix the problem.

When trying to program the application to the embedded flash, the programmer stops at first address with “loading error” !

* You are probably trying to program a program to the flash which is linked for the external RAM area. See Appendix for details on the linker settings.

Hardware units such as LEDs, user buttons, UART0 or CAN are not working.

∗ Make sure you have enabled these units on the evaluation board using the appropriate jumpers (e.g. JP25 for LEDs). See the provided examples and the hardware manual for information on how to control the peripherals.

CAN devices do not respond ∗ Adjust the potentiometer RV2 (slew rate) according to the line.

Sometimes function of USER_0 button are call, but USER_1 button was used and vice versa.

*Replace the Capacitors C37 and C38 at the USER buttons with a RC Combination (C=10nF; R=470Ohm). The standard Capacitors may not be able to filter all spikes (debouncing) when pressing the buttons. So a crosstalk may occur.

When using pre-betaII-update and FlexPL modules, no communication can be established

Since pre-betaII-update ERAY version, the bus guardian pins are removed. So, the Level at BGE input pin at FlexPL module possible might be Low.

Use workaround (1K pullup at BGE pin) as described in FlexPLModule_Workaround.PDF documentation at CD1.4 or use latest ERAY version (Since CD 1.4 beta version), which alsway dive H-level at former BGE pin.

FLEXRAY-FPGA-EVA-KIT-369 Chapter 12 Related Products


12 Related Products

< “FlexRay-FPGA-Eval-Kit-369” Evaluation board for FlexRay

< MB2198-01 Emulator debugger main unit

< MB2198-10 DSU cable (not included in main unit)

< MB2197-120 Evaluation chip adapter board

< FR360-PROBE-160 Emulator probe adapter for package FPT-160P-M15

< STARTERKITMB91360-ADA160 Adapter board including 160-pin Socket (NQPack160SE / HQPack160SE)

use instead of ADA-91362-91369-RAM board

< MB91FV360G Evaluation chip for MB91360 series

< MB91F369GA Flash-Microcontroller

< NQPack160SE Socket for package FPT-160P-M15 (Tokyo Eletech Corp. www.tetc.co.jp/e_tet.htm)

< HQPack160SE Header for FPT-160P-M15

http://www.tetc.co.jp/e_tet.htm

FLEXRAY-FPGA-EVA-KIT-369 Chapter 13 Appendix


13 Appendix

13.1 Figures Figure 1: LED lightning after power-on................................................................................. 10 Figure 2: CPU369 default Jumper setting............................................................................. 11 Figure 3: FPGA-board jumper setting................................................................................... 11 Figure 4:FlexRay Evaluation kit configuration ...................................................................... 22 Figure 5: Power Connector (J30) (EIAJ RC5320A Type5) .................................................. 40 Figure 6: 9-pin D-Sub male Connector (Top View)............................................................... 40 Figure 7: JTAG Connector J6 (TOP View) ........................................................................... 45 Figure 8: Pin Layout of the 96-polar DIN Connector............................................................. 46 Figure 9: Pin Layout of the 48-pin DIN Connector ................................................................ 47 Figure 10: CPU369 board: Pin Assignment of Peripheral Jumpers ...................................... 54 Figure 11: CPU369 board: Serial Interface Connector P1 .................................................... 55 Figure 12: Softune Workbench main window ....................................................................... 57 Figure 13: SWB Debugging window..................................................................................... 66 Figure 14: Fujitsu Flash Programmer for FR series.............................................................. 72 Figure 15: Fujitsu MB91360 Flash Programmer ................................................................... 73 Figure 16: External Flash programming with Fujitsu MB91360 Flash Programmer .............. 74 Figure 17: CPU369 board: Silk-plot...................................................................................... 80 Figure 18: Main Board Silk-Plot............................................................................................ 81 Figure 19: Daughter Board 1 Silk-Plot.................................................................................. 82

13.2 Tables Table 1: Available boards..................................................................................................... 23 Table 2: FlexRay board power supply jumper settings ......................................................... 24 Table 3: FlexRay main board, reset settings ........................................................................ 25 Table 4: FlexRay main board, BUS Switch........................................................................... 25 Table 5: Flexray board RS485 Bus Driver device jumper settings (Ach) .............................. 26 Table 6: FlexRay board: Bus Driver device jumper settings for daughter board 2 (Ach) ....... 28 Table 7: FlexRay board RS485 Bus Driver device jumper settings (Bch) ............................. 29 Table 8: Bus Driver device jumper settings for daughter board 2 (Bch)................................ 31 Table 9: Reserved Switches................................................................................................. 32 Table 10: FPGA operation mode setting .............................................................................. 32 Table 11: FlexRay Evaluation Daughter Board: FPGA configuration jumper ........................ 33 Table 12: FlexRay Main board: Power supply check pins .................................................... 34

FLEXRAY-FPGA-EVA-KIT-369 Chapter 13 Appendix


Table 13: FPGA Main board: Mon 1 (J54) Connector (Bus I/F) pins..................................... 35 Table 14: FPGA Main board: Mon 2 (J55) Connector (Bus I/F) pins..................................... 37 Table 15: FPGA Main board: Mon 3 (J56) Connector (Bus I/F) pins..................................... 37 Table 16: FlexRay daughter board 1: Power supply monitor pins......................................... 38 Table 17: FlexRay daughter board 1: IO Port Monitor (J15) pins.......................................... 38 Table 18: FlexRay daughter board 1: J16 pins..................................................................... 39 Table 19: Daughter Board 1 Connectors J2, J3, J4, J5 ........................................................ 43 Table 20: Daughter Board 2 Connectors J6, J20.................................................................. 44 Table 21: Daughter Board 2 Connectors J7, J21.................................................................. 45 Table 22: CPU Board Connector J50 (96-pin DIN Connector).............................................. 46 Table 23: CPU Board Connector J51 (48-polar DIN Connector) .......................................... 47 Table 24: CPU369 board: Power supply Switch setting (SW1)............................................. 49 Table 25: CPU369 board: Power Supply Jumper settings.................................................... 50 Table 26: CPU369 board: Operation mode settings ............................................................. 50 Table 27: CPU369 board: UART Jumper setting.................................................................. 50 Table 28: CPU 369 board: reserved UART settings ............................................................. 51 Table 29: CPU 369 board: external Flash CS setting ........................................................... 51 Table 30: CPU369 board: Hardware standby jumper setting................................................ 51 Table 31: CPU369 board: Clock selection jumper ................................................................ 51 Table 32: CAN interface Jumper (JP23, JP24)..................................................................... 52 Table 33: CPU369 board: MCU module URAT / LED selection............................................ 52 Table 34: CPU369 board: power supply header................................................................... 53 Table 35: CPU369 board: Pin Assignment of Peripheral Jumpers (JH1, JH2)...................... 54

-- END --

Documents

EVALUATION BOARD FLEXRAY-FPGA-EVA-KIT-369 · 2006. 9. 13. · 2005-05-23 V1.0, MSt First release 2005-07-14 V1.1, MSt FLEXRAY address area added; Access to LED port and IOPort at