CSNSM

EUSO BALLOONEC-ASIC Electrical Interface

S. Ahmad, P. Barrillon, S. Blin, S. Dagoret, F. Dulucq, C. de La Taille,G. Martin-Chassard

IN2P3-OMEGA LAL Orsay, France

Reminder of EC-ASIC

2

ASIC B ASIC FASIC D

68 pins

ASIC A

68 pins

ASIC C ASIC E

120 pins

A B C D E F68 pins

68 pins

68 pins

68 pins

• 6 ASICs, on top & bottom of the PCB• 6 connectors (68 pins) ⇒ MAPMTs

• 1 connector (120 pins) ⇒ PDM Board

EC-ASIC Interfaces

Connections EC-ASIC ⇔ PDM:

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• Connector 120 pins should be enough

• Choice: HIROSE FX2-120P-1.27DS– Header– Dimension=82mm x 7.5mm– Right angle type– Through hole

Input name and number of pins Output name and number of pins

avdd 4 Sr_ck 1 Clk_40n 1 Adata_ki 1 Atransmit_on 1 Adata_pc[7..0] 8 AOR_ki_sum 1 Aerror_sc 1

vdd_ki 2 Sr_in 1 Clk_40p 1 Bdata_ki 1 Btransmit_on 1 Bdata_pc[7..0] 8 BOR_ki_sum 1 Berror_sc 1

dvvd 4 sr_out 1 Clk_gtu_n 1 Cdata_ki 1 Ctransmit_on 1 Cdata_pc[7..0] 8 COR_ki_sum 1 Cerror_sc 1

VH 4 Sr_rstb 1 Clk_gtu_p 1 Ddata_ki 1 Dtransmit_on 1 Ddata_pc[7..0] 8 DOR_ki_sum 1 Derror_sc 1

gnd 14 resetb 1 Val_evt_n 1 Edata_ki 1 Etransmit_on 1 Edata_pc[7..0] 8 EOR_ki_sum 1 Eerror_sc 1

Select_sc_probe 1 Val_evt_p 1 Fdata_ki 1 Ftransmit_on 1 Fdata_pc[7..0] 8 FOR_ki_sum 1 Ferror_sc 1

Loadb_sc 1 AOR_FSU 1 COR_FSU 1 EOR_FSU 1

Select_din 1 BOR_FSU 1 DOR_FSU 1 FOR_FSU 1

EC-ASIC Interfaces

① ASIC Parameters setting : Slow Control (SC) Registers– Daisy chain – 6 ASICs– Optional : Signal Monitoring(probe) – interface sharing– Serial TTL signals

② Data Transmission (I/O of Digital Module)– LVDS :

• Readout Clock - 40 MHz

• GTU - 400kHz, 98% Duty Cycle, Syncronised to ↓ Readout Clock

– Serial TTL:• Transmission On - Flag the Data Transmission to PDM• Data Out – Serial links for Data• Reset

③ Analog I/O:– LVDS : Fast ASIC Masking– TTL:

• OR_FSU(6x)• OR_PA, OR_VFS & OR_KI – Not Used

4

5

SPACIROC Slow Control

Features:

•Shift registers

•Non destructive readout

•Radiation hardened

•Data majority voter

•Error detection

•Low frequency operations

Components:

•Scan Type DFF

•Triple Data Latch

•Majority & Error logic

SPACIROC SC : 898 bits

Slow Control - 1 Bit Cell

EC-ASIC Slow Control

6

ASIC A

6 ASICs Daisy Chain :

Asr_in

Sr_rstb

Sr_ck

Load_sc

Select_dinSelect_sc_probe

ASIC B

Sr_rstb

Sr_ck

Load_sc

Select_dinSelect_sc_probe

ASIC F

Sr_rstb

Sr_ck

Load_sc

Select_dinSelect_sc_probe

FSr_out

SPACIROC ASIC SC : 898 bitsEC-ASIC SC: 5 388 bitsPDM SC : 32 328 bits

Signal (TTL 3.3V) SC Probe Description

Sr_in ✓ ✓ Shift Register In

Sr_ck ✓ ✓ Clock

Sr_rstb ✓ ✓ Reset

Load_sc ✓ - Load Data Latch

Select_din ✓ - Select input

Select_sc_probe ✓ ✓ Shift SC or Probe

Sr_out ✓ ✓ Shift Register Out

EC-ASIC Data Transmission

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Data Transmission :• Starts after detecting of the rising

edge ↑ GTU

• TransmitOn active for flagging the transmission

• DataOut: StartBit=‘1’

• DataOut: MSB first, Ch0 to Ch7 (+Ch8 for KI)

• Transmission ends with parity bit: ‘1’ for even and ’0’ for odd number of 1s.

• Total DataOut: StartBit(1 bit) + Data(64 bits) +

Parity(1 bit)

• Data rate: 3.4 kbit/GTU

Signal Qte Type Description

Clk Readout 1 LVDS 40 MHz Readout Clock

GTU 1 LVDS 400KHz Gate Time Unit

TransmitOn 6 TTL 1.5V Transmission On

DataOut 54 TTL 1.5V Serial Data lines

Reset 1 TTL 3V Reset

*Full timing diagram available

Progress status

A. Slow Control Interface(PDM):– Heritage UFFO: Same ASIC and SC bit counts– Changes on EC: 4xASIC ⇒ 6xASIC – Full ASIC parameter settings & Readout

B. Data Readout Interface(PDM):– Heritage UFFO: Identical readout interface– Changes on EC: 4xASIC ⇒ 6xASIC – Readout Clock : 20MHz ⇒ 40MHz

C. Pinlist is pending the completion of EC-ASIC schematic

D. Possible rising problems:– Limitations on the ASIC DataOut buffer: max load ~20pF @40MHz

⇒ Short Cable length is preferred(max ~15cm)

– Drawbacks on Multidrop LVDS ? (6 Loads)– Signal integrity (Crosstalk,…)

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BACKUP SLIDES

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10

Digital Module Timing Diagram

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GTU : 2% duty cycle synchronised on falling edge of ClkReadout Global Reset (Rstb) at least 25 ns.

IO signals for the ASIC communication:

A. Inputs (non exhaustive list) 64 MAPMT anodes inputs + 1 dynode input

• in<0…63>, last_dynode

Slow Control signals:• sr_in, select_din, sr_stb, sr_ck, load_sc (TTL)

Probe (analog/digital) signals:• sr_in, sr_clk, sr_rstb (TTL)

select_sc_prob (Shared I/O: sr_rstb, sr_ck, sr_in, sr_out) (TTL)

resetb : Digital Global Reset (TTL) Val_evt (LVDS) : Trigger enable

GTU (LVDS) : 400kHz clock ClockReadOut (LVDS) : 40MHz clock

VHi: defined voltage for digital high level outputs (1.5V) VLo: defined voltage for digital low level outputs (0V)

trig_ext(TTL) : External Trigger for debugging

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ASIC Interface

Analog inputs

Clocks from FPGA

FPGA

12

ASIC Interface

IO signals for the ASIC communication:

B. Outputs (non exhaustive list) Data Output

• transmit_on (VHi-VLo)• Data Out (VHi-VLo) : data_pc<0…7>, data_ki

Or trigger outputs(VHi-VLo) : • OR_trig_fsu,OR_trig_pa,OR_trig_vfs : PC• OR_ki_sum,OR_ki_dynode : KI

Probes : Analog & Digital

Probes/Slow Control output:• sr_out (Shared), error_sc (Slow Control)

Various current and voltage monitoring (Bias, Threshold, etc..)