Ethernet BomberEthernet Packet Generator for network

analysis

Oren Novitzky & Rony Setter

Advisor: Mony Orbach

Spring 2008 – Winter 2009Spring 2008 – Winter 2009

Midterm PresentationMidterm Presentation

Project Goals(From Char. Presentation)

Developing a hardware Ethernet packet

generator for Ethernet network and

devices testing.

Support different operation modes –

Stand-alone / remote controlled.

Implementation of the system on Altera

PCI-E Development kit board with

Stratix II GX FPGA.

Project Goals(From Char. Presentation)

Learning common communication

protocols such as Ethernet, UDP, IP

Learning HW development language and

tools.

Architecture guideline:Reaching line speed

Hardware Optimization:

-- Using fast packet memory: large Using fast packet memory: large

on- on- chip MRAM for CPU .chip MRAM for CPU .

- Accelerating the packet checksum - Accelerating the packet checksum

using using C2H accelerator for HW C2H accelerator for HW

implementation.implementation.

- Using high speed external - Using high speed external

memory: memory: DDR2-SDRAM and SSRAM.DDR2-SDRAM and SSRAM.

.

Architecture guideline:Reaching line speed

Hardware Optimization (cont.):

-- Interfacing Altera’s TSE MAC with Interfacing Altera’s TSE MAC with

SGDMA (instead of NIOS II directly)SGDMA (instead of NIOS II directly)

- Increasing core clock from - Increasing core clock from

83.33MHz to 83.33MHz to 150MHz.150MHz.

.

Architecture guideline:Reaching line speed

Software Optimization:

-- Using the UDP protocol (instead of Using the UDP protocol (instead of

TCP) TCP) to increase throughput to increase throughput

performanceperformance

- Networking with InterNiche’s - Networking with InterNiche’s

“NicheStack” “NicheStack” fully configurable fully configurable

networking stack and networking stack and MicroC/OS-II MicroC/OS-II

operating system.operating system.

- Raising compiler optimization - Raising compiler optimization

level to level to maximum (3)maximum (3)

.

PHYMarvell

External Ethernet 10/100 Mbps

UDP/IP Packet generator

Nios II

Ethernet MAC

Altera TSE

MII

RJ-4

5

Block Diagram

DDR2 SDRAM/QDR2 SRAM

NicheStackUDP

Networking

On chip Memory

Ext. CLK100MHz

PLL100->150

MHz

JTAG Debug Module

SGDMA Interface

JTA

G

Architecture Feasibility Proof

Avalon BUS

NiosIIProcessor

JTAGDebugModule

JTAGUART

On-chipMemory

DataM

InstM S S

JTAG cont.

PLLSGDMA

TX

S

Src

SGDMARX

S

Sink

Triple speed Ethernet MACSink SrcS

100 Mhz

150Mhz

FPGA

MII

SOPC ArchitectureOn-BoardMemory

ControllersS

SOPC ArchitectureTripple Speed Ethernet MAC

Scatter-Gather DMA Controllers

NIOS II CPU

On-Chip Memories

On-Board Memories

PLL

JTAG Interface

CPU Timers

Pipeline Bridge

Board resource usage

HW in use

Project Milestones – Part A

Work Week

Adjusting architecture to SIIGX with SOPC builder

Learning NicheStack functions and syntax

Learning MicroC OS basics

Exam period winter 09’

Simulating design with basic software – transmitting UDP packets

Part A final presentation and demo.

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