Students: Shalev Dabran Eran Papir

Supervisor: Mony Orbach

In association with:Spring 2005

High Speed Digital Systems Lab

Project GoalsProject Goals

Developing a 16bit CRC-GENRATOR for the Rocket Developing a 16bit CRC-GENRATOR for the Rocket I/O experiment using to the Virtex II-pro I/O experiment using to the Virtex II-pro

PPC

To PC

PacketGeneration

Patterns

PLB

Test Status

Storage

TrafficGenerator

TrafficAnalyzer

Rocket I/O

Tra

nsceiv

er

BRAM 1

BRAM 2

CRCGenerator

CRCAnalyzer

PropertiesProperties

Data rate – up to 2.5 Gbits /sec.

Data width - 32 bits / cycle.

Data length is unlimited.

What is CRCWhat is CRC?? When we transmit message we want to be sure When we transmit message we want to be sure

that the message that was received in the that the message that was received in the destination is the same one that we sent.destination is the same one that we sent.

We add to the transmitted message an overhead We add to the transmitted message an overhead data for checking it on the received side.data for checking it on the received side.

The overhead data called CRC - Cyclic The overhead data called CRC - Cyclic Redundancy Checking.Redundancy Checking.

CRC are used for error detection in CRC are used for error detection in communication systems.communication systems.

RequirementsRequirements

On the transmitted side:On the transmitted side: We get double word stream of data with We get double word stream of data with

start_of_data packet and end_of_data packet.start_of_data packet and end_of_data packet. We add a CRC word to the end_of_data packet.We add a CRC word to the end_of_data packet.

On the received sideOn the received side:: Compare the calculated CRC & the received CRC.Compare the calculated CRC & the received CRC. Output an error signal if error detectedOutput an error signal if error detected

88 bit CRCbit CRC

8 bit CRC solution to 32 bit data8 bit CRC solution to 32 bit data

DATA

D31

D30

D0

……

…

…

…

D31

31,0 31,7

1,0 1,7

R R

R R

R

0,0

7,7

M

M

0,0 0,7R R CRC=D0

D0

++D31

Transmitter IntegrationTransmitter Integration

Rocket I/O Transceiver

CRCGenerator

TrafficGenerator DATA

Control

DATA+CRC

Control

Control

Data

Receiver IntegrationReceiver Integration

Rocket I/O Transceiver

CRCAnalyzer

TrafficAnalyzer DATA

Control

DATA+CRC

Control

Control

Data

TestsTests

CRC test – by known vector.CRC test – by known vector. Changing Polynomial.Changing Polynomial. Integrating in the complete system.Integrating in the complete system. Bypass test.Bypass test. Error injection.Error injection.

Changing PolynomialsChanging Polynomials

The matrix is written in the internal ramThe matrix is written in the internal ram We can change it by write a new values to We can change it by write a new values to

the ram with out the need of VHDL code the ram with out the need of VHDL code changes.changes.

VHDL ImplementationVHDL Implementation

Test BenchTest Bench

Transmitter SideTransmitter Side

Handling the two CRC’sHandling the two CRC’s

We use a XOR function to compare the two We use a XOR function to compare the two CRC’s (received and calculated).CRC’s (received and calculated).

If the data that was sent and the data that If the data that was sent and the data that was received are identical the CRC’s are the was received are identical the CRC’s are the same and there will be no error.same and there will be no error.– XOR XOR : :

‘‘1’1’’1’ and ‘0’’1’ and ‘0’’0’ = ‘0’’0’ = ‘0’ ‘‘0’0’’1’ and ‘1’’1’ and ‘1’’0’ = ‘1’’0’ = ‘1’

Receiver SideReceiver Side

Error InjectError Inject

Our CRC Vs. Web CRCOur CRC Vs. Web CRC

Our is flexible, the web’s constantOur is flexible, the web’s constant Our pipeline is better (one gate between Our pipeline is better (one gate between

latches).latches). Our area is much Bigger.Our area is much Bigger. We use around 5000 latches the web can We use around 5000 latches the web can

be uses around 200.(Transmiter and be uses around 200.(Transmiter and Receiver)Receiver)

Main different is the latches , area & timingMain different is the latches , area & timing

SummarySummary Our part in this project was to add 16 bit changeable parallel Our part in this project was to add 16 bit changeable parallel

CRC to both the Transmitter part and the receiver part.CRC to both the Transmitter part and the receiver part. We check the differences between a serial and a parallel We check the differences between a serial and a parallel

implementation and decided to go with a specific implementation implementation and decided to go with a specific implementation that we can use to simply modify the polynomial that is being that we can use to simply modify the polynomial that is being used.used.

CRC block features:CRC block features:– Can be bypassed using a bypass signal.Can be bypassed using a bypass signal.– Can be intentionally inserted error using the error inject signal.Can be intentionally inserted error using the error inject signal.– Can used different polynomials by changing the chip internal Can used different polynomials by changing the chip internal

memory without changing the VHDL code.memory without changing the VHDL code. After the implementation of the CRC block we used a Test After the implementation of the CRC block we used a Test

Bench to test out block and then integrated our CRC block with Bench to test out block and then integrated our CRC block with the rest of the system.the rest of the system.

ConclusionsConclusions

Because we used a CRC that can get any Because we used a CRC that can get any polynomial and didn't use a specific code for a polynomial and didn't use a specific code for a specific polynomial, we needed a general specific polynomial, we needed a general purpose logic design and this design uses a lot purpose logic design and this design uses a lot of logic cells on the chip.of logic cells on the chip.

Being a part of a big project gave us all the Being a part of a big project gave us all the project definitions that led us in a specific project definitions that led us in a specific direction but didn't give us a lot of room to direction but didn't give us a lot of room to maneuver.maneuver.

In this project we learned about VHDL In this project we learned about VHDL implementations and the usage of the Virtex2 implementations and the usage of the Virtex2 pro chip. pro chip.

THE ENDTHE END