ENGR337 Homework Package

Chapter 1 Frequency Response and LTSpice

1.1. Draw the unit circle in the X-Y plane and the corresponding sine wave in the sine-angle plane.

1.2. Derive the impedance of a cap and an inductor when the input signal is ejwt .

1.3. What are the amplitude and the phase shift of the following sinewaves?

1) 5 2) 5j 3) 1+j 4) j 5) 2+3j

1.4. What is the phase shift of the output signal compared to the input signal? Is the output leading

or lagging?

1) Vi: 2+4j, Vo: 1+3j

1.5. Draw the output and the input in the same coordinate, show the time delay of the output

compared to the input. Is the output lagging or leading? Show the amplitude attenuation of the

output compared to the input. Verify the result using LTSpice.

Fig. 1.5

1.6. Draw the output and the input in the same coordinate, show the time delay of the output

compared to the input. Is the output lagging or leading? Show the amplitude attenuation of the

output compared to the input. Verify the result using LTSpice.

Fig. 1.6

1.7. What are the capacitances of the following cap combinations?

Fig. 1.7

1.8. Draw the output and the input in the same coordinate, show the time delay of the output

compared to the input. Is the output lagging or leading? Show the amplitude attenuation of the

output compared to the input. Verify the result using LTSpice.

Fig. 1.8

1.9. Draw the output and the input in the same coordinate, show the time delay of the output

compared to the input. Is the output lagging or leading? Show the amplitude attenuation of the

output compared to the input. Verify the result using LTSpice.

Fig. 1.9

1.10. What is the 3dB frequency of the following circuit? Draw the Bode Plot, including the

amplitude and the phase in the frequency domain in the same diagram. Verify with LTSpice.

Fig. 1.10

1.11. What is the 3dB frequency of the following circuit? Draw the Bode Plot, including the

amplitude and the phase in the frequency domain in the same diagram. Verify with LTSpice.

Fig. 1.11

1.12 Calculate |Vo/Vi|, and the time delay. Hand draw the input the output signal, and also show

the time delay on the graph. Finally, compare the results to your simulation. V1: amplitude 1V

(Vpp 2V), f=100 kHz.

Fig. 1.8

1.13. Calculate |Vo/Vi|, and the time delay. Hand draw the input the output signal, and also show

the time delay on the graph. Finally, compare the results to your simulation. V1: amplitude 1V

(Vpp 2V), f=100 kHz.

1.14. Calculate |Vo/Vi|, and the time delay. Hand draw the input the output signal, and also show

the time delay on the graph. Finally, compare the results to your simulation. V1: amplitude 1V,

f=100 kHz.

Fig. 1.10

Chapter 2 Active Filters and Operational Amplifiers

2.1 Comment on the following Op Amp configurations. Answer the following questions for each

of them: (1) Is this circuit connection correct? (2) What is the application of this configuration? (3)

Simulate the circuits in LTSpice and explain the voltage at Vm.

Hint: find the Op Amp device from here: Press ‘F2’ to open the library, double click [opamps],

scroll to the very right of all the opamp devices and pick up ‘UniversalOpamp2’.

2.2 (1) Derive the Voltage Gain equation of the following inverting amplifier. (2) What is the

problem of the following circuit? Fix it by replacing the GND of the OpAmp with -9V. (3) Using

the +9/-9 V power supply for this circuit, can you amplify this signal by 10 times or more without

distorting it? Why? (4) What is the maximum gain of this circuit for this specific signal being used

in this schematic below?

2.3 (1) Derive the Voltage Gain equation of the following noninverting amplifier. (2) What is the

problem of the following circuit? Fix it by replacing the GND of the OpAmp with -9V. (3) Using

the +9/-9 V power supply for this circuit, can you amplify this signal by 10 times or more without

distorting it? Why? (4) What is the maximum gain of this circuit for this specific signal being used

in this schematic below?

2.4 The input sinewave does not have any Negative Swing in the following example. Instead, it

originally carries a 2 V DC offset and a 1mV and 60 Hz noise.

(1) Directly simulate the input and output of the following circuit configuration, explain the Vin

and Vout waveforms.

(2) Add a passive high-pass filter to filter out the DC offset at the output of the Op Amp and add

a passive low-pass filter to filter out the 60 Hz noise of the output signal. Calculate the cut-off

frequencies of the two filters. Zoom in your signal waveform to show the 60 Hz noise is gone.

2.5 When the input comes from the inverting terminal, you need to match the DC offset voltage at

the two inputs of the Op Amp. Use the following circuit to remove the 60 Hz noise from the signal.

2.6 The example in 2.5 is rare. We hope to set the Vref at 2.5 V (the middle of 0-5 V) to get more

signal swing space. However, the DC offset from the original signal is 2 V. Let’s use a highpass

filter to remove the 2 V DC first and then add a 2.5 V Vref to the signal before it goes into the

opamp.

The problem of the following circuit is the grain resistor R1 affects the cutoff frequency and the

attenuation of the front high-pass filter. Fix it by adding a buffer between the high-pass filter and

R1 and show if there is any improvements in the results.

2.7 In problem 2.6, you can use a buffer to block the connection between the high-pass filter and

the gain resistor R1. However, if you use the Non-inverting configuration, you won’t have this

problem. Use a non-inverting configuration to remove the 2V DC offset and the 60 Hz noise, and

add a 2.5 V DC Vref to the output.

2.8 Derive the differential gain and the common mode gain of the following difference amplifier.

Then, show the common-mode rejection ratio (CMRR). (Assume R2/R1 = R4/R3, or say, R2=R4,

R1=R3).

2.9 Derive the voltage gain of the following instrumentation amplifier.

2.10 Based on the following circuit, design the values of the capacitor and the resistor to make the

cutoff frequency to be 5 kHz. Use LTSpice to verify the cutoff frequency.

Fig. 2.10

2.11. In the following integrator, Vo is charged to -0.5 V – 0 V. Modify the value of the resistor

or the capacitor, to make the Vo swings between -1 V – 0V. (Do not change anything about the

voltage source).

(Show the calculations and the simulations for credit).

Chapter 3 The pn Junction and the Diode

3.1 Read the textbook P136-139 (it’s fine if you do not have the textbook, refer to the lecture video

and notes), calculate the intrinsic carrier density ni for silicon at T=50K and 350K. Show the

calculation process for the credit.

3.2 Explain what are ni, nn, np, pn, pp, NA, and ND?

3.3 Consider an n-type silicon for which the dopant concentration ND=10^17/cm3. Find the electron

and the hole concentration at T=300K (room temperature) and T= 350K. Show the calculation

process for the credit.

3.4 Find the resistivity of (a) intrinsic silicon and (b) p-type silicon with NA=1015/cm3. Use

ni=1.5x1010/cm3, and assume that for intrinsic silicon µn=1350 cm2/V s and µp=480 cm2/V s, and

for the doped silicon µn=1000 cm2/V s and µp=400 cm2/V s.

3.5 Draw the pn junction and explain:

1) Without an external voltage, the formation of a depletion region, and the formation of the

diffusion current and the drift current.

2) With an external voltage, explain the changes of the width of the depletion region under

‘forward bias’ and ‘reverse bias’ operations.

3) Explain how the depletion region will be changed, and how the diode capacitance will be

changed with an increasing voltage under both ‘forward bias’ and ‘reverse bias’ operations?

3.6 (1) Refer to the following LTSpice example, change the diode’s built-in voltage to 1 V and

simulate it. Keep in mind the diode in the following figure has a -50 V built-in voltage.

(2) If you do not set up a BV, what is the default built-in voltage? Simulate it and show your

answer.

3.7 Ideal diodes (no built-in voltages) find the values of the voltages and currents indicated in Fig.

3.7.

Fig. 3.7

3.8 In Fig. 3.8, Vi is a 1k Hz 5-V peak-peak sine wave (centered at 0V), sketch the waveform of

Vo and label the peak values. (ideal diodes)

Fig. 3.8

3.9 Design a voltage multiplier (a high voltage DC power supply), the input voltage is a (-5V,5V)

peak-peak square wave, the output should be at least 40 V DC. However, the working load is a 50

pF capacitor, the maximum voltage can be applied to the cap is 20 V. Use this HV power supply

to drive this capacitor without burning it. (you may need a Zener diode to protect your circuit).

(Use LTSpice to design the circuit and demonstrate your design).

Chapter 4 The MOSFETs

**KP and Vth can be found in model.txt

4.1. (1) Build the circuit using nmos in LTSpice, and change the VGS values to ‘list 1.5 1.8 2’,

and simulate the ‘VDS vs ID’ curve. (2) Use a fixed VGS voltage and change the variable to

VDS, and use ‘.step param VDS list 2 3 4 5’, and simulate the ‘VGS vs ID’ curve. Show your

simulation on a printed paper for credit.

Fig. 4.1

4.2. Repeat the problem above for the PMOS circuit below: (please note that it is VSG/VSD

now, and the PMOS substrate is connected to the highest potential in the circuit). Show your

simulation on a printed paper for credit.

4.3. Draw a figure to explain the ‘Body Effect’.

4.4. Calculate ID of the NMOS and verify with LTSpice. Show your calculation/simulation on a

printed paper for credit.

**KP and Vth can be found in model.txt. Use the N_1u model for this problem.

Fig. 4.4

4.5. Calculate ID of the PMOS and verify with LTSpice. Show your calculation/simulation on a

printed paper for credit.

**KP and Vth can be found in model.txt. Use the P_1u for this problem.

Fig. 4.5

4.6 For the circuits seen in Fig. 4.6, estimate the output DC voltage. Verify the calculation using

LTSpice. (use .op)

. **KP and Vth can be found in model.txt. Use the N_1u and the P_1u for this problem.

Fig. 4.6

4.7 Estimate the AC, id, drain current that flows in the circuit seen in Fig. 4.7. Verify your

calculation with SPICE using transient analysis. **KP and Vth can be found in model.txt. Use

the P_1u for this problem. The simulation schematic is shown below.

Fig. 4.7

4.8 Calculate the DC operating points (DC voltages/currents) and the AC voltages/currents in all

the nodes in the following differential pair. Use LTspice to verify all of them. (Put the values in a

table, two columns, one for the calculated values, one for the simulation values).

Fig. 4.8

4.9 Using the CMOS long-channel process (N_1u and P_1u), determine the current flowing in

the circuit seen in Fig. 4.9. Verify your answer with SPICE. **KP and Vth can be found in

model.txt.

Fig. 4.9

4.10 Repeat 4.9 for the circuit in Fig. 4.10. Can M1 and M2 be replaced with a single MOSFET?

If so how and what size? If not why? **KP and Vth can be found in model.txt.

Fig. 4.10

Chapter 5 Operational Amplifiers II (Op Amp II)

5.1. Draw the following Biasing circuit + Op Amp in LTSpice (zoom-in to see the parameters),

Change the adjustable resistor R1 to 50k, 100k, 150k, 200k, and 300k, discuss the results of the

DC operating point of the marked area below (VGS, VDS,sat, and ID). What is the input swing ranges

at the input of the differential pair? (Use the C5_models.txt model this time. The threshold is

around 0.67V). The model file is available on the online lecture page. The differential pair is only

DC biased, there is no AC input signal applied.

Fig. 5.1

5.2 Derive the small signal gain for the differential pair (Fig 5.2(a)) (CMOS Book P718) and the

common-source amplifier (Fig 5.2(b, c)) (CMOS Book P658) in the following figure: (refer to the

notes of the lecture).

(a) (b) (c)

Fig. 5.2

5.3 (1) In Fig. 5.3(a), derive the gain at Vo1 and Vout, draw the gain and phase plot by hand, then

verify using LTSpice.

(2) In Fig. 5.3(b), calculate the poles for the input (fin) and output (fout). Then Use LTSpice to

plot the ‘.ac’ analysis, label the poles in your figure (use your calculated values to approximate the

location and then label in your figure use your pen). (Assume gm1=gm2=150 uA/V, Cgs1=23.3

fF, Cgd1=2 fF, Csg2=70 fF).

Fig. 5.3(a)

Fig. 5.3(b)

Chapter 6 BJT Transistors

6.1. Summarize the following parameters of an NPN BJT transistor.

IB =

IC =

IE =

gm=

rbe=

vbe=

6.2. Calculate the DC operating point (.op) of the following BJT amplifier, compare with your

simulation. The parameters to be calculated and tested: IE, IC, IB, VB, VC, VE, gm, rbe, VCC,

VEE. Beta=100. (hint: 1. DC VBE is 0.7 V as the built-in potential of a pn junction. 2. The current

source 1 mA is the key to get you started).

Fig. 6.1

6.3 Given that Beta=100, calculate the DC operating points and the AC gain (no simulation, just

calculation). Draw the equivalent AC small signal model.

Fig. 6.3

6.4 Q1 has Beta=100, Q2 has Beta=100, VBE=0.7V. (1) Find IE1, IE2, VB1, VB2. (2) If a load

resistance RL=1k ohm is connected to the output terminal, find the voltage gain from the base to

the emitter of Q2, vo/vb2, and find the input resistance Rib2 looking into the base of Q2. (3)

Replacing Q2 with its input resistance Rib2, analyze the input resistance looking into Q1’s base.

Calculate ve1/vb1. (4) Find the overall voltage gain vo/vb1. (make sure you can distinguish AC and

DC notations). Vdd is 5 V, don’t do simulation for this in LTSpice.

Fig. 6.4