Eng. Física Tecnológica ArquitecturaComputadores -Aula 2

Microcontroladores

Eng. Física TecnológicaArquitectura Computadores - Aula 2

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s XX Century

historyplex.com/scientific-achievements-top-discoveries-of-20th-century

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s Apollo Guidance Computer• The AGC was the first silicon

integrated circuit based uProcessor

• Block II version (used in the crewed flights) used 2,800 ICs, each with dual three-input NOR gates.

• Timing reference came from a 2.048 MHz crystal clock.

• Four 16-bit registers for general computational use, called the central registers:

• A: accumulator, for general computation

• Z: Program counter – the address of the next instruction to be executed

• Q: remainder from the DV instruction

• LP: Lower product after MP instructions

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s Ariane 5 – 1996 disaster

• Re-use SW Ariane 4• Better acceleration • Data conversion

– 64-bit floating point– 16-bit signed integer– Arithmetic Overflow

• Losses > 370M€

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s

Clock

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s Number systems

• Decimal numbers (base 10) Symbols 0-9:32410 = 3x102 + 2x101 + 4x100

• Digital systems have only two states, ON/OFF (1 bit). Symbols 0/1

• Binary numbers (base 2) 10102 = 1x23 +0x22 +1x21 +0x20 =1010

– 4 bit register (nibble) -> 24 =16 combinations [0-15]– 8 bit register (byte) -> 28 = 256 combinations [0-255]– 16 bit register -> 216 = 65536 combinations [0-65535]

• Hexadecimal (base 16), 16 symbols 0-9,A-F – F516 = 15x161 +5x160 =24010 =1111 01012

• Convertion Binary from/to Hexadecimal

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s Signed binary numbers

• Sign bit (MSB) + Magnitude bits

Binary value (8 bit) Two's complement interpretation

Unsigned interpretation

00000000 0 0

00000001 1 1

⋮ ⋮ ⋮01111110 126 126

01111111 127 127

10000000 −128 128

10000001 −127 129

10000010 −126 130

⋮ ⋮ ⋮11111110 −2 254

11111111 −1 255

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s General CPU Diagram

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s Von Neumann vs Harvard architectures

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s Microcontroller

• Single chip, with:– Microprocessor CPU– Memory

• RAM (data)• PROM/

EEPROM (program)– Internal Clock

Oscillator– timers – watchdog timer– I/O peripherals

• Digital pins• Analog (ADCs, DAC)• Communication

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s Atmel/AVR CPU Architecture

• Harvard architecture– 8 bit data bus/ALU– RISC 16 bit instruction set

• Set of Internal Registers– 32 “working” registers (GPR)– “Program counter” (PC)

has 14 bits address lines for the Flash Program memory

– “Instruction register” (IR) Last Instruction read

– “Stack Pointer”,pointer to STACK (zone on Data memory, LIFO type)

– “Status Register”, SREG, is an 8-bit flag register. Each bit in SREG represents a different flag or condition. Changed after ALU Operations

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s Arquitecture of AVR CPU (8bit)

• Reduced Instruction Set Computer (RISC)– Set of simple instructions that allow hardware

simplification and lower cost.– Optimized C compilers– Instructions are executed in every clock cycle

• 16 bit Instructions, with 0 to 2 8-bit operands – (add r1, r3)

– Instructions may use all of the 32 GPR• “Load-store memory access” model: to operate data

stored in Data Memory it is necessary first to fetch values to GPR, and afterwards to save the result back in Memory

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s Arquitecture of AVR CPU

• Modified Harvard Memory Model: Program and Data memories are physically separated in two “address spaces”. “Modified” since it allows CPU to read/write data to Program memory

• Two-stage Instruction Pipeline (fetch and execute): Parallel instruction fetches and executions are enabled by the Harvard architecture. 20MHz ~ 20 MIPS

ATmega48A/PA/88A/PA/168A/PA/328/P

¤ 2020 Microchip Technology Inc. Data Sheet Complete DS40002061B-page 23

7.6 Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 7-4. The Parallel Instruction Fetches and Instruction Executions

Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 7-5. Single Cycle ALU Operation

7.7 Reset and Interrupt HandlingThe AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section ”Memory Programming” on page 289 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 66. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 66 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by

clk

1st Instruction Fetch1st Instruction Execute

2nd Instruction Fetch2nd Instruction Execute

3rd Instruction Fetch3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

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s AVR-ALU

• Arithmetic Logic Unit– 3 types of operations : Arithmetic,

Logical and Bit functions– Operate with data stored on one or

two GPR 32x8bit registers. (R0 to R31)

• Instructions execute in one clock cycle• Some instructions allow 16 bit

operations. – Result is stored on the first operand

(add r1, r3)– Status Register (SREG) flags are modified



7.3.1 SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N � V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

7.4 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

z One 8-bit output operand and one 8-bit result input

Bit 7 6 5 4 3 2 1 0

0x3F (0x5F) I T H S V N Z C SREGRead/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0



7. AVR CPU Core

7.1 OverviewThis section discusses the AVR core architecture in general. The main function of the CPU core is to ensure

correct program execution. The CPU must therefore be able to access memories, perform calculations, control

peripherals, and handle interrupts.

Figure 7-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate

memories and buses for program and data. Instructions in the program memory are executed with a single level

pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory.

This concept enables instructions to be executed in every clock cycle. The program memory is In-System

Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle

access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two

FlashProgramMemory

InstructionRegister

InstructionDecoder

ProgramCounter

Control Lines

32 x 8GeneralPurpose

Registrers

ALU

Statusand Control

I/O Lines

EEPROM

Data Bus 8-bit

DataSRAM

Dire

ct A

ddre

ssin

g

Indi

rect

Add

ress

ing

InterruptUnit

SPIUnit

WatchdogTimer

AnalogComparator

I/O Module 2

I/O Module1

I/O Module n

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s ALU STATUS REGISTER



7.3.1 SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N � V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

7.4 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

z One 8-bit output operand and one 8-bit result input

Bit 7 6 5 4 3 2 1 0

0x3F (0x5F) I T H S V N Z C SREGRead/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• I: Global Interrupt Enable• T: Copy Storage• H: Half Carry Flag (operations with BCD numbers)• S : Sign Flag: S = N xor V• V : Two's Compliment Overflow Flag

(signed numbers [-128, +127])• N : Negative Flag• Z : Zero Flag (1 if the result is zero)• C : Carry Flag (overflow of unsigned numbers [0, 255])

• Flag Bits H, S,V,N, and C are used with in conditional Jump/Branch Instructions to change Program sequence.

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s AVR General purpose working (file registers)• ALU instructions

work only with data from GPR registers ( one clock cycle)– add r1, r3mov r8, r7

• Only registers R16 to R31 may be initialized with a constant (literal)– ldi r16, 200



z Two 8-bit output operands and one 8-bit result inputz Two 8-bit output operands and one 16-bit result inputz One 16-bit output operand and one 16-bit result input

Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 7-2. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

7.4.1 The X-register, Y-register, and Z-register

The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3.

Figure 7-3. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

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s AVR Data Memory / SRAM• Data memory consists of :

– Registers- consists of 32 general purpose working 8-bit registers (R0-R31)

– I/O Memory for peripheral functions, such as control registers and other I/O functions, 64 locations accessible by the IN/OUT bus

– Extended I/O Memory, Extended Peripherals– Internal SRAM- Store variables within a software application, and

STACK

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s AVR Data Memory acesses• Data can be accessed through the standard data bus.

– Different data bus addressing modes for the entire data memory

• The direct addressing, reaches the entire data space. Address is written on the instruction

• Indirect addressing. Reaches data through pointers X, Y, and Z

• Secondary In/Out bus– direct faster access to the 64-byte I/O Memory

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s SRAM direct access

• Access to entire to SRAM space (Instructions STS e LDS)– ldi r16, 33sts 0x100, r16 ; store to sramlds r17, 0x100 ; load from sram

• Access to Secondary In/Out bus, only 64 addresses (instructions IN, OUT)– ldi r16, 33out 0x5, r16 ; 0x5 =PORTB addressin r20, 0x3 ; 0x3 =PINB address

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s SRAM indirect access

• Equivalent to “C” pointers A = *ptrX;

• Uses 16 bit pointers X, Y and Z– ldi r16, 13ldi xl, 0x11 ; pointer X=0x0211ldi xh, 0x02st X, r16 ; Store r16 value on address 0x0211ld r17, X ; reads data from address in X pointer to r17

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s SRAM indirect access through pointers

• Can point to any of the SRAM address space (0x0000- 0x08FF), need at least 12 bits.

• Uses two GPR regs per pointer:X (r27:r26), Y (r29:r28) and Z (r31:r30)

• Pointer Z allows also to read/write data from/to Program Flash Memory



z Two 8-bit output operands and one 8-bit result inputz Two 8-bit output operands and one 16-bit result inputz One 16-bit output operand and one 16-bit result input

Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 7-2. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

7.4.1 The X-register, Y-register, and Z-register

The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3.

Figure 7-3. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

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s STACK Zone of Data memory• The STACK is a memory zone used by the CPU to store data or

addresses temporally– Storing CPU data to stack is called “PUSH”. The opposite is called

“POP” operation– CPU register “Stack Pointer” (SP), saves the next address to

store data – The data store/read is done in LIFO style (Last In/First Out), – In AVR architecture Stack zone is located in the end of Data

Memory – On reset the SP is initialized to last SRAM address. When

stack “grows”, SP decrements– Instruction push r16 stores the data in reg R16 on “top”

of stack and decrement SP– pop r16, increments SP and loads last saved data to R16

number to the stack, it is analogous to placing a plate on the table. Save another number(or plate) and this goes on top of the first one. Save a third, and now we have 3 numbers(or plates) stacked up. The numbers in the stack are stored consecutively in memory andthe list of numbers grows closer toward lower memory. So numbers can be pushed ontothe stack and at any time they can be pulled off, but to get to the first number (or bottomplate), one first has to pull off the topmost numbers (or plates), one at a time. This type ofstack is called LIFO, or Last-In First-Out. Immediate access is limited to only the topmostitem. You can either push a number onto the stack or take the top number off.

To keep track of the last byte pushed onto the stack, there is a pointer called the stackpointer (SP). Normally you should not be concerned with the value of the SP, but doremember that on the AVR the SP points to the next available unused byte (see the fol-lowing figure). The stack on the AVR is initialized to the last available byte in SRAM. Onthe ATmega328, this is memory location 0x08ff. Thus, you need not initialize the SP, butif you need to you can. For the AVR, as you push data onto the stack, the stack growstoward lower memory addresses. The AVR’s SP is 16 bits. The register SPH is the upper8 bits, while the register SPL is the lower 8 bits of SP.

The syntax for pushing register r16 onto the stack is: push r16

The syntax for pulling register r16 from the stack is: pop r16

This example demonstrates how to swap r16 and r17 using the stack.

push r16push r17pop r16pop r17

What is the limit to our example with the plates? You can place plates onto the stack untilyou run into the ceiling. A similar thing happens with the stack on the AVR. Here, thelimitation is available memory space. Generally, there is no warning whatsoever whenthe computer stack overflows, and it will most likely crash at that point. On the AVR,

78 Chapter 2 n AVR Programming

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s STACK memory and Calling subroutines

• The STACK is automatically used whenever you call a subroutine.– Instruction “call some_function”, “pushes”

the return PC address to stack– Instruction ”ret” in the end of the subroutine,

“pops” PC to the program address of the next instruction after “call some_function”

ldi r16,0x01 ; load r16 with 0x01ldi r17,0x02 ; load r17 with 0x02

call addReg ; call subroutineloop: rjmp loop ; infinite loop

addReg:add r16,r17 ; add r16 and r17ret

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s AVR – Program memory (Flash)• Non volatile memory, 32KBytes,

organized by 16bits words . • Atmega328P can have up to 16K lines

of code – Each line contains a machine coded

instruction– CPU register “PC”, program counter,

contains the address of next instruction to be loaded to the CPUAt CPU Reset, PC = 0x000

– In normal programs sequence PC =>(PC+1), except when there are jumps or calling subroutines or Interrupts

• Divided in two sections :– Zone for compiled Programs– Boot Loader: allows to upload

programs through the serial/USB interface



Figure 8-1. Program Memory Map ATmega 48A/48PA

Figure 8-2. Program Memory Map ATmega88A, ATmega88PA, ATmega168A, ATmega168PA, ATmega328 and ATmega328P

0x0000

0x7FF

Program Memory

Application Flash Section

0x0000

0x0FFF/0x1FFF/0x3FFF

Program Memory

Application Flash Section

Boot Flash Section

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s Instructions AVR

• Each Instruction occupies 1 or 2 lines of the FLASH memory– One instruction contains a machine opcode and one or two

operands– Each machine opcode corresponds to a mnemonic in Assembly

• Main instruction types:– Arithmetic and Logical, use the ALU (ADD, AND, OR …)

– Bit and Bit Test: also use ALU. Change individual bits in GPR and SREG register

– Branch Control: control program sequence– Data Transfer – MCU control (NOP, SLEEP..)

• See complete list in Atmega328P datasheet (chapter 37)

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s ALU Instruction subset

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s Branch Instructions• Change sequence of the program sequence by changing the PC (program counter)• “Conditional Branch”

– branch is taken if a specified condition is true after an ALU operation– BRBC/BRBS with field “s” being the bit index of the Status Reg, SREG

(ex: BRBS s, k)• If TRUE signed offset K is added to PC to yield new PC • else, the branch is not taken, PC->PC+1

– Also other forms • BREQ, Branch if Z flag is Set (Zero Flag)• SBRS, skip if bit in register is SET

• “Unconditional Branch” ( Jump or Call)– always change the PC (without condition) – JMP, RJMP, CALL, RCALL

• JMP, RJMP equivalent to GOTO, • CALL/RCALL for subroutines• JMP, CALL the new PC is given as operand• Relative forms, RJMP, RCALL add signed offset to PC

ex: rjmp -5 ; PC->PC+1-5

– RET, RETI, Return instructions from subroutines/interruptions: PC is fetched from STACK

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s Microcontroller ATmega328P

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Eng. Física Tecnológica ArquitecturaComputadores -Aula 2