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324 Power systems electromagnetic transients simulation

Figure 13.3 B asic RTDS rack

follows:

Tandem processor cardThe TPC is used to perform the computations required to model the power system.One TPC contains two independent digital signal processors (DSPs) and its hardwareis not dedicated to a particular system component. Therefore, it may participate inthe modelling of a transformer in one case, while being used to model a synchronousmachine or a transmission line in another case.

Triple processor cardThe 3PC is used to model complex components, such as FACTS devices, whichcannot be modelled by a TPC. The 3PC is also used to model components whichrequire an excessive number of TPC processors. Each 3PC contains three analoguedevices (ADSP21062), based on the SHARC (Super Harvard ARchitecture) chip;these enable the board to perform approximately six times as many instructions as aTPC in any given period.

Similarly to theTPC, thefunctionof a given processor is notcomponentdedicated.Inter-rack communication cardThe IRC card permits direct communications between the rack in which it is installedand up to six other racks. In a multirack simulation, the equations representing

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Transient simulation in real time 325

different parts of the power system can be solved in parallel on the individual racksand the required data exchanged between them via the IRC communication channels.

Thus a multirack RTDS is able to simulate large power systems and still maintainreal-time operation. The IRC communication channels are dedicated and differentfrom the Ethernet communications between the host workstation and the simulator.

Workstation interface cardThe WIC is an M68020-based card, whose primary function is to handle the com-munications requests between the RTDS simulator and the host workstation. Eachcard contains an Ethernet transceiver and is assigned its own Ethernet address, thusallowing the connection of the RTDS racks to any standard Ethernet-based local areanetwork.

All the low level communication requests between the simulator and the host

workstation are handled by the high level software running on the host workstationand the multitasking operating system being run by the WICs M68020 processor.RTDS simulation uses two basic software tools, a Library of Models and

Compilers and PSCAD, a Graphical User Interface.PSCAD allows the user to select a pictorial representation of the power system

or control system components from the library in order to build the desired circuit.The structure of PSCAD is described in Appendix A with reference to the EMTDCprogram. Although initially the RTDS PSCAD was the original EMTDC version,due to the RTDS special requirements, it has now developed into a different product.The latter also provides a script language to help the user to describe a sequence of commands to be used for either simulation, output processing or circuit modication.This facility, coupled with the multi-run feature, allows many runs to be performedquickly under a variety of operating conditions.

Once the system has been drawn and the parameters entered, the appropriate com-piler automatically generates the low level code necessary to perform the simulationusing the RTDS. Therefore this software determines the function of each processorcard for each simulation. In addition, the compiler automatically assigns the role thateach DSP will play during the simulation, based on the required circuit layout andthe available RTDS hardware. It also produces a user readable le to direct the userto I/O points which may be required for interfacing of physical measurement, protec-tion or control equipment. Finally, subsystems of tightly coupled components can beidentied and assigned to different RTDS racks in order to reduce the computationalburden on processors.

The control system software allows customisation of control system modules. Italso provides greater exibility for the development of sequences of events for thesimulations.

13.2.2 RTDS applications

Protective relay testingCombined with appropriate voltage and current amplication, the RTDS can be usedto perform closed-loop relay tests, ranging from the application of simple voltageand current waveforms through to complicated sequencing within a complex power

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bus voltages line currents bus voltages line currents

amplified

RTDS Voltage & current amplifiers Physical relay(s)

breaker trip/reclose signals

Figure 13.4 RTDS relay set-up

system model. The availability of an extensive library, which includes measurementtransducers, permits testing the relays under realistic system conditions. The relay isnormally connected via analogue output channels to voltage and current ampliers.Auxiliary contacts of the output relay are, in turn, connected back to circuit breakermodels using the RTDS digital input ports. A sketch of the relay testing facility isshown in Figure 13.4.

By way of example, Figure 13.5 shows a typical set of voltages and currents at thelocation of a distance protection relay [5]. The fault condition was a line-to-line shorton thehigh voltageside of a generator step-up transformer connected to a transmissionline. The diagrams indicate the position of the relay trip signal, the circuit breakersopening (at current zero crossings) and the reclosing of the circuit breaker after faultremoval.

Control system testingSimilarly to the concept described above for protection relay testing, the RTDS canbe applied to the evaluation and testing of control equipment. The signals required bythe control system (analogue and/or digital) are produced during the power systemsimulation, while the controller outputs are connected to input points on the particularpower system component under simulation. This process closes the loop and permitsthe evaluation of the effect of the control system on the system under test.

Figure 13.6 illustrates a typical conguration for HVDC control system tests,where analogue voltage and current signals are passed to the control equipment,which in turn issues ring pulses to the HVDC converter valves in the power systemmodel [9].

Figure 13.7 shows typical captured d.c. voltage and current waveforms that occurfollowing a three-phase line to ground fault at the inverter end a.c. system.

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30.0000

18.0000

6.0000

6.0000

18.0000

30.0000

85.0000

51.0000

17.0000

17.0000

51.0000

85.0000

Phase A Phase CPhase B

Phase A

Case 4-1 AB fault beyond transformer (dy)

Phase CPhase B

V o

l t a g e

( k V )

C u r r e n

t ( k A )

Figure 13.5 Phase distance relay results

commutating bus voltages d.c. current & voltage valve current zero pulses

firing pulses block/bypass signal

. .. .

.. .. ..

RTDS HVDCcontrol system

Figure 13.6 HVDC control system testing

13.3 Real-time implementation on standard computers

This section describes a DTNA that can perform real-time tests on a standard mul-tipurpose parallel computer. The interaction between the real equipment under testand the simulated power system is carried out at every time step. A program basedon the parallel processing architecture is used to reduce the solution time [10], [11].

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3.002.502.001.501.00

0.500.00

k A

k V

750500250

0 250 500 750

T_3PT_CH-1. out:0:1

T_3PF_CH-1. out:0:2

Id_CH_PI

Ud_CH_PI

Figure 13.7 Typical output waveforms from an HVDC control study

Standard parallel computer

Communication board

Fibre optic links

OutputInput

Amplifiers

D / A

c o n v e r t e r s

D / A

c o n v e r t e r s

D / A

c o n v e r t e r s

D i g i t a l o u t p u

t s

L o g

i c a l o u

t p u

t s

I n t e r f a c e b o a r

d

A / D

c o n v e r t e r s

A / D

c o n v e r t e r s

A / D

c o n v e r t e r s

D i g i t a l

i n p

u t s

L o g

i c a l

i n p u

t s

I n t e r f a c e b o a r

d

Equipmentunder test

Figure 13.8 General structure of the DTNA system

The general structure of the DTNA system is shown in Figure 13.8. A standardHP-CONVEX computer is used, with an internal architecture based on a crossbarthat permits complete intercommunication between the different processors. Thisincreases the computing power linearly with the number of processors, unlike mostcomputers, which soon reach their limit due to bus congestion.

The basic unit input/output (I/O) design uses two VME racks (for up to32 analoguechannels) and allows the testing of three relays simultaneously. Additional VMEracks and I/O boards can be used to increase the number of test components. The

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only special-purpose device to be added to the standard computer is a communicationboard, needed to interface the computer and the I/O systems.

Each board provides four independent 16-bit ADC and DAC converters, allowingthe simultaneous sampling of four analogue inputs. Moreover, all the boards aresynchronised to ensure that all the signals are sampled at exactly the same time.

Each of the digital and logical I/O units provides up to 96 logical channels or12 digital channels. Most standard buses are able to handle large quantities of databut require relatively long times to initialise each transmission. In this application,however, the data sent at each time step is small but the transmission speed mustbe fast; thus, the VME based architecture must meet such requirements. Like otherEMTP based algorithms, the ARENEs version uses a linear interpolation to detectthe switching instants, i.e. when a switching occurs at t x (in the time step betweent and t + t ) then the solution is interpolated back to t x . However, as some of theequipment (e.g. the D/A converters and ampliers) need equal spacing between datapoints, the new values at t x are used as t + t values. Then, in the next step anextrapolation is performed to get back on to the t + 2 t step [12][15].

Finally the characteristics and power rating of the ampliers depend on theequipment to be tested.

13.3.1 Example of real-time test

The test system shown in Figure 13.9 consists of three lines, each 120 km long anda distance relay (under test). The relay is the only real piece of equipment, the restof the system being represented in the digital simulator and the solution step used is100 s. The simulated currents and voltages monitored by the current and voltage

E

EE

120 km 120 km

20km100km

Distance relay

Current transformer

Capacitor voltage transformer

Figure 13.9 Test system

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Current phase A

Voltage phase A

0.010

0.005

0.000

0.005

0.010

0.10

0.05

0.00

0.05

0.10

4900.0 5100.0 5300.0 5500.0

4900.0 5100.0 5300.0 5500.0Time (ms)

Figure 13.10 Current and voltage waveforms following a single-phase short-circuit

transformers are sent to the I/O converters and to the ampliers. The relays are directlyconnected to these ampliers.

The test conditions are as follows: initially a 5 s run is carried out to achieve thesteady state. Then a single-phase fault is applied to one of the lines 100 km away fromthe relay location.

Some of the results from the real-time simulation are illustrated in Figure 13.10.The top graph shows the current in the faulty phase, monitored on the secondaryof the simulated current transformer. The lower graph shows the voltage of thefaulty phase, monitored on the secondary of the simulated capacitive voltagetransformer.

Important information derived from these graphs is the presence of some residualvoltage in the faulty phase, due to capacitive coupling to other phases (even thoughthe line is opened at both ends). The self-extinguishing fault disappears after 100 ms.The relay recloser sends a closing order to the breakers after 330 ms. Then after atransient period the current returns to the steady-state condition.

13.4 Summary

Advances in digital parallel processing, combined with the ability of power systemsto be processed by means of subsystems, provides the basis for real-time transientsimulation.

Simulation in real-time permits realistic testing of the behaviour of control andprotection systems. This requires the addition of digital to analogue and analogue todigital converters, as well as analogue signal ampliers.

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The original, and at present still the main application in the market, is a simula-tor based on dedicated architecture called RTDS (real-time digital simulator). Thisunit practically replaced all the scale-down physical simulators and can potentiallyrepresent any size system,

The development of multipurpose parallel computing is now providing the basisfor real-time simulation using standard computers instead of dedicated architectures,and should eventually provide a more economical solution.

13.5 References

1 KUFFEL, P., GIESBRECHT, J., MAGUIRE, T., WIERCKX, R. P. and

Mc LAREN, P.: RTDS a fully digital power system simulator operating inreal-time, Proceedings of the ICDS Conference, College Station, Texas, USA,April 1995, pp. 1924

2 WIERCKX, R. P.: Fully digital real time electromagnetic transient simula-tor, IERE Workshop on New Issues in Power System Simulation , 1992, VII ,pp. 128228

3 BRANDT, D., WACHAL, R., VALIQUETTE, R. and WIERCKX, R. P.: Closedloop testing of a joint VAr controller using a digital real-time simulator for HVdcsystem and control studies, IEEE Transactions on Power Systems , 1991, 6 (3),

pp. 11406.4 WIERCKX, R. P., GIESBRECHT W. J., KUFFEL, R. et al .: Validation of a fullydigital real time electromagnetic transient simulator for HVdc system and controlstudies, Proceedings of the Athens Power Tech. Conference, September 1993,pp. 7519

5 Mc LAREN, P. G., KUFFEL, R., GIESBRECHT, W. J., WIERCKX, R. P. andARENDT, L.: A real time digital simulator for testing relays, IEEE Transactionson Power Delivery , January 1992, 7 (1), pp. 20713

6 KUFFEL, R., M c LAREN, P., YALLA, M. and WANG, X.: Testing of theBeckwith electric M-0430 multifunction protection relay using a real-time digitalsimulator (RTDS), Proceedings of International Conference on Digital Power System Simulators (ICDS) , College Station, Texas, USA, April 1995, pp. 4954.

7 Mc LAREN, P., DIRKS, R. P., JAYASINGHE, R. P., SWIFT, G. W. andZHANG, Z.: Using a real time digital simulator to develop an accurate model of a digital relay, Proceedings of International Conference on Digital Power SystemSimulators, ICDS95 , April 1995, p. 173

8 Mc LAREN, P., SWIFT, G. W., DIRKS, R. P. et al .: Comparisons of relaytransient test results using various testing technologies, Proceedings of Sec-ond International Conference on Digital Power System Simulators, ICDS97 ,May 1997, pp. 5762

9 DUCHEN, H., LAGERKVIST, M., KUFFEL, R. and WIERCKX, R.: HVDCsimulation and control system testing using a real-time digital simulator (RTDS),Proceedings of the ICDS Conference, College Station, Texas, USA, April 1995,p. 213

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10 STRUNZ, K. and MULLER, S.: New trends in protective relay testing, Proceed-ings of Fifth International Power Engineering Conference (IPEC), May 2001, 1,pp. 45660

11 STRUNZ, K., MARTINOLE, P., MULLER, S. and HUET, O.: Control systemtesting in electricity market places, Proceedings of Fifth International PowerEngineering Conference (IPEC), May 2001

12 STRUNZ, K., LOMBARD, X., HUET, O., MARTI, J. R., LINARES, L.and DOMMEL, H. W.: Real time nodal analysis-based solution techniquesfor simulations of electromagnetic transients in power electronic systems,Proceedings of Thirteenth Power System Computation Conference (PSCC),June 1999, Trondheim, Norway, pp. 104753

13 STRUNZ, K. and FROMONT, H.: Exact modelling of interaction between gatepulse generators and power electronic switches for digital real time simula-tors, Proceedings of Fifth Brazilian Power Electronics Conference (COBEP),September 1999, pp. 2038

14 STRUNZ, K., LINARES, L., MARTI, J. R., HUET, O. and LOMBARD, X.:Efcient and accurate representation of asynchronous network structure changingphenomena in digital real time simulators, IEEE Transactions on Power Systems ,2000, 15 (2), pp. 58692

15 STRUNZ, K.: Real time high speed precision simulators of HDC extinctionadvance angle, Proceedings of International Conference on Power SystemsTechnology (PowerCon2000) , December 2000, pp. 106570

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Appendix A

Structure of the PSCAD/EMTDC program

PSCAD/EMTDC version 2 consists of a set of programs which enable the efcientsimulation of a wide variety of power system networks. EMTDC (ElectromagneticTransient and DC) [1], [2], although based on the EMTP method, introduced a numberof modications so that switching discontinuities could be accommodated accuratelyand quickly [3], the primary motivation being the simulation of HVDC systems.PSCAD (Power Systems Computer Aided Design) is a graphical Unix-based userinterface for the EMTDC program. PSCAD consists of software enabling the user to

enter a circuit graphically, create new custom components, solve transmission lineand cable parameters, interact with an EMTDC simulation while in progress and toprocess the results of a simulation [4].

The programs comprising PSCAD version 2 are interfaced by a large numberof data les which are managed by a program called FILEMANAGER. This pro-gram also provides an environment within which to call the other ve programs andto perform housekeeping tasks associated with the Unix system, as illustrated inFigure A.1. The starting point for any study with EMTDC is to create a graphicalsketch of the circuit to be solved using the DRAFT program. DRAFT provides the

user with a canvas area and a selection of component libraries (shown in Figure A.2).

Filemanager

Cable TLine Draft Runtime

EMTDC

UniPlot MultiPlot

Figure A.1 The PSCAD/EMTDC Version 2 suite

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Figure A.2 DRAFT program

A library is a set of component icons, any of which can be dragged to the canvasarea and connected to other components by bus-work icons. Associated with eachcomponent icon is a form into which component parameters can be entered. Theuser can create component icons, the forms to go with them and FORTRAN code todescribe how the component acts dynamically in a circuit. Typical components aremulti-winding transformers, six-pulse groups, control blocks, lters, synchronous

machines, circuit-breakers, timing logic, etc.The output from DRAFT is a set of les which are used by EMTDC. EMTDCis called from the PSCAD RUNTIME program, which permits interactions with thesimulation while it is in progress. Figure A.3 shows RUNTIME plotting the outputvariables as EMTDC simulates. RUNTIME enables the user to create buttons, slides,dials and plots connected to variables used as input or output to the simulation (shownin Figure A.4). At the end of simulation, RUNTIME copies the time evolution of specied variables into data les. The complete state of the system at the end of simulation can also be copied into a snapshot le, which can then be used as thestarting point for future simulations. The output data les from EMTDC can be plottedand manipulated by the plotting programs UNIPLOT or MULTIPLOT. MULTIPLOTallows multiple pages to be laid out, with multiple plots per page and the results fromdifferent runs shown together. Figure A.5 shows a MULTIPLOT display of the resultsfrom two different simulations. A calculator function and off-line DFT function are

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Structure of the PSCAD/EMTDC program 335

Figure A.3 RUNTIME program

Figure A.4 RUNTIME program showing controls and metering available

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Figure A.5 MULTIPLOT program

also very useful features. The output les can also be processed by other packages,such as MATLAB, or user-written programs, if desired. Ensure % is the rst characterin the title so that the les do not need to be manually inserted after each simulationrun if MATLAB is to be used for post-processing.

All the intermediate les associated with the PSCAD suite are in text formatand can be inspected and edited. As well as compiling a circuit schematic to input

les required by EMTDC, DRAFT also saves a text-le description of the schematic,which can be readily distributed to other PSCAD users. A simplied description of the PSCAD/EMTDC suite is illustrated in Figure A.6. Not shown are many batchles, operating system interface les, set-up les, etc.

EMTDC consists of a main program primarily responsible for nding the network solution at every time step, input and output, and supporting user-dened componentmodels. The user must supply two FORTRAN source-code subroutines to EMTDC DSDYN.F and DSOUT.F. Usually these subroutines are automatically generated byDRAFT but they can becompletely written or editedby hand. At the start of simulationthese subroutines are compiled and linked with the main EMTDC object code.

DSDYN is called each time step before the network is solved and provides anopportunity for user-dened models to access node voltages, branch currents or inter-nal variables. The versatility of this approach to user-dened component modulesmeans that EMTDC has enjoyed wide success as a research tool. A owchart for the

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Structure of the PSCAD/EMTDC program 337

TLINE

FILEMANAGER

Componentlibraries

Schematicdescription

FORTRANcompiler

Snapshotfile

Workstation

User Interaction

UNIPLOT MATLAB

Runtime batch file

CABLE

DRAFT

Systemdata file

Make file

FORTRANfiles

EMTDCexecutable

outputdatafiles

RUNTIME

Laser printer

postscriptfile

MULTIPLOT

OR

CABLEdataTLINE data

Figure A.6 Interaction in PSCAD/EMTDC Version 2

EMTDC program, illustrated in Figure A.7, indicates that the DSOUT subroutine iscalled after the network solution. The purpose of the subroutine is to process variablesprior to being written to an output le. Again, the user has responsibility for supplyingthis FORTRAN code, usually automatically from DRAFT. The external multiple-runloop in Figure A.7 permits automatic optimisation of system parameters for somespecied goal, or the determination of the effect of variation in system parameters.

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