Emergency Light Flash MCU · PWM outputs with a dead time insertion, are used to drive an internal PMOS transistor and an external NMOS transistor to implement the synchronous rectification

Emergency Light Flash MCU

HT45FH4J

Revision: V1.10 Date: Deee 1 01Deee 1 01

Rev. 1.10 Deee 1 01 Rev. 1.10 3 Deee 1 01

HT45FH4JEmergency Light Flash MCU


Table of Contents

Features ............................................................................................................ 6CPU Featues ......................................................................................................................... Peipheal Featues ................................................................................................................. Eegeny Light Appliation Featues ....................................................................................

General Description ........................................................................................ 7Block Diagram .................................................................................................. 7Pin Assignment ................................................................................................ 8Pin Descriptions .............................................................................................. 9Absolute Maximum Ratings ...........................................................................11D.C. Characteristics ........................................................................................11A.C. Characteristics ....................................................................................... 13LVD&LVR Electrical Characteristics ............................................................ 14ADC Electrical Characteristics ..................................................................... 15LDO Regulator Electrical Characteristics ................................................... 15Over Current Pretection Electrical Characteristics .................................... 16Power-on Reset Electrical Characteristics .................................................. 16System Architecture ...................................................................................... 17

Cloking and Pipelining ......................................................................................................... 17Poga Counte ................................................................................................................... 18Stak ..................................................................................................................................... 19Aitheti and Logi Unit – ALU ........................................................................................... 19

Flash Program Memory ................................................................................. 20Stutue ................................................................................................................................ 0Speial Vetos ..................................................................................................................... 0Look-up Tale ........................................................................................................................ 1Tale Poga Exaple ........................................................................................................ In Ciuit Pogaing ......................................................................................................... 3On-Chip Deug Suppot – OCDS .........................................................................................

RAM Data Memory ......................................................................................... 25Stutue ................................................................................................................................ 5

Special Function Register Description ........................................................ 27Indiet Addessing Registes – IAR0 IAR1 ......................................................................... 7Meoy Pointes – MP0 MP1 .............................................................................................. 7Bank Pointe – BP ................................................................................................................. 8Auulato – ACC ............................................................................................................... 8Poga Counte Low Registe – PCL .................................................................................. 8Look-up Tale Registes – TBLP TBHP TBLH ..................................................................... 8Status Registe – STATUS .................................................................................................... 9

Rev. 1.10 Deee 1 01 Rev. 1.10 3 Deee 1 01



EEPROM Data Memory .................................................................................. 31EEPROM Data Meoy Stutue ........................................................................................ 31EEPROM Registes .............................................................................................................. 31Reading Data fo the EEPROM ........................................................................................ 33Witing Data to the EEPROM ................................................................................................ 33Wite Potetion ..................................................................................................................... 33EEPROM Inteupt ................................................................................................................ 33Pogaing Consideations ................................................................................................ 3

Oscillator ........................................................................................................ 35Osillato Oveview ............................................................................................................... 35System Clock Configurations ................................................................................................ 35Intenal RC Osillato – HIRC ............................................................................................... 3Intenal 3kHz Osillato – LIRC ........................................................................................... 3

Operating Modes and System Clocks ......................................................... 36Syste Cloks ...................................................................................................................... 3Syste Opeation Modes ...................................................................................................... 37Contol Registe .................................................................................................................... 39Opeating Mode Swithing ................................................................................................... 1NORMAL Mode to SLOW Mode Swithing ........................................................................... 1SLOW Mode to NORMAL Mode Swithing .......................................................................... Enteing the SLEEP Mode .................................................................................................... Enteing the IDLE0 Mode ...................................................................................................... 3Enteing the IDLE1 Mode ...................................................................................................... 3Standy Cuent Consideations ........................................................................................... 3Wake-up ................................................................................................................................

Watchdog Timer ............................................................................................. 45Wathdog Tie Clok Soue .............................................................................................. 5Wathdog Tie Contol Registe ......................................................................................... 5Wathdog Tie Opeation ...................................................................................................

Reset and Initialisation .................................................................................. 47Reset Funtions .................................................................................................................... 7Reset Initial Conditions ......................................................................................................... 50

Input/Output Ports ......................................................................................... 53Pull-high Resistos ................................................................................................................ 53Pot A Wake-up ..................................................................................................................... 5I/O Pot Contol Registes ..................................................................................................... 5Pin-shaed Funtions ............................................................................................................ 55Pin-shaed Funtion Seletion Registes .............................................................................. 55I/O Pin Stutues .................................................................................................................. 5Pogaing Consideations ................................................................................................ 57

Rev. 1.10 Deee 1 01 Rev. 1.10 5 Deee 1 01



Timer Modules – TM ...................................................................................... 58Intodution ........................................................................................................................... 58TM Opeation ........................................................................................................................ 58TM Clok Soue ................................................................................................................... 58TM Inteupts ......................................................................................................................... 58TM Extenal Pins ................................................................................................................... 59TM Input/Output Pin Contol ................................................................................................. 59Pogaing Consideations ................................................................................................ 0

Periodic Type TM – PTM ................................................................................ 61Peiodi TM Opeation .......................................................................................................... 1Peiodi Type TM Registe Desiption ................................................................................. Peiodi Type TM Opeating Modes ...................................................................................... Copae Math Output Mode ............................................................................................... Tie/Counte Mode ............................................................................................................. 9PWM Output Mode ................................................................................................................ 9Single Pulse Output Mode .................................................................................................... 71Captue Input Mode .............................................................................................................. 73

Analog to Digital Converter .......................................................................... 75A/D Oveview ........................................................................................................................ 75A/D Convete Registe Desiption ...................................................................................... 7A/D Convete Data Registes – SADOL SADOH ................................................................ 7A/D Convete Contol Registes – SADC0 SADC1 ............................................................. 7A/D Opeation ....................................................................................................................... 78A/D Input Pins ....................................................................................................................... 80Convesion Rate and Tiing Diaga .................................................................................. 80Suay of A/D Convesion Steps ....................................................................................... 81Pogaing Consideations ................................................................................................ 8A/D Tansfe Funtion ........................................................................................................... 8A/D Pogaing Exaples ................................................................................................. 83

Complementary PWM output ....................................................................... 85Over Current Protection ............................................................................... 87

Ove Cuent Potetion Opeation ....................................................................................... 87Ove Cuent Potetion Contol Registes ........................................................................... 88Input Voltage Range .............................................................................................................. 91Offset Caliation .................................................................................................................. 9

Emergency Light Application Description .................................................. 93Chage unde Noal Mains Supply ..................................................................................... 93Analog Battey Boost Chage unde Noal Mains Supply ................................................. 93Buzze Diving ....................................................................................................................... 93LED Diving ........................................................................................................................... 93

High Voltage MOS .......................................................................................... 94Contol Registes .................................................................................................................. 9

Rev. 1.10 Deee 1 01 Rev. 1.10 5 Deee 1 01



Interrupts ........................................................................................................ 98Inteupt Registes ................................................................................................................. 98Inteupt Opeation .............................................................................................................. 103Extenal Inteupt ................................................................................................................. 10OCP Inteupt ...................................................................................................................... 105Multi-funtion Inteupt ........................................................................................................ 105A/D Convete Inteupt ....................................................................................................... 105Tie Base Inteupts ........................................................................................................... 10EEPROM Inteupt .............................................................................................................. 107LVD Inteupt ....................................................................................................................... 107TM Inteupts ....................................................................................................................... 107Inteupt Wake-up Funtion ................................................................................................. 108Pogaing Consideations .............................................................................................. 108

Low Voltage Detector – LVD ....................................................................... 109LVD Registe ....................................................................................................................... 109LVD Opeation ......................................................................................................................110

Configuration Option ....................................................................................110Application Circuit ........................................................................................111

Eegeny Light Appliation Ciuit (LED unde 0.W) .......................................................111Eegeny Light Appliation Ciuit (LED ove 1W) ............................................................11

Instruction Set ...............................................................................................113Intodution ..........................................................................................................................113Instution Tiing .................................................................................................................113Moving and Tansfeing Data ..............................................................................................113Aitheti Opeations ...........................................................................................................113Logial and Rotate Opeation ..............................................................................................11Banhes and Contol Tansfe ............................................................................................11Bit Opeations ......................................................................................................................11Tale Read Opeations ........................................................................................................11Othe Opeations ..................................................................................................................11

Instruction Set Summary .............................................................................115Tale Conventions ................................................................................................................115

Instruction Definition ....................................................................................117Package Information ................................................................................... 126

1-pin NSOP (150il) Outline Diensions ......................................................................... 170-pin SSOP (150il) Outline Diensions ......................................................................... 18

Rev. 1.10 Deee 1 01 Rev. 1.10 7 Deee 1 01



Features

CPU Features• Highvoltageinput(upto12V)totheintegratedLDOandoutputs5VtosupplyMCUoperatingvoltage

• Upto0.2μsinstructioncyclewith20MHzsystemclockatVDD=5V• Powerdownandwake-upfunctionstoreducepowerconsumption• Oscillators

♦ Internal12/16/20MHzHightSpeedRC--HIRC♦ InternalLowSpeed32kHzRC--LIRC

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP• Allinstructionsexecutedinoneortwoinstructioncycles• Tablereadinstructions• 63powerfulinstructions• 4-levelsubroutinenesting• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:2K×16

• RAMDataMemory:128×8• TrueEEPROMMemory:64×8• WatchdogTimerfunction• 12bidirectionalI/Olines• Twopin-sharedexternalinterrupts• MultipleTimerModulefortimemeasure,inputcapture,comparematchoutput,PWMoutputfunctionorsinglepulseoutputfunction

• TwocomplementaryPWMoutputwithdeadtimecontrol• Overcurrentprotection(OCP)withinterrupt• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals• 6externalchannels12-bitresolutionA/Dconverter• Lowvoltageresetfunction• Lowvoltagedetectfunction• Package:16-pinNSOP,20-pinSSOP

Emergency Light Application Features• OneintegratedLDO:5VoutputtosupplyoperatingvoltagefortheMCU,LEDindicatorandothercircuits.

• Oneintegratedresistordivider,itsDC/DCboostvoltageisusedforcloseloopcontrol• OneinternalPMOSanddrivinganexternalNMOScanimplementtheDC/DCboostandbuckcontrol

• InternalLEDdrivingcircuit(0.6W)• SupportsanadditionalexternalNMOSforhighpowerLEDdriving(over0.6W)• HighvoltageandhighcurrentoutputforBuzzerdriving(140mA)• OneinternalswitchforemergencylightproductbatteryandLEDlightingself-testfunction

Rev. 1.10 Deee 1 01 Rev. 1.10 7 Deee 1 01



General Description ThisdeviceisanEmergencyLightASSPFlashMCU.Thedeviceincludes2K×16ofFlashProgramMemory,128bytesofDataMemoryand64bytesofDataEEPROM.TheinternalLDOprovidesamaximuminputvoltageof12Vandoutputsa5Vvoltagewithacurrentof50mAwhichcanthenbeprovidedtotheMCUandperipheralcircuits.AdditionalfeaturesincludeonefullyintegratedhighaccuracyRCoscillatorwiththreefixedfrequenciesofeither12MHz,16MHzor20MHz,aninternal6-channel12-bitA/Dconverterandthree10-bitPeriodicTimers.OneoftheseTimerscanbeusedtogeneratetwocomplementaryPWMoutputswhichareusedfortherequiredDC/DCboostandbuckcircuitry.Arangeofprotectionfeaturesareprovided,suchasovercurrentprotection,LowVoltageDetectorandLowVoltageReset,whichareusedforsystemvoltagemonitoring. If thesystemvoltagefallsbelowtheLVRvalue,thedevicewillbeautomaticallyresettoreducethepossibilityofunstableoperations.

In the traditional emergency light applications, amicrocontrollerusually requiresadditionaltransistorstodriveLEDs,buzzersaswellastheboostandbuckcircuits.However,thisnewdeviceincludesapowerfuldrivingcapability, itcandirectlydriveLEDswithacurrentof100mAandbuzzerswithacurrentof140mA.Duringbatterycharginganddischarging, thecomplementaryPWMoutputswithadead timeinsertion,areused todrivean internalPMOStransistorandanexternalNMOStransistortoimplementthesynchronousrectificationfunction.Thedeviceisabletoreducethepowerconsumptiontoaminimum,improvetheoperatingefficiencyandextendtheLEDilluminationtime.Asforprotectionfeatures, theovercurrentprotectioncircuitryensuresthattheLEDsandthebatteryremainfreefromdamagewhenovercurrentoccurs.

Block Diagram

8-bitRISCMCUCore

Flash Program Memory

EEPROMData

Memory

Flash/EEPROM Programming Circuitry

RAMData

Memory

TimeBase

Low Voltage Detect

Watchdog Timer

InterruptController

ResetCircuit

Internal RCOscillators

12-bit A/DConverter

I/O

Over Current Protection

Low Voltage Reset

VDD

5V LDO(50mA)

Boot/Buck control

Buzzer driver(140mA)

LED driver(100mA)

Level Shift Level Shift

Timer Module

Timer Module

Timer Module

Level Shift

LED_OUT BZ BAT_IN

OCP0/1

ANx

INTx

HV_IN(7~12V input)

Rev. 1.10 8 Deee 1 01 Rev. 1.10 9 Deee 1 01



Pin Assignment

115113111109

13578

BAT_INBZLED_OUTHVSSPA0/ICPDA/OCDSDAPA/ICPCK/OCDSCKPA1/AN0/TP0PA3/AN1/VREF/INT0/TCK0PA/AN/TP1

PA5/AN3/OCP1/INT1/TCK1PA/AN/OCP0/TP

VSSPA7/AN5/PWM0L/TCK

VDD/LDO_OUTHV_IN/LDO_IN

HV_OUT

HT45FH4J/HT45VH4J16 NSOP-A

BAT_INBZLED_OUTHVSSPA0/ICPDA/OCDSDAPA/ICPCK/OCDSCKPB0/PWM0HPB1PA/AN/TP1

PA5/AN3/OCP1/INT1/TCK1PA/AN/OCP0/TP

VSSPA7/AN5/PWM0L/TCK

VDD/LDO_OUTHV_IN/LDO_IN

HV_OUT

HT45FH4J/HT45VH4J20 SSOP-A

PBPB3PA1/AN0/TP0

PA3/AN1/VREF/INT0/TCK0

0191817115113111

13578910

Note:1.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,thedesiredpin-sharedfunctionisdeterminedbythecorrespondingsoftwarecontrolbits.

2.Theactualdeviceand itsequivalentOCDSEVdeviceshare the samepackage type,howevertheOCDSEVdevicepartnumberisHT45VH4J.PinsOCDSCKandOCDSDAwhicharepin-sharedwithPA2andPA0areonlyusedfortheOCDSEVdevice.

Rev. 1.10 8 Deee 1 01 Rev. 1.10 9 Deee 1 01



Pin DescriptionsWiththeexceptionofthepowerpinsandsomerelevanttransformercontrolpins,allpinsonthisdevicecanbe referencedby theirPortname,e.g.PA0,PA1etc,whichrefer to thedigital I/Ofunctionofthepins.HoweverthesePortpinsarealsosharedwithotherfunctionsuchastheAnalogtoDigitalConverter,TimerModulepinsetc.Thefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.

AsthePinDescriptiontableshowsthesituationforthepackagewiththemostpins,notallpinsinthetablewillbeavailableonsmallerpackagesizes.

Pin Name Function OPT I/T O/T Description

PA0/ICPDA/OCDSDA

PA0 PAPUPAWU ST CMOS Geneal pupose I/O. Registe enaled pull-up and

wake-up.ICPDA — ST CMOS In-iuit pogaing data/addess pin

OCDSDA — ST CMOS On-hip deug suppot data/addess pin only fo EV IC

PA1/AN0/TP0 PA1

PAPUPAWUCTRL3

ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up.

AN0 CTRL3 AN — A/D Convete input 0TP0 CTRL3 ST CMOS TM0 I/O

PA/ICPCK/OCDSCK

PA PAPUPAWU ST CMOS Geneal pupose I/O. Registe enaled pull-up and

wake-up.ICPCK — ST — In-iuit pogaing lok pin

OCDSCK — ST — On-hip deug suppot lok pin only fo EV IC

PA3/AN1/VREF/INT0/TCK0

PA3PAPUPAWUCTRL3


AN1 CTRL3 AN — A/D Convete input 1VREF CTRL3 AN — A/D Convete efeene voltage input

INT0CTRL3INTEGINTC1

ST — Extenal inteupt 0

TCK0 CTRL3TM0C0 ST — TM0 lok input

PA/AN/TP1PA

PAPUPAWUCTRL3


AN CTRL3 AN — A/D Convete input TP1 CTRL3 ST CMOS TM1 I/O

PA5/AN3/OCP1/INT1/TCK1

PA5PAPUPAWUCTRL3


AN3 CTRL3 AN — A/D Convete input 3

OCP1 CTRL3 AN — Ove uent potetion input

INT1CTRL3INTEGINTC1

ST — Extenal inteupt 1

TCK1 CTRL3TM1C0 ST — TM1 lok input

Rev. 1.10 10 Deee 1 01 Rev. 1.10 11 Deee 1 01



Pin Name Function OPT I/T O/T Description

PA/AN/OCP0/TP

PAPAPUPAWUCTRL


AN CTRL AN — A/D Convete input

OCP0 CTRL AN — Ove uent potetion input

TP CTRL ST CMOS TM I/O

PA7/AN5/PWM0L/ TCK

PA7PAPUPAWUCTRL


AN5 CTRL AN — A/D Convete input 5PWM0L CTRL — CMOS Copleentay PWM0 output

TCK CTRLTMC0 ST — TM lok input

PB0/PWM0HPB0 PBPU

CTRL ST CMOS Geneal pupose I/O. Registe enaled pull-up

PWM0H CTRL — CMOS Copleentay PWM0 outputPB1~PB3 PB1~PB3 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up

VDD/LDO_OUTVDD — PWR — Positive powe supply

LDO_OUT — PWR — 5V LDO outputHV_IN/LDO_IN LDO_IN — PWR — LDO inputVSS VSS — PWR — Negative powe supplyHigh Voltage I/O PortsBZ BZ — — CMOS Buzze dive outputBAT_IN BAT_IN — PMOS PMOS Battey inputLED_OUT LED_OUT — — PMOS LED dive outputHigh Voltage PowerHV_IN/LDO_IN HV_IN — PWR — Positive powe supply (fo High Voltage)HV_OUT HV_OUT — PWR — High Voltage OutputHVSS HVSS — PWR — Negative powe supply (fo High Voltage)

Note:I/T:InputtypeO/T:OutputtypeOPT:OptionalbyregisteroptionPWR:PowerST:SchmittTriggerinputCMOS:CMOSoutputPMOS:PMOSoutputAN:Analogsignal

Rev. 1.10 10 Deee 1 01 Rev. 1.10 11 Deee 1 01



Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOLTotal..................................................................................................................................... 80mAIOHTotal....................................................................................................................................-80mATotalPowerDissipation......................................................................................................... 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. CharacteristicsTa = 5°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VCC Analog Opeation Voltage — HV_IN pin input voltage 5 7 1 VVDD Opeation Voltage — fSYS=1/1/0MHz -3% 5 +3% V

IDD1Opeation Cuent Noal ModefSYS=fH 5V

No load fH=1MHz ADC off WDT enale — .5 3.8 A

No load fH=1MHz ADC off WDT enale — 3.3 5.0 A

No load fH=0MHz ADC off WDT enale — . .3 A

IDDOpeation Cuent Slow Mode fSYS=fL=fLIRC fSUB=fLIRC

5V No load fSYS=fLIRC ADC off WDT enale — 55 95 μA

IDD3Opeation Cuent Noal Mode fH=1MHz 5V

No load fSYS=fH/ ADC off WDT enale — . 3.3 A

No load fSYS=fH/ ADC off WDT enale — 1.5 .5 A

No load fSYS=fH/8 ADC off WDT enale — 1. 1.8 A

No load fSYS=fH/1 ADC off WDT enale — 1.1 1.5 A


No load fSYS=fH/ ADC off WDT enale — 0.9 1.35 A

Rev. 1.10 1 Deee 1 01 Rev. 1.10 13 Deee 1 01





IDDOpeation Cuent Noal Mode fH=0MHz 5V

No load fSYS=fH/ ADC off WDT enale — .7 .1 A

No load fSYS=fH/ ADC off WDT enale — 1. . A

No load fSYS=fH/8 ADC off WDT enale — 1.5 .3 A


No load fSYS=fH/3 ADC off WDT enale — 1. 1.8 A

No load fSYS=fH/ ADC off WDT enale — 1.15 1.75 A

IIDLE0IDLE0 Mode Standy Cuent (LIRC on) 5V No load ADC off

WDT enale LVR disale — . 38 μA

IIDLE11 IDLE1 Mode Standy Cuent 5V No load ADC off WDT enale fSYS=1MHz on — 1. . A

IIDLE1 IDLE1 Mode Standy Cuent 5V No load ADC off WDT enale fSYS=1MHz on — .0 .0 A

IIDLE13 IDLE1 Mode Standy Cuent 5V No load ADC off WDT enale fSYS=0MHz on — .5 5.0 A

ISLEEPSLEEP Mode Standy Cuent (LIRC on) 5V No load ADC off

WDT enale LVR disale — 8 0 μA

VILInput Low Voltage fo I/O Pots o Input Pins

5V — 0 — 1.5 V

— — 0 — 0.VDD V

VIHInput High Voltage fo I/O Pots o Input Pins

5V — 3.5 — 5.0 V

— — 0.8VDD — VDD V

IOL1

I/O Pot Sink Cuent (exept fo BZ BAT_IN LED_OUT PA7)

5V VOL=0.1VDD 1 3 — A

IOH1

I/O Pot Soue Cuent (exept fo BZ BAT_IN LED_OUT PA7)

5V VOH=0.9VDD 1 — A

IOL I/O Pot Sink Cuent (PA7) 5V VOL=0.1VDD 0 80 — A

IOH I/O Pot Soue Cuent (PA7) 5V VOH=0.9VDD 0 80 — A

RPH Pull-high Resistane fo I/O Pots 5V — 10 30 50 kΩ

High Voltage I/O Ports

IOL3 I/O Pot Sink Cuent (BZ) .5V VOL=0.1HV_OUT 115 10 — A

IOH3 I/O Pot Soue Cuent (BZ) .5V VOH=0.9HV_OUT -5% 10 — A

IOH I/O Pot Soue Cuent (BAT_IN) .5V VOH=HV_OUT-0.5 35 — — A

IOH5I/O Pot Soue Cuent (LED_OUT) .5V VOH=HV_OUT-0.5 100 — — A

Rev. 1.10 1 Deee 1 01 Rev. 1.10 13 Deee 1 01



A.C. CharacteristicsTa = 5°C



fCPU Opeating Clok 5V±3% —

DC — 1 MHz

DC — 1 MHz

DC — 0 MHz

fSYS Syste Clok (HIRC) 5V±3% —

— — 1 MHz

— — 1 MHz

— — 0 MHz

fHIRC HIRC Fequeny (note) 5V±3%Ta=5°C -% 1/1/0 +% MHz

Ta=-0°C~85°C -5% 1/1/0 +5% MHz

fLIRC LIRC Fequeny 5V±3%

Ta=5°C -10% 3 +10% kHz

Ta=-0°C ~ 85°C -30% 3 +0% kHz

tTIMERTCKn Input Pin Miniu Pulse Width — — — 30 — ns

tINT Inteupt Miniu Pulse Width — — 1 3.3 5 μs

tEERD EEPROM Read Tie — — — tSYS

tEEWR EEPROM Wite Tie — — — s

tSST

Syste Stat-up Tie Peiod (Wake-up fo HALT fSYS off at HALT state)

—fSYS=HIRC 1 — — tHIRC

fSYS=LIRC — — tSYS

Syste Stat-up Tie Peiod (Wake-up fo HALT fSYS on at HALT state)

— fSYS=HIRC — — tHIRC

tRSTD

Syste Reset Delay Tie (Powe on Reset LVR H/W Reset LVR S/W Reset WDT S/W Reset)

— — 5 50 100 s

Syste Reset Delay Tie (WDT Noal Reset) — — 8.3 1.7 33.3 s

Note:1.tSYS=1/fSYS,tHIRC=1/fHIRC2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshould

beconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

Rev. 1.10 1 Deee 1 01 Rev. 1.10 15 Deee 1 01



LVD&LVR Electrical CharacteristicsTa = 5°C



VLVR1

Low Voltage Reset Voltage —

LVR enale .1V

-5%

.1

+5%

V

VLVR LVR enale .55V .55 V

VLVR3 LVR enale 3.15V 3.15 V

VLVR LVR enale 3.8V 3.8 V

VLVD1

Low Voltage Deteto Voltage

— LVDEN= 1 VLVD = .0V

-5%

.0

+5%

V

VLVD — LVDEN= 1 VLVD = .V . V

VLVD3 — LVDEN= 1 VLVD = .V . V

VLVD — LVDEN= 1 VLVD = .7V .7 V

VLVD5 — LVDEN= 1 VLVD = 3.0V 3.0 V

VLVD — LVDEN= 1 VLVD = 3.3V 3.3 V

VLVD7 — LVDEN= 1 VLVD = 3.V 3. V

VLVD8 — LVDEN= 1 VLVD = .0V .0 V

ILVRAdditional Powe Consuption if LVR is used 5V±3% LVR disable → LVR enale — 0 90 μA

ILVDAdditional Powe Consuption if LVD is used 5V±3%

LVD disable → LVD enable (LVR disale) — 75 115 μA

LVD disable → LVD enable (LVR enale) — 0 90 μA

tLVR Low Voltage Width to Reset — — 10 0 80 μs

tLVD Low Voltage Width to Inteupt — — 0 10 0 μs

tLVDS LVDO Stale Tie— Fo LVR enale LVD off → on — — 5 μs

— Fo LVR disale LVD off → on — — 15 μs

tSRESET Softwae Reset Width to Reset — — 5 90 10 μs

Note:VLVRandVLVDaretheLVRandLVDvoltagewhentheVDDvoltagedrops.

Rev. 1.10 1 Deee 1 01 Rev. 1.10 15 Deee 1 01



ADC Electrical CharacteristicsTa = 5°C



AVDD A/D Convete Opeation Voltage — — .7 5 5.5 V

VREF A/D Convete Refeene Voltage — — .0 — AVDD V

VAD A/D Convete Input Voltage — — 0 — AVDD /VREF

V

IADCAdditional Powe Consuption if A/D Convete is used 5V No Load (tADCK = 0.5μs) — 1.5 3.0 A

DNL Diffeential Non-lineaity 5V

VREF=AVDD=VDDtADCK = 0.5μs -3 — +5 LSB

VREF=AVDD=VDDtADCK = 10μs -3 — +5 LSB

INL Integal Non-lineaity 5V

VREF=AVDD=VDDtADCK = 0.5μs -5 — + LSB

VREF=AVDD=VDDtADCK = 10μs -5 — + LSB

tADCK A/D Convete Clok Peiod — — 0.5 — 10 μs

tADCA/D Convesion Tie (Inlude Saple and Hold Tie) — 1-it ADC 1 — 0 tADCK

tADS A/D Convete Sapling Tie — 1-it ADC — — tADCK

tONST A/D Convete On-to-Stat Tie — — — — μs

LDO Regulator Electrical CharacteristicsVIN=VOUT+.0V IO=1A Ta=5°C unless othewise specified



VIN Input Voltage — — 7 — 1 VVOUT Output Voltage — — -3% 5 3% V

ΔVOUT Output Voltage Toleane 7V~1VIO=50A Ta=5°C -3.0 — 3.0 %IO=50A Ta=-0°C~85°C (exept 5°C) -5.0 — 5.0 %

ΔVLOAD Load Regulation 7V~1V 1mA≤IO≤50A — 0.18 0.3 %A

VDROP Dop Out Voltage 7V~1V IO=1A ΔVO=% — — 100 V

ISS Quiensent Cuent 7V~1V IO=0A — 5 5 μA

ΔVLINE Line Regulation 7V~1V 1.0V+VOUT≤VIN≤1VIO=1A — 0. — %/V

ΔVOUT/ΔTa Temperature Coefficient 7V~1V IO=50A — 0.5 — V/°C

Note:1.TheLDOcanprovidea50mAloadandacurrentlimitfunction.2.TheLDOisalwaysenabledwithoutacontrolsignal,itrequiresanexternal0.1mFandmorethan10mFcapacitorsforVINandVouttoVSSpin.

Rev. 1.10 1 Deee 1 01 Rev. 1.10 17 Deee 1 01



Over Current Pretection Electrical CharacteristicsTa = 5°C



IOP Opeation Cuent 5V ENOCP[1:0]=01 DAC VREF=.5V — 730 150 μA

OCP Comparator

ICOMP Copaato Opeating Cuent 5V No load — 30 0 μA

VCMPOS Copaato Input Offset Voltage5V — -15 — 15 V

5V By aliation - — V

VHYS Copaato Hysteesis Width 5V — 0 0 0 V

VCMCopaato Coon Mode Voltage Range 5V — VSS — VDD-

1. V

OCP OPA

IOPA OPA Opeating Cuent 5V No load — 00 350 μA

VOPAOS OPA Input Offset Voltage 5V— -15 — 15 V

With aliation - — V

VCMOPA Coon Mode Voltage Range 5V — VSS — VDD-

1. V

GAIN OPA Gain Eo 5V All onditions -5 G 5 %

DAC for OCP

IDAC DAC Opeating Cuent5V VREF=.5V — 50 300 μA

5V VREF=5V — 500 00 μA

RO RR Output Resisto 5V — — 10 — kΩ

DNL DAC Diffeential NonLineaity — — -0.5 — 0.5 LSB

INL DAC Integal NonLineaity — — -1 — 1 LSB

Power-on Reset Electrical CharacteristicsTa = 5°C



VPOR VDD Stat Voltage to Ensue Powe-on Reset — — — — 100 V

RRVDD VDD Rising Rate to Ensue Powe-on Reset — — 0.035 — — V/s

tPORMiniu Tie fo VDD Stays at VPOR to Ensue Powe-on Reset — — 1 — — s

Rev. 1.10 1 Deee 1 01 Rev. 1.10 17 Deee 1 01



System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicetakesadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increasedspeedofoperationandPeriodicperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcall instructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.The internaldatapath issimplifiedbymovingdata throughtheAccumulatorandtheALU.Certain internalregistersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheranHIRCorLIRCoscillator issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

System Clock and Pipelining

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

Rev. 1.10 18 Deee 1 01 Rev. 1.10 19 Deee 1 01



Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas“JMP”or“CALL” thatdemanda jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program CounterProgram Counter High byte PCL Register

PC10~PC8 PCL7~PCL0

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

Rev. 1.10 18 Deee 1 01 Rev. 1.10 19 Deee 1 01



StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrement:INCA,INC,DECA,DEC

• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

Rev. 1.10 0 Deee 1 01 Rev. 1.10 1 Deee 1 01



Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdevicetheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberof times,allowing theuser theconvenienceofcodemodificationon thesamedevice.Byusing theappropriateprogramming tools, thisFlashdeviceoffersusers the flexibility toconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof2K×16bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

Program Memory Structure

Rev. 1.10 0 Deee 1 01 Rev. 1.10 1 Deee 1 01



Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe“TABRD[m]”or“TABRDL[m]”instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas“0”.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

InstructionTable Location Bits

b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0TABRD [] @10 @9 @8 @7 @ @5 @ @3 @ @1 @0TABRDL [] 1 1 1 @7 @ @5 @ @3 @ @1 @0

Table LocationNote:b10~b0:Tablelocationbits

@7~@0:Tablepointer(TBLP)bits

@10~@8:Tablepointer(TBHP)bits

Rev. 1.10 Deee 1 01 Rev. 1.10 3 Deee 1 01



Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“700H”whichreferstothestartaddressofthelastpagewithinthe2KwordsProgramMemoryofthedevice.Thetablepointerissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“706H”or6locationsafterthestartofthelastpage.NotethatthevalueforthetablepointerisreferencedtothefirstaddressspecifiedbytheTBHPandTBLPregistersifthe“TABRD[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRD[m]”instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2 : :mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a ; to the last page or specific pagemov a,07h ; initialise high table pointermov tbhp,a : :tabrd tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address “706H” transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address “705H” transferred to tempreg2 and TBLH ; in this example the data “1AH” is transferred to tempreg1 and data “0FH” to ; register tempreg2, the value 00H will be transferred to the high byte register TBLH : :org 700h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :

Rev. 1.10 Deee 1 01 Rev. 1.10 3 Deee 1 01



In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:

Holtek Write Pins MCU Programming Pins FunctionICPDA PA0 Pogaing Seial Data/AddessICPCK PA Pogaing Seial ClokVDD VDD Powe SupplyVSS VSS Gound

Duringtheprogrammingprocess,theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwopins.

TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefor theclock.Twoadditional linesarerequiredfor thepowersupply.The technicaldetailsregardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitanceof*mustbelessthan1nF.

Rev. 1.10 Deee 1 01 Rev. 1.10 5 Deee 1 01



On-Chip Debug Support – OCDSAnEVchipexists for thepurposesofdeviceemulation.ThisEVchipdevicealsoprovidesan“On-ChipDebug”function todebug thedeviceduring thedevelopmentprocess.TheEVchipandtheactualMCUdevicesarealmostfunctionallycompatibleexceptforthe“On-ChipDebug”function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinistheOCDSData/Address input/outputpinwhile theOCDSCKpin is theOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpinsintheactualMCUdevicewillhavenoeffectintheEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpins for ICP.ForamoredetailedOCDSdescription, refer to thecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSDA OCDSDA On-hip Deug Suppot Data/Addess input/outputOCDSCK OCDSCK On-hip Deug Suppot Clok input

VDD VDD Powe SupplyGND VSS Gound

Rev. 1.10 Deee 1 01 Rev. 1.10 5 Deee 1 01



RAM Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.

StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

TheoverallDataMemoryissubdividedintotwobanks.TheSpecialPurposeDataMemoryregistersareaccessibleinallbanks,withtheexceptionof theEECregisterataddress40H,whichisonlyaccessibleinBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforthedeviceistheaddress00H.

00H

7FH80H

FFH

Speial Pupose Data Meoy

Geneal Pupose Data Meoy

EEC at 0H in Bank 1

Bank 0

Data Memory Structure

Capacity Banks18×8 Bank 0: 80H~FFH

General Purpose Data Memory Structure

Rev. 1.10 Deee 1 01 Rev. 1.10 7 Deee 1 01



00H IAR001H MP00H IAR103H MP10H05H ACC0H PCL07H TBLP08H TBLH09H TBHP0AH STATUS0BH SMOD0CH LVDC0DH INTEG0EH0FH10H

INTC0

11H

INTC1

1H

19H

PAPU

18HPAWU

1BH1AH

1DH1CH

1FH

PAPAC

13H1H

MFI0

15H

MFI1

1H17H

: Unused ead as 00H

INTC

MFIPBC

WDTCTBC

PBPU

PB

CTRL

SADOLSADOHSADC0SADC1

TM0DLTM0DHTM0ALTM0AH

CPR

TM1C1

0H1HH

9H8H

BHAH

DHCH

FHEH

3HH5HH7H

30H31H3H

3DH3CH

3FH3EH

33H3H35H3H37H

TM1DLTM1DHTM1ALTM1AH

OCPC00H1HH3HH5HH7H8H9HAH

7FH

BP

Unused

LVRC

TM1C0

TM1RPLTM1RPH

OCPDAOCPOCALOCPCCAL

TMDH

Unused::

MFI3

1EH EEAEED

Bank 0 1 Bank 0 Bank 1

EEC

OCPC1

TMC0TMC1TMDL

Unused

TM0RPLTM0RPHCTRLCTRL3CTRLCTRL5

38H39H3AH3BH

TMRPH

TMALTMAH

TMRPLBHCHDH

TM0C0TM0C1

EH

Unused

Unused

Special Purpose Data Memory Structure

Rev. 1.10 Deee 1 01 Rev. 1.10 7 Deee 1 01



Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection.However,severalregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 codeorg00hstart: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM addressloop: clr IAR0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

Rev. 1.10 8 Deee 1 01 Rev. 1.10 9 Deee 1 01



Bank Pointer – BPFor thisdevice, theDataMemory isdivided into twobanks,Bank0andBank1.Selecting therequiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0~1.

TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetinthePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.DirectlyaddressingtheDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafromBank1mustbeimplementedusingIndirectAddressing.

BP Register Bit 7 6 5 4 3 2 1 0

Nae — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas“0”Bit0 DMBP0:SelectDataMemoryBanks

0:Bank01:Bank1

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Rev. 1.10 8 Deee 1 01 Rev. 1.10 9 Deee 1 01



Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

Rev. 1.10 30 Deee 1 01 Rev. 1.10 31 Deee 1 01



STATUS RegisterBit 7 6 5 4 3 2 1 0

Nae — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 × × × ×

“×” unknownBit7~6 Unimplemented,readas“0”Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction

Bit3 OV:Overflowflag0:nooverflow1:anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:noauxiliarycarry1:anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:nocarry-out1:anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

Rev. 1.10 30 Deee 1 01 Rev. 1.10 31 Deee 1 01



EEPROM Data MemoryOneofthespecialfeaturesinthedeviceisitsinternalEEPROMDataMemory.EEPROM,whichstandsforElectricallyErasableProgrammableReadOnlyMemory,isbyitsnatureanon-volatileformofmemory,withdataretentionevenwhenitspowersupply is removed.Byincorporatingthiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproduct identificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithintheproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityisupto64×8bits.UnliketheProgramMemoryandRAMDataMemory, theEEPROMDataMemoryisnotdirectlymappedandis thereforenotdirectlyaccessible in the samewayas theother typesofmemory.ReadandWriteoperations to theEEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinBank0andasinglecontrolregisterinBank1.

EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewayasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbedirectlyaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

EEPROM Control Registers List

NameBit

7 6 5 4 3 2 1 0EEA — — D5 D D3 D D1 D0EED D7 D D5 D D3 D D1 D0EEC — — — — WREN WR RDEN RD

EEA RegisterBit 7 6 5 4 3 2 1 0

Nae — — D5 D D3 D D1 D0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5~0 DataEEPROMaddress

DataEEPROMaddressbit5~bit0

Rev. 1.10 3 Deee 1 01 Rev. 1.10 33 Deee 1 01



EED RegisterBit 7 6 5 4 3 2 1 0

Nae D7 D D5 D D3 D D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 EEPROMdataEEPROMdatabit7~bit0

EEC RegisterBit 7 6 5 4 3 2 1 0

Nae — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDcannotbesetto“1”atthesametime.

Rev. 1.10 3 Deee 1 01 Rev. 1.10 33 Deee 1 01



Reading Data from the EEPROM ToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTowritedatatotheEEPROM,theEEPROMaddressofthedatatobewrittenmustfirstbeplacedin theEEAregisterandthedataplacedin theEEDregister.Thenthewriteenablebit,WREN,in theEECregistermustfirstbesethightoenablethewritefunction.After this, theWRbit intheEECregistermustbe immediatelysethigh to initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbeforeimplementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.SettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycle iscontrolledusingan internal timerwhoseoperation isasynchronous tomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallyclearedtozerobythemicrocontroller, informingtheuserthatthedatahasbeenwrittentotheEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbitintherelevantinterruptregister.HoweverastheEEPROMiscontainedwithinaMulti-functionInterrupt,theassociatedmulti-functioninterruptenablebitmustalsobeset.WhenanEEPROMwritecycleends, theDEFrequest flagand itsassociatedmulti-functioninterruptrequestflagwillbothbeset.Iftheglobal,EEPROMandMulti-function interruptsareenabledandthestackisnotfull,a jumpto theassociatedMulti-functionInterruptvectorwilltakeplace.WhentheinterruptisservicedonlytheMulti-functioninterruptflagwillbeautomaticallyreset, theEEPROMinterruptflagmustbemanuallyresetbytheapplicationprogram.MoredetailscanbeobtainedintheInterruptsection.

Rev. 1.10 3 Deee 1 01 Rev. 1.10 35 Deee 1 01



Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbePeriodicbyensuringthattheWriteEnablebit isnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrolregisterexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.TheglobalinterruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.NotethatthedeviceshouldnotentertheIDLEorSLEEPmodeuntiltheEEPROMreadorwriteoperationistotallycompleted,otherwise,theEEPROMreadorwriteoperationwillfail.

Programming Examples• Reading data from the EEPROM – polling method

MOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, ASET IAR1.1 ; set RDEN bit, enable read operationsSET IAR1.0 ; start Read Cycle - set RD bitBACK:SZ IAR1.0 ; check for read cycle endJMP BACKCLR IAR1 ; disable EEPROM read/writeCLR BPMOV A, EED ; move read data to registerMOV READ_DATA, A

• Writing Data to the EEPROM – polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, EEPROM_DATA ; user defined dataMOV EED, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, A ; BP points to data memory bank 1CLR EMISET IAR1.3 ; set WREN bit, enable write operationsSET IAR1.2 ; start Write Cycle - set WR bit – executed immediately ; after set WREN bitSET EMIBACK:SZ IAR1.2 ; check for write cycle endJMP BACKCLR IAR1 ; disable EEPROM read/writeCLR BP

Rev. 1.10 3 Deee 1 01 Rev. 1.10 35 Deee 1 01



OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupts.Fullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock,thedevicehastheflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq.Intenal High Speed RC HIRC 1/1/0MHzIntenal Low Speed RC LIRC 3kHz

Oscillator Types

System Clock ConfigurationsThereare twomethodsofgeneratingthesystemclock,ahighspeedoscillatoranda lowspeedoscillator.Thehighspeedoscillatoris theinternal12MHz,16MHzor20MHzRCoscillator.Thelowspeedoscillatoris theinternal32kHzRCoscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

ThefrequencyoftheslowspeedorhighspeedsystemclockisalsodeterminedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.Notethattwooscillatorselectionsmustbemadenamelyonehighspeedandone lowspeedsystemoscillators. It isnotpossible tochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.

High Speed Osillato

HIRC

LIRC

Low Speed Osillato

fH - stage Pesale

HLCLK CKS~CKS0 its

fH/

fH/

fH/8

fH/1

fH/3

fH/

fSUB

fSYS

System Clock Configurations

Rev. 1.10 3 Deee 1 01 Rev. 1.10 37 Deee 1 01



Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasthreefixedfrequenciesofeither12MHz,16MHzor20MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Notethatifthisinternalsystemclockoptionisselected,asitrequiresnoexternalpinsforitsoperation.

Internal 32kHz Oscillator – LIRCThe Internal32kHzSystemOscillator is the lowfrequencyoscillator. It isa fully integratedRCoscillatorwitha typicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.

Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovided thisdevicewithbothhighand lowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,orlowfrequency,fSUB,source,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromtheHIRCoscillator.ThelowspeedsystemclocksourcecanbesourcedfromtheLIRCoscillator.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

Rev. 1.10 3 Deee 1 01 Rev. 1.10 37 Deee 1 01



System Clock ConfigurationsNote:WhenthesystemclocksourcefSYSisswitchedtofLfromfH,thehighspeedoscillationwillstoptoconserve

thepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

System Operation ModesThere are fivedifferentmodesofoperation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingthreemodes, theSLEEP,IDLE0andIDLE1ModeareusedwhenthemicrocontrollerCPUisswitchedofftoconservepower.

OperatingMode

DescriptionCPU fSYS fSUB fTBC

NORMAL ode On fH~fH/ On OnSLOW ode On fSUB On OnILDE0 ode Off Off On OnIDLE1 ode Off On On OnSLEEP ode Off Off On Off

Rev. 1.10 38 Deee 1 01 Rev. 1.10 39 Deee 1 01



NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbythehighspeedoscillator.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromthehighspeedoscillator,HIRC.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromfSUB.Runningthemicrocontroller inthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEPmodetheCPUwillbestopped.HoweverthefSUBclockwillcontinuetooperate.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPU,thesystemoscillatorwillbestopped,thelowfrequencyclockfSUBwillbeon.

IDLE1 ModeTheIDLE1ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPU,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModethelowfrequencyclockfSUBwillbeon.

Note:IfLVDEN=1andtheSLEEPorIDLEmodeisentered,theLVDandbandgapfunctionswillnotbedisabled,andthefSUBclockwillbeforcedtobeenabled.

Rev. 1.10 38 Deee 1 01 Rev. 1.10 39 Deee 1 01



Control RegisterTheSMODregisterisusedtocontroltheinternalclockswithinthedevice.

SMOD RegisterBit 7 6 5 4 3 2 1 0

Nae CKS CKS1 CKS0 — LTO HTO IDLEN HLCLKR/W R/W R/W R/W — R R R/W R/WPOR 1 1 0 — 0 0 1 0

Bit7~5 CKS2 ~ CKS0:ThesystemclockselectionwhenHLCLKis“0”000:fSUB001:fSUB010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbeLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4 Unimplemented,readas“0”Bit3 LTO:LIRCSystemOSCSSTreadyflag

0:Notready1:Ready

ThisisthelowspeedsystemoscillatorSSTreadyflagwhichindicateswhenthelowspeedsystemoscillatorisstableafterpoweronresetorawake-uphasoccurred.Theflagwillchangetoahighlevelafter1~2cycles.

Bit2 HTO:HIRCSystemOSCSSTreadyflag0:Notready1:Ready

ThisisthehighspeedsystemoscillatorSSTreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstableafterawake-uphasoccurred.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterpoweronresetorawake-uphasoccurred,theflagwillchangetoahighlevelafter15~16clockcyclesiftheHIRCoscillatorisused.

Bit1 IDLEN:IDLEModeControl0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

Bit0 HLCLK:SystemClockSelection0:fH/2~fH/64orfSUB1:fH

ThisbitisusedtoselectifthefHclockorthefH/2~fH/64orfSUBclockisusedasthesystemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~fH/64orfSUBclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

Rev. 1.10 0 Deee 1 01 Rev. 1.10 1 Deee 1 01



CTRL RegisterBit 7 6 5 4 3 2 1 0

Nae FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — x 0 0

"x" unknownBit7 FSYSON:fSYSControlinIDLEMode

0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

DescribeelsewhereBit1 LRF:LVRCControlregistersoftwareresetflag

DescribeelsewhereBit0 WRF:WDTControlregistersoftwareresetflag

Describeelsewhere

Rev. 1.10 0 Deee 1 01 Rev. 1.10 1 Deee 1 01



Operating Mode Switching Thedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionof theIDLENbit in theSMODregisterandFSYSONintheCTRLregister.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfSUB.IftheclockisfromthefSUB,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMs.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.

NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower, thesystemclockcanswitch to run in theSLOWModebysetting theHLCLKbitto“0”andsettingtheCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequiresthisoscillator tobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

Rev. 1.10 Deee 1 01 Rev. 1.10 3 Deee 1 01



SLOW Mode to NORMAL Mode Switching InSLOWModethesystemusesLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,where thehighspeedsystemoscillator isused, theHLCLKbit shouldbeset to“1”orHLCLKbit is“0”,butCKS2~CKS0isset to“010”,“011”,“100”,“101”,“110”or“111”.Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.

Entering the SLEEP ModeThereisonlyonewayforthedevicetoentertheSLEEPModeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecounting

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Rev. 1.10 Deee 1 01 Rev. 1.10 3 Deee 1 01



Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruc-tion,buttheTimeBaseclockfTBCandthelowfrequencyfSUBclockwillbeon.


• TheWDTwillbeclearedandresumecounting.



Entering the IDLE1 ModeThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockandfTBCandthelowfrequencyfSUBwillbeonandtheap-plicationprogramwillstopatthe“HALT”instruction.


• TheWDTwillbeclearedandresumecounting.



Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobe takenwith the loads,whichareconnected to I/Opins,whichare setupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.IntheIDLE1Modethesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator, theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Rev. 1.10 Deee 1 01 Rev. 1.10 5 Deee 1 01



Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

IfthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Theactualsourceof thewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

Rev. 1.10 Deee 1 01 Rev. 1.10 5 Deee 1 01



Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalfSUBclockwhichisinturnsuppliedbytheLIRCoscillator.TheWatchdogTimersourceclockis thensubdividedbyaratioof28 to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.

Watchdog Timer Control RegisterAsingleregister,WDTC,controlstherequiredtimeoutperiodaswellastheenableoperation.TheWDTCregister is initiatedto01010011Batanyresetbutkeepsunchangedat theWDTtime-outoccurrenceinapowerdownstate.

WDTC Register Bit 7 6 5 4 3 2 1 0

Nae WE WE3 WE WE1 WE0 WS WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4 ~ WE0:WDTenablebit10101or01010:EnabledOthers:ResetMCU

Ifthesebitsarechangedduetoadverseenvironmentalconditions,themicrocontrollerwillbereset.Theresetoperationwillbeactivatedafter2~3LIRCclockcyclesandtheWRFbitintheCTRLregisterwillbesethigh.

Bit2~0 WS2 ~ WS0:SelectWDTTimeoutPeriod000:28/fSUB001:210/fSUB010:212/fSUB011:214/fSUB100:215/fSUB101:216/fSUB110:217/fSUB111:218/fSUB

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

Rev. 1.10 Deee 1 01 Rev. 1.10 7 Deee 1 01



CTRL RegisterBit 7 6 5 4 3 2 1 0

Nae FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — x 0 0

"x" unknownBit7 FSYSON:fSYSControlIDLEMode

DescribeelsewhereBit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

DescribeelsewhereBit1 LRF:LVRControlregistersoftwareresetflag

DescribeelsewhereBit0 WRF:WDTControlregistersoftwareresetflag

0:Notoccur1:Occurred

ThisbitissethighbytheWDTControlregistersoftwareresetandclearedbytheapplicationprogram.Notethatthisbitcanonlybeclearedtozerobytheapplicationprogram.

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.Therearefivebits,WE4~WE0,intheWDTCregistertoofferenableandresetcontroloftheWatchdogTimer.WhentheWE4~WE0bitsvalueareequal to01010Bor10101B, theWDTfunction isenabled.However,iftheWE4~WE0bitsarechangedtoanyothervaluesexcept01010Band10101B,whichcouldbecausedbyadverseenvironmentalconditionssuchasnoise,itwillresetthemicrocontrollerafter2~3LIRCclockcycles.

WE4 ~ WE0 Bits WDT Function

01010B o 10101B Enale

Any othe value Reset MCU

Watchdog Timer Enable Control

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueiswrittenintotheWE4~WE0bitfiledexcept01010Band10101B,thesecondisusingtheWatchdogTimersoftwareclear instructionsandthethirdisviaaHALTinstruction.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDT.

Themaximumtime-outperiodiswhenthe218divisionratioisselected.Asanexample,witha32kHzLIRCoscillatoras itssourceclock, thiswillgiveamaximumwatchdogperiodofaround8secondsforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

Rev. 1.10 Deee 1 01 Rev. 1.10 7 Deee 1 01



“CLR WDT”Instution

8-stage Divide WDT Pesale

WE~WE0 itsWDTC Registe Reset MCU

fSUB/8

8-to-1 MUX

CLR

WS~WS0

WDT Tie-out(8/fSUB ~ 18/fSUB)

LIRC

“HALT”Instution

fSUB

Watchdog Timer

Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsTherearefourwaysinwhichamicrocontrollerresetcanoccur,througheventsoccurringinternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

VDDPowe-on

ResetSST Tie-out

tRSTD

Note:tRSTDispower-ondelay,typicaltime=50msPower-On Reset Timing Chart

Rev. 1.10 8 Deee 1 01 Rev. 1.10 9 Deee 1 01



Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltage,VLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheCTRLregisterwillalsobesethigh.ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexist forgreater than thevalue tLVRspecified in theLVD&LVRcharacteristics. If the lowvoltagestatedoesnotexceedthisvalue,theLVRwill ignorethelowsupplyvoltageandwillnotperformaresetfunction.

TheactualVLVRisdefinedbytheLVS7~LVS0bits intheLVRCregister.If theLVS7~LVS0bitsarechangedtoanyothervalueexceptsomecertainvaluesdefinedin theLVRCregisterby theenvironmentalnoise,theLVRwillresetthedeviceafter2~3LIRCclockcycles.Whenthishappens,theLRFbitintheCTRLregisterwillbesethigh.Afterpowerontheregisterwillhavethevalueof01010101B.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceentersthepowerdownmode.

Note:tRSTDispower-ondelay,typicaltime=50msLow Voltage Reset Timing Chart

• LVRC Register

Bit 7 6 5 4 3 2 1 0Nae LVS7 LVS LVS5 LVS LVS3 LVS LVS1 LVS0R/W R/W R/W R/W R/W R R R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 LVS7 ~ LVS0:LVRVoltageSelectcontrol01010101:2.1V00110011:2.55V10011001:3.15V10101010:3.8VAnyothervalue:GeneratesMCUreset–registerisresettoPORvalue

Whenanactuallowvoltageconditionoccurs,anMCUresetwillbegenerated.Theresetoperationwillbeactivatedafter2~3LIRCclockcycles.In thissituationthisregistercontentswillremainthesameaftersucharesetoccurs.Any registervalue,other than thedefinedvalues above,will also result in thegenerationofanMCUreset.Theresetoperationwillbeactivatedafter2~3LIRCclockcycles.HoweverinthissituationthisregistercontentswillberesettothePORvalue.

Rev. 1.10 8 Deee 1 01 Rev. 1.10 9 Deee 1 01



• CTRL Register

Bit 7 6 5 4 3 2 1 0Nae FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — x 0 0

"x" unknownBit7 FSYSON:fSYSControlIDLEMode

DescribeelsewhereBit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

0:Notoccur1:Occurred

ThisbitissethighwhenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedtozerobytheapplicationprogram.

Bit1 LRF:LVRControlregistersoftwareresetflag0:Notoccur1:Occurred

ThisbitissethighiftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedtozerobytheapplicationprogram.

Bit0 WRF:WDTControlregistersoftwareresetflagDescribeelsewhere

Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperationisthesameasaLVRresetexceptthattheWatchdogtime-outflagTOwillbesethigh.

Note:tRSTDispower-ondelay,typicaltime=16.7msWDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedtozeroandtheTOflagwillbesethigh.RefertotheA.C.CharacteristicsfortSSTdetails.

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Rev. 1.10 50 Deee 1 01 Rev. 1.10 51 Deee 1 01



Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Powe-on esetu u LVR eset duing NORMAL o SLOW Mode opeation1 u WDT tie-out eset duing NORMAL o SLOW Mode opeation1 1 WDT tie-out eset duing IDLE o SLEEP Mode opeation

Note:“u”standsforunchanged

Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETPoga Counte Reset to zeoInteupts All inteupts will e disaledWDT Clea afte eset WDT egins ountingTie Modules Tie Modules will e tuned offInput/Output Pots I/O pots will e setup as inputs Stak Pointe Stak Pointe will point to the top of the stak

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontroller is inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.

Register Reset(Power On)

WDT Time-out(Normal Operation)

WDT Time-out(SLEEP/IDLE)

Poga Counte 0 0 0 H 0 0 0 H 0 0 0 H

MP0 x x x x x x x x x x x x x x x x u u u u u u u u

MP1 x x x x x x x x x x x x x x x x u u u u u u u u

BP - - - - - - - 0 - - - - - - - 0 - - - - - - - u

ACC x x x x x x x x u u u u u u u u u u u u u u u u

PCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBLP x x x x x x x x u u u u u u u u u u u u u u u u

TBLH x x x x x x x x u u u u u u u u u u u u u u u u

TBHP - - - - - x x x - - - - - u u u - - - - - u u u

STATUS - - 0 0 x x x x - - 1 u u u u u - - 1 1 u u u u

SMOD 11 0 - 0 0 1 0 11 0 - 0 0 1 0 u u u - u u u u

LVDC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u u

INTEG - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

INTC0 - 0 0 - 0 0 - 0 - 0 0 - 0 0 - 0 - u u - u u - u

INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

INTC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

MFI0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

MFI1 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

MFI - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

Rev. 1.10 50 Deee 1 01 Rev. 1.10 51 Deee 1 01






MFI3 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

PA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PB - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u u

PBC - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u u

PBPU - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u u

TBC 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 u u u u - u u u

EEA - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u

EED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

EEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

SADOL (ADRFS=0) x x x x - - - - x x x x - - - - u u u u - - - -

SADOH (ADRFS=0) x x x x x x x x x x x x x x x x u u u u u u u u

SADOL (ADRFS=1) x x x x x x x x x x x x x x x x u u u u u u u u

SADOH (ADRFS=1) - - - - x x x x - - - - x x x x - - - - u u u u

SADC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

SADC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

CTRL 0 - - - - x 0 0 0 - - - - 0 0 0 u - - - - u u u

LVRC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 u u u u u u u u

TM0C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -

TM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM0DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM0AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM0RPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM0RPH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM1C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -

TM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM1AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TM1RPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TM1RPH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

CPR 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 u u u u u u u

OCPC0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 u u u u - - - u

OCPC1 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u

OCPDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

OCPOCAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

Rev. 1.10 5 Deee 1 01 Rev. 1.10 53 Deee 1 01






OCPCCAL 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 u u u u u u u u

CTRL 0 - 0 0 0 0 0 1 0 - 0 0 0 0 0 1 u - u u u u u u

CTRL3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

CTRL - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u

CTRL5 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u u

TMC0 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -

TMC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TMDH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TMAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TMAH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TMRPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TMRPH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

Note:"-"notimplement"u"standsfor"unchanged"

"x"standsfor"unknown"

Rev. 1.10 5 Deee 1 01 Rev. 1.10 53 Deee 1 01



Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectional input/output lines labeledwithportnamesPA~PB.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

RegisterName

Bit7 6 5 4 3 2 1 0

PA PA7 PA PA5 PA PA3 PA PA1 PA0PAC PAC7 PAC PAC5 PAC PAC3 PAC PAC1 PAC0

PAPU PAPU7 PAPU PAPU5 PAPU PAPU3 PAPU PAPU1 PAPU0PAWU PAWU7 PAWU PAWU5 PAWU PAWU3 PAWU PAWU1 PAWU0

PB — — — — PB3 PB PB1 PB0PBC — — — — PBC3 PBC PBC1 PBC0

PBPU — — — — PBPU3 PBPU PBPU1 PBPU0

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternalresistor.Toeliminatetheneedfortheseexternalresistors,allI/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU~PBPU,andareimplementedusingweakPMOStransistors.

NotethatonlywhentheI/OportsareconfiguredasdigitalintputorNMOSoutput,theinternalpull-highfunctionscanbeenabledusingthePAPU~PBPUregisters.Inotherconditions,internalpull-highfunctionsaredisabled.

PAPU RegisterBit 7 6 5 4 3 2 1 0

Nae PAPU7 PAPU PAPU5 PAPU PAPU3 PAPU PAPU1 PAPU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 I/OPortAbit7~bit0Pull-HighControl0:Disable1:Enable

PBPU RegisterBit 7 6 5 4 3 2 1 0

Nae — — — — PBPU3 PBPU PBPU1 PBPU0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3~0 I/OPortBbit3~bit0Pull-HighControl

0:Disable1:Enable

Rev. 1.10 5 Deee 1 01 Rev. 1.10 55 Deee 1 01



Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

NotethatonlywhenthePortApinsareconfiguredasgeneralpurposeI/OsandthedeviceisintheHALTstatus, thePortAwake-upfunctionscanbeenabledusingtherelevantbits in thePAWUregister.Inotherconditions,thewake-upfunctionsaredisabled.

PAWU RegisterBit 7 6 5 4 3 2 1 0

Nae PAWU7 PAWU PAWU5 PAWU PAWU3 PAWU PAWU1 PAWU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 I/OPortAbit7~bit0WakeUpControl0:Disable1:Enable

I/O Port Control RegistersEach I/Oporthas itsowncontrol registerknownasPAC~PBC, to control the input/outputconfiguration.With this control register, eachCMOSoutput or input canbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

PAC RegisterBit 7 6 5 4 3 2 1 0

Nae PAC7 PAC PAC5 PAC PAC3 PAC PAC1 PAC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7~0 I/OPortAbit7~bit0Input/OutputControl0:Output1:Input

PBC RegisterBit 7 6 5 4 3 2 1 0

Nae — — — — PBC3 PBC PBC1 PBC0R/W — — — — R/W R/W R/W R/WPOR — — — — 1 1 1 1

Bit7~4 Unimplemented,readas“0”Bit3~0 I/OPortBbit3~bit0Input/OutputControl

0:Output1:Input

Rev. 1.10 5 Deee 1 01 Rev. 1.10 55 Deee 1 01



Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thedesiredfunctionofthemulti-functionI/Opinsisselectedbyaseriesofregistersviatheapplicationprogramcontrol.

Pin-shared Function Selection RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.Thedevice includes theCTRL3andCTRL4registerswhichcanselectthedesiredfunctionsofthemulti-functionpin-sharedpins.

Themostimportantpoint tonoteis tomakesurethat thedesiredpin-sharedfunctionisproperlyselectedandalsodeselected.Toselect thedesiredpin-sharedfunction, thepin-sharedfunctionshouldfirstbecorrectlyselectedusingthecorrespondingpin-sharedcontrolregister.Afterthatthecorrespondingperipheralfunctionalsettingshouldbeconfiguredandthentheperipheralfunctioncanbeenabled.Tocorrectlydeselectthepn-sharedfunction,theperipheralfunctionshouldfirstbedisabledandthenthecorrespondingpin-sharedfunctioncontrolregistercanbemodifiedtoselectotherpin-sharedfunctions.

Pin-shared Function Selection Registers List

NameBit

7 6 5 4 3 2 1 0CTRL3 IOCN7 IOCN IOCN5 IOCN IOCN3 IOCN IOCN1 IOCN0CTRL — — — IOCN1 IOCN11 IOCN10 IOCN9 IOCN8

CTRL3 RegisterBit 7 6 5 4 3 2 1 0

Nae IOCN7 IOCN IOCN5 IOCN IOCN3 IOCN IOCN1 IOCN0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 IOCN7~IOCN6:PA5pinfunctionselection00:INT1/TCK1/PA501:AN310:OCP111:INT1/TCK1/PA5

TheINT1orTCK1pinisfurtherlyselectedusingthecorrespondingfunctionselectionbitsintheinterruptcontrolregisterorTMcontrolregister.

Bit5~4 IOCN5~IOCN4:PA4pinfunctionselection00:PA401:AN210:TP111:PA4

Bit3~2 IOCN3~IOCN2:PA3pinfunctionselection00:INT0/TCK0/PA301:AN110:VREF11:INT0/TCK0/PA3

TheINT0orTCK0pinisfurtherlyselectedusingthecorrespondingfunctionselectionbitsintheinterruptcontrolregisterorTMcontrolregister.

Rev. 1.10 5 Deee 1 01 Rev. 1.10 57 Deee 1 01



Bit1~0 IOCN1~IOCN0:PA1pinfunctionselection00:PA101:AN010:TP011:PA1


Nae — — — IOCN1 IOCN11 IOCN10 IOCN9 IOCN8R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas“0”Bit4 IOCN12:PB0pinfunctionselection

0:PB01:PWM0H

Bit3~2 IOCN11~IOCN10:PA7pinfunctionselection00:TCK2/PA701:AN510:PWM0L11:TCK2/PA7

TheTCK2pinisfurtherlyselectedusingthecorrespondingfunctionselectionbitsintheTMcontrolregister.

Bit1~0 IOCN9~IOCN8:PA6pinfunctionselection00:PA601:AN410:OCP011:TP2

I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

Generic Input/Output Structure

Rev. 1.10 5 Deee 1 01 Rev. 1.10 57 Deee 1 01



A/D Input/Output Structure

Programming ConsiderationsWithintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregisters,PAC~PBC,arethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregisters,PA~PB,arefirstprogrammed.Selectingwhichpinsare inputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvaluesintotheappropriateportcontrolregisterorbyprogrammingindividualbits intheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

Read/Wite Timing

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Rev. 1.10 58 Deee 1 01 Rev. 1.10 59 Deee 1 01



Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevice includesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

IntroductionThedevicecontainsthree10-bitPeriodicTMs,eachTMhavingareferencenameofTM0,TM1andTM2.ThemainfeaturesoftheTMsaresummarisedintheaccompanyingtable.

Function PTMTie/Counte √I/P Captue √Copae Math Output √PWM Channels 1Single Pulse Output 1PWM Alignent EdgePWM Adjustent Peiod & Duty Duty o Peiod

TM Function Summary

TM0 TM1 TM210-it PTM 10-it PTM 10-it PTM

TM Name/Type Reference

TM OperationTheTMsoffer adiverse rangeof functions, fromsimple timingoperations toPWMsignalgeneration.ThekeytounderstandinghowtheTMoperates is toseeit intermsofafreerunningcounterwhosevalue is thencomparedwith thevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounterisdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrives themaincounter ineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingtheTnCK2~TnCK0bitsintheTMcontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH,thefTBCclocksourceortheexternalTCKnpin.TheTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsEachPeriodicTMshastwointernal interrupts, theinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerated,itcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

Rev. 1.10 58 Deee 1 01 Rev. 1.10 59 Deee 1 01



TM External PinsEachoftheTMs,irrespectiveofwhattype,hasoneTMinputpin,withthelabelTCKn.TheTMinputpin,isessentiallyaclocksourcefortheTMandisselectedusingtheTnCK2~TnCK0bitsintheTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingtheTnCK2~TnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.

TheTMseachhaveoneoutputpinwhichisselectedusingthecorrespondingpin-sharedfunctionselectionbitsdescribedinthePin-sharedFunctionsection.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunction,theTMoutputfunctionmustfirstbesetupusingrelevantpin-sharedfunctionselectionregister.

Type TM0 TM1 TM2 Pin Control RegistersInput TCK0 TCK1 TCK CTRL3 o CTRL

Output TP0 TP1 TP CTRL3 o CTRL

TM External Pins

TM Input/Output Pin ControlSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingtherelevantpin-sharedfunctionselectionregisters,withthecorrespondingselectionbits ineachpin-sharedfunctionregistercorrespondingtoaTMinput/outputpin.ConfiguringtheselectionbitscorrectlywillsetupthecorrespondingpinasaTMinput/output.Thedetailsofthepin-sharedfunctionselectionaredescribedinthepin-sharedfunctionsection.

TM0(PTM)

TP0

TCK0

TP Output

TCK Input

IOCN1~IOCN0

IOCN3~IOCN

0

1

T0CAPTS

Captue Input

TM0 Function Pin Control Block Diagram

TM1(PTM)

TP1

TCK1

TP Output

TCK Input

IOCN5~IOCN

IOCN7~IOCN

0

1

T1CAPTS

Captue Input


Rev. 1.10 0 Deee 1 01 Rev. 1.10 1 Deee 1 01



TM2(PTM)

TP

TCK

TP Output

TCK Input

IOCN9~IOCN8

IOCN11~IOCN10

0

1

TCAPTS

Captue Input


Programming ConsiderationsTheTMCounterRegisters,theCapture/CompareCCRAandtheCCRPregisters,being10-bit,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.AstheCCRAandCCRPregistersareimplementedinthewayshowninthefollowingdiagramandaccessingtheseregisterpairsiscarriedoutinaspecificwaydescribedabove,itisrecommendedtousethe“MOV”instructiontoaccesstheCCRAorCCRPlowbyteregisters,namedTMnALorTMnRPL,usingthefollowingaccessprocedures.AccessingtheCCRAorCCRPlowbyteregisterwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

Data Bus

8-it Buffe

TMnDHTMnDL

TMnRPHTMnRPL

TMnAHTMnAL

TM Counte Registe (Read only)

TM CCRA Registe (Read/Wite)

TM CCRP Registe (Read/Wite)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRAorCCRP♦ Step1.WritedatatoLowByteTMnALorTMnRPL

– notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteTMnAHorTMnRPH

– heredata iswrittendirectly to thehighbyteregistersandsimultaneouslydata is latchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRAorCCRP♦ Step1.ReaddatafromtheHighByteTMnDH,TMnAHorTMnRPH

– heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowByteTMnDL,TMnALorTMnRPL– thisstepreadsdatafromthe8-bitbuffer.

Rev. 1.10 0 Deee 1 01 Rev. 1.10 1 Deee 1 01



Periodic Type TM – PTMThePeriodicTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.ThePeriodicTMcanalsobecontrolledwithanexternalinputpinandcandriveoneexternaloutputpin.

Periodic TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearetwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwiththeCCRAandCCRPregisters.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theTnONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.ThePeriodicTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroltheoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Periodic Type TM Block Diagram (n=0~2)

Rev. 1.10 Deee 1 01 Rev. 1.10 3 Deee 1 01



Periodic Type TM Register DescriptionOveralloperationofthePeriodicTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAandCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0TMnC0 TnPAU TnCK TnCK1 TnCK0 TnON — — —TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnCAPTS TnCCLRTMnDL D7 D D5 D D3 D D1 D0TMnDH — — — — — — D9 D8TMnAL D7 D D5 D D3 D D1 D0TMnAH — — — — — — D9 D8TMnRPL D7 D D5 D D3 D D1 D0TMnRPH — — — — — — D9 D8

10-bit Periodic TM Register List (n=0~2)

TMnC0 Register Bit 7 6 5 4 3 2 1 0

Nae TnPAU TnCK TnCK1 TnCK0 TnON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —

Bit7 TnPAU:TMnCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 TnCK2 ~ TnCK0:SelectTMnCounterclock000:fSYS/4001:fSYS010:fH/16011:fH/64100:fTBC101:fH

110:TCKnrisingedgeclock111:TCKnfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 TnON:TMnCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTMOutputcontrolbit,whenthebitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas“0”

Rev. 1.10 Deee 1 01 Rev. 1.10 3 Deee 1 01



TMnC1 Register Bit 7 6 5 4 3 2 1 0

Nae TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnCAPTS TnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 TnM1~TnM0:SelectTMnOperationMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheTnM1andTnM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 TnIO1~TnIO0:SelectTPnoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTPn01:InputcaptureatfallingedgeofTPn10:Inputcaptureatfalling/risingedgeofTPn11:Inputcapturedisabled

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthesebitsarebothzero,thennochangewill takeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheTnOCbit.NotethattheoutputlevelrequestedbytheTnIO1andTnIO0bitsmustbedifferent fromthe initialvaluesetupusing theTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheTnONbitfromlowtohigh.In thePWMMode, theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.It isnecessarytochangethevaluesoftheTnIO1andTnIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theTnIO1andTnIO0bitsarechangedwhentheTMisrunning.

Rev. 1.10 Deee 1 01 Rev. 1.10 5 Deee 1 01



Bit3 TnOC:TPnOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 TnPOL:TPnOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTPnoutputpin.WhenthebitissethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 TnCAPTS:TMncapturetriggersourceselect0:FromTPnpin1:FromTCKnpin

Bit0 TnCCLR:SelectTMnCounterclearcondition0:TMnComparatrorPmatch1:TMnComparatrorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that thePeriodicTMcontains twocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheTnCCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

TMnDL Register Bit 7 6 5 4 3 2 1 0

Nae D7 D D5 D D3 D D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TMnDL:TMnCounterLowByteRegisterbit7~bit0TMn10-bitCounterbit7~bit0

TMnDH RegisterBit 7 6 5 4 3 2 1 0

Nae — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 TMnDH:TMnCounterHighByteRegisterbit1~bit0

TMn10-bitCounterbit9~bit8

Rev. 1.10 Deee 1 01 Rev. 1.10 5 Deee 1 01



TMnAL Register Bit 7 6 5 4 3 2 1 0


Bit7~0 TMnAL:TMnCCRALowByteRegisterbit7~bit0TMn10-bitCCRAbit7~bit0

TMnAH Register Bit 7 6 5 4 3 2 1 0

Nae — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 TMnAH:TMnCCRAHighByteRegisterbit1~bit0

TMn10-bitCCRAbit9~bit8

TMnRPL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 TMnRPL:TMnCCRPLowByteRegisterbit7~bit0TMn10-bitCCRPbit7~bit0

TMnRPH Register Bit 7 6 5 4 3 2 1 0

Nae — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 TMnRPH:TMnCCRPHighByteRegisterbit1~bit0

TMn10-bitCCRPbit9~bit8

Rev. 1.10 Deee 1 01 Rev. 1.10 7 Deee 1 01



Periodic Type TM Operating ModesThePeriodicTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.

Compare Match Output ModeToselect thismode,bitsTnM1andTnM0in theTMnC1register, shouldbeallcleared to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HereboththeTnAFandTnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto“0”.

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaTnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchfromComparatorP,willhavenoeffectontheTMoutputpin.ThewayinwhichtheTMoutputpinchangesstatearedeterminedbytheconditionoftheTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheTMoutputpin,whichissetupaftertheTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1,TnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.10 Deee 1 01 Rev. 1.10 7 Deee 1 01



Counte Value

0x3FF

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin

Tie

CCRP=0

CCRP > 0

Counte oveflowCCRP > 0Counte leaed y CCRP value

Pause

Resue

Stop

Counte Restat

TnCCLR = 0; TnM [1:0] = 00

Output pin set to initial Level Low if TnOC=0

Output Toggle with TnAF flag

Note TnIO [1:0] = 10 Ative High Output seletHee TnIO [1:0] = 11

Toggle Output selet

Output not affeted y TnAF flag. Reains High until eset y TnON it

Output PinReset to Initial value

Output ontolled y othe pin-shaed funtion

Output Invetswhen TnPOL is high

Compare Match Output Mode – TnCCLR = 0Note:1.WithTnCCLR=0--aComparatorPmatchwillclearthecounter

2.TheTMoutputpiniscontrolledonlybytheTnAFflag

3.TheoutputpinisresettoinitialstatebyaTnONbitrisingedge

4.n=0~2

Rev. 1.10 8 Deee 1 01 Rev. 1.10 9 Deee 1 01



Counte Value

0x3FF

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin

Tie

CCRA=0

CCRA = 0Counte oveflowCCRA > 0 Counte leaed y CCRA value

Pause

Resue

Stop Counte Restat

TnCCLR = 1; TnM [1:0] = 00

Output pin set to initial Level Low if TnOC=0

Output Toggle with TnAF flag

Note TnIO [1:0] = 10 Ative High Output seletHee TnIO [1:0] = 11

Toggle Output selet

Output not affeted y TnAF flag. Reains High until eset y TnON it

Output PinReset to Initial value

Output ontolled y othe pin-shaed funtion

Output Invetswhen TnPOL is high

TnPF not geneated

No TnAF flag geneated on CCRA oveflow

Output does not hange

Compare Match Output Mode – TnCCLR = 1Note:1.WithTnCCLR=1--aComparatorAmatchwillclearthecounter

2.TheTMoutputpiniscontrolledonlybytheTnAFflag

3.TheoutputpinisresettoinitialstatebyaTnONrisingedge

4.TheTnPFflagisnotgeneratedwhenTnCCLR=1

5.n=0~2

Rev. 1.10 8 Deee 1 01 Rev. 1.10 9 Deee 1 01



Timer/Counter ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldallbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectivelyandalso theTnIO1andTnIO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible. In thePWMmode, theTnCCLRbithasnoeffectas thePWMperiod.BothoftheCCRPandCCRAregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

10-bit PTM, PWM Mode

Period Duty

CCRP CCRA

IffH=20MHz,TMclocksourceselectfH,CCRP=200andCCRA=50,

TheTMPWMoutputfrequency=(fH)/200=20MHz/200=100kHz,duty=50/200=25%

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

Rev. 1.10 70 Deee 1 01 Rev. 1.10 71 Deee 1 01



Counte Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TMn O/P Pin(TnOC=1)

Tie

Counte leaed y CCRP

Pause Resue Counte Stop if TnON it low

Counte Reset when TnON etuns high

TnM [1:0] = 10

PWM Duty Cyle set y CCRA

PWM esues opeation

Output ontolled y othe pin-shaed funtion Output Invets

When TnPOL = 1PWM Peiod set y CCRP

TMn O/P Pin(TnOC=0)

PWM Mode Note:1.HereCounterclearedbyCCRP

2.AcounterclearsetsthePWMPeriod

3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or01

4.TheTnCCLRbithasnoinfluenceonPWMoperation

5.n=0~2

Rev. 1.10 70 Deee 1 01 Rev. 1.10 71 Deee 1 01



Single Pulse Output ModeToselectthismode,therequiredbitpairs,TnM1andTnM0shouldbesetto10respectivelyandalsothecorrespondingTnIO1andTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theTnONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhentheTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheTnONbit isclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateTMinterrupts.ThecountercanonlyberesetbacktozerowhentheTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheTnCCLRbitisalsonotused.

Single Pulse Generation (n=0~2)

Rev. 1.10 7 Deee 1 01 Rev. 1.10 73 Deee 1 01



Counte Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Tie

Counte stopped y CCRA

PauseResue Counte Stops

y softwae

Counte Reset when TnON etuns high

TnM [1:0] = 10 ; TnIO [1:0] = 11

Pulse Width set y CCRA

Output Invetswhen TnPOL = 1

No CCRP Inteupts geneated

TM O/P Pin(TnOC=0)

TCKn pin

Softwae Tigge

Cleaed y CCRA ath

TCKn pin Tigge

Auto. set y TCKn pin

Softwae Tigge

Softwae Clea

Softwae TiggeSoftwae

Tigge

Single Pulse ModeNote:1.CounterstoppedbyCCRA

2.CCRPisnotused

3.ThepulseistriggeredbytheTCKnpinorbysettingtheTnONbithigh

4.ATCKnpinactiveedgewillautomaticallysettheTnONbithigh

5.IntheSinglePulseMode,TnIO[1:0]mustbesetto“11”andcannotbechanged.

6.n=0~2

Rev. 1.10 7 Deee 1 01 Rev. 1.10 73 Deee 1 01



Capture Input ModeToselectthismodebitsTnM1andTnM0intheTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheTPnorTCKnpin,selectedbytheTnCAPTSbitintheTMnC1register.Theinputpinactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheTnIO1andTnIO0bitsintheTMnC1register.ThecounterisstartedwhentheTnONbitchangesfromlowtohighwhichis initiatedusing theapplicationprogram.

WhentherequirededgetransitionappearsontheTPnorTCKnpinthepresentvalueinthecounterwillbelatchedintotheCCRAregisterandaTMinterruptgenerated.IrrespectiveofwhateventsoccurontheTPnorTCKnpinthecounterwillcontinuetofreerununtiltheTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheTnIO1andTnIO0bitscanselecttheactivetriggeredgeontheTPnorTCKnpintobearisingedge,fallingedgeorbothedgetypes.IftheTnIO1andTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheTPnorTCKnpin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AstheTPnorTCKnpinispinsharedwithotherfunctions,caremustbetakeniftheTMnisintheCaptureInputMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheTnCCLR,TnOCandTnPOLbitsarenotusedinthisMode.

Rev. 1.10 7 Deee 1 01 Rev. 1.10 75 Deee 1 01



Counte Value

YY

CCRP

TnON

TnPAU

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

CCRA Value

Tie

Counte leaed y CCRP

PauseResue

Counte Reset

TnM [1:0] = 01

TM aptue pin TPn o

TCKn

XX

Counte Stop

TnIO [1:0] Value

XX YY XX YY

Ative edge Ative

edgeAtive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disale Captue

Capture Input ModeNote:1.TnM[1:0]=01andactiveedgesetbytheTnIO[1:0]bits

2.ATMCaptureinputpinactiveedgetransferscountervaluetoCCRA

3.TheTnCCLRbitisnotused

4.Nooutputfunction–TnOCandTnPOLbitsarenotused

5.CCRPdetermines thecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero

6.n=0~2

Rev. 1.10 7 Deee 1 01 Rev. 1.10 75 Deee 1 01



Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D OverviewThedevicecontainsamulti-channelanalog todigitalconverterwhichcandirectly interface toexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoa12-bitdigitalvalue.Italsocanconverttheinternalsignals,suchastheOCPAOsignalfromtheOCPfunctionorDCtoDCvoltagefromtheseriesresistors, intoa12-bitdigitalvalue.TheexternalorinternalanalogsignaltobeconvertedisdeterminedbytheSAINS2~SAINS0bitstogetherwiththeSACS3~SACS0bits.Notethatwhentheinternalanalogsignalistobeconverted,thepin-sharedcontrolbitsshouldalsobeproperlyconfiguredexcept theSAINSandSACSbitfields.Moredetailed informationabout theA/Dinputsignal isdescribedin the“A/DConverterControlRegisters”and“A/DConverterInputSignal”sectionsrespectively.

TheaccompanyingblockdiagramshowstheinternalstructureoftheA/Dconvertertogetherwithitsassociatedregisters.

External Input Channels A/D Channel Select Bits Input Pins

SACS3~SACS0 AN0~AN5

Pin-shaed Seletion

OCPAO signal

SACS3~SACS0

SAINS~SAINS0

A/D Convete

START

ADBZ

ENADC

VSS

A/D Clok

÷ N (N=0~7)

fSYS

SACKS~SACKS0

VDDVREF

SAVRS1~SAVRS0ENADC

SADOL

SADOH

AN0

AN1

AN5

A/D Refeene Voltage

A/D DataRegistes

Seies esistos

A/D Converter Structure

Rev. 1.10 7 Deee 1 01 Rev. 1.10 77 Deee 1 01



A/D Converter Register DescriptionOveralloperationoftheA/Dconverteriscontrolledusingfourregisters.AreadonlyregisterpairexiststostoretheA/DConverterdata12-bitvalue.TheremainingtworegistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.

Register Name

Bit7 6 5 4 3 2 1 0

SADOL (ADRFS=0) D3 D D1 D0 — — — —

SADOL (ADRFS=1) D7 D D5 D D3 D D1 D0

SADOH (ADRFS=0) D11 D10 D9 D8 D7 D D5 D

SADOH (ADRFS=1) — — — — D11 D10 D9 D8

SADC0 START ADBZ ENADC ADRFS SACS3 SACS SACS1 SACS0SADC1 SAINS SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS SACKS1 SACKS0

A/D Converter Registers List

A/D Converter Data Registers – SADOL, SADOHAsthedevicecontainsaninternal12-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasSADOH,andalowbyteregister,knownasSADOL.After theconversionprocess takesplace, theseregisterscanbedirectlyreadbythemicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised, theformat inwhichthedata isstorediscontrolledbytheADRFSbit in theSADC0registerasshownintheaccompanyingtable.D0~D11aretheA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.NotethattheA/DconverterdataregistercontentswillbeclearedtozeroiftheA/Dconverterisdisabled.

ADRFSSADOH SADOL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D9 D8 D7 D D5 D D3 D D1 D0 0 0 0 01 0 0 0 0 D11 D10 D9 D8 D7 D D5 D D3 D D1 D0

A/D Converter Data Registers

A/D Converter Control Registers – SADC0, SADC1TocontrolthefunctionandoperationoftheA/Dconverter,twocontrolregistersknownasSADC0,SADC1areprovided.These8-bitregistersdefinefunctionssuchastheselectionofwhichanalogchannel is connected to the internalA/Dconverter, thedigitiseddata format, theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterbusystatus.TheSACS3~SACS0bitsintheSADC0registerareusedtodeterminewhichexternalchannelinputisselectedtobeconverted.TheSAINS2~SAINS0bitsintheSADC1registerareusedtodeterminethat theanalogsignal tobeconvertedcomesfromthe internalanalogsignalorexternalanalogchannel input. If theSAINS2~SAINS0bitsareset to“000”or“011~111”, theexternalanalogchannelinputisselectedtobeconvertedandtheSACS3~SACS0bitscandeterminewhichexternalchannelisselectedtobeconverted.IftheSAINS2~SAINS0bitsaresetto“001”,theOCPAOsignalfromtheOCPfunctionisselectedtobeconverted.If theSAINS2~SAINS0bitsareset to“010”,theDC/DCvoltageof theseriesresistors isselected tobeconverted.Caremustbe takenwhentheinternalanalogsignalisselectedtobeconverted.Iftheinternalanalogsignalisselectedtobeconverted, theSACS3~SACS0bitsmustbeproperlyset toselectafloatingstate.Otherwise, theexternalchannelinputwillbeconnectedtogetherwiththeinternalanalogsignal.Thiswillresultinunpredictablesituationssuchasanirreversibledamage.

Rev. 1.10 7 Deee 1 01 Rev. 1.10 77 Deee 1 01



SAINS [2:0] SACS [3:0] Input Signals Description

Exept 001 and 010

0000~0101 AN0~AN5 Extenal pin analog input0110~1111 — Floating

001 0110~1111 OPA output OCPAO signal fo the OCP funtion010 0110~1111 DC/DC voltage DC/DC voltage of the seies esistos

A/D Converter Input Signal Selection

SADC0 Register

Register Name

Bit7 6 5 4 3 2 1 0

Nae START ADBZ ENADC ADRFS SACS3 SACS SACS1 SACS0R/W R/W R R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 START:StarttheA/DConversion0→1→0:StartanA/Dconversion0→1:ResettheA/DconverterandcleartheADBZflagto“0”1→0:StarttheA/DconversionandsettheADBZflagto“1”

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.

Bit6 ADBZ:A/DConverterbusyflag0:NoA/Dconversionisinprogress1:A/Dconversionisinprogress

ThisreadonlyflagisusedtoindicatewhethertheA/Dconversionis inprogressornot.WhentheSTARTbitissetfromlowtohighandthentolowagain,theADBZflagwillbesetto1toindicatethattheA/Dconversionisinitiated.TheADBZflagwillbeclearedto0aftertheA/Dconversioniscomplete.

Bit5 ENADC:A/DConverterfunctionenablecontrol0:Disable1:Enable

Thisbitcontrols theA/Dinternal function.Thisbitshouldbeset toone toenabletheA/Dcomverter.If thebit isset low,thentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.WhentheA/Dconverterfunctionisdisabled,thecontentsoftheA/Ddataregisterpair,SADOHandSADOL,willbeclearedto0.

Bit4 ADRFS:A/DConverterdataformatcontrol0:A/Dconverterdataformat→SADOH=D[11:4];SADOL=D[3:0]1:A/Dconverterdataformat→SADOH=D[11:8];SADOL=D[7:0]

Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Dconverterdataregistersection.

Bit3~0 SACS3~SACS0:A/Dconverterexternalanaloginputchannelselect0000:AN00001:AN10010:AN20011:AN30100:AN40101:AN50110~1111:Floating

Rev. 1.10 78 Deee 1 01 Rev. 1.10 79 Deee 1 01



SADC1 Register

Register Name

Bit7 6 5 4 3 2 1 0

Nae SAINS SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS SACKS1 SACKS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~5 SAINS2~SAINS0:A/Dconverterinputsignalselect000:Externalsource–Externalanalogchannelinput001:Internalsource–OCPAOsignalfromtheOCPfunction010:Internalsource–DC/DCvoltageoftheseriesresistors011~111:Externalsource–Externalanalogchannelinput

CaremustbetakeniftheSAINS2~SAINS0bitsaresetto“001”or“010”toselecttheinternalanalogsignal tobeconverted.Whentheinternalanalogsignal isselectedtobeconverted,theSACS3~SACS0bitsmustbeset toavaluefrom“0110”to“1111”.Otherwise,theexternalchannelinputwillbeconnectedtogetherwiththeinternalanalogsignal.Thiswillresultinunpredictablesituationssuchasanirreversibledamage.

Bit4~3 SAVRS1~SAVRS0:A/Dconverterreferencevoltageselect00:FromVREFpin01:FromVDDpin1x:FromVREFpin

Bit2~0 SACKS2~SACKS0:A/Dconversionclocksourceselect000:fSYS001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:fSYS/128

ThesebitsareusedtoselecttheclocksourcefortheA/Dconverter.

A/D OperationTheSTARTbitisusedtostarttheADconversion.Whenthemicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,theA/Dconversionwillnotbeinitiated.

TheADBZbit intheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversionprocessisinprogressornot.Thisbitwillbeautomaticallysetto1bythemicrocontrollerafteranA/Dconversionissuccessfullyinitiated.WhentheA/Dconversioniscomplete,theADBZwillbeclearedto0.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbeset in theinterruptcontrolregister,andiftheinterruptsareenabled,aninternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowtotheassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled, themicrocontrollercanpoll theADBZbitintheSADC0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

Although theA/D clock source is determined by the system clock fSYS, and by bitsSACKS2~SADCKS0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstherecommendedrangeofpermissibleA/Dclockperiod, tADCK, isfrom0.5μsto10μs,caremustbetakenforselectedsystemclockfrequencies.Forexample, if thesystemclockoperatesatafrequencyof4MHz, theSACKS2~SADCKS0bitsshouldnotbeset to000or11x.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.

Rev. 1.10 78 Deee 1 01 Rev. 1.10 79 Deee 1 01



fSYS

A/D Clock Period (tADCK)

SACKS [2:0]= 000

(fSYS)

SACKS [2:0]= 001

(fSYS/2)

SACKS [2:0]= 010

(fSYS/4)

SACKS [2:0]= 011

(fSYS/8)

SACKS [2:0]= 100(fSYS/16)

SACKS [2:0]= 101(fSYS/32)

SACKS [2:0]= 110(fSYS/64)

SACKS [2:0]= 111(fSYS/128)

1 MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs *

MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs *

MHz 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs *

8 MHz 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs 16μs *

1 MHz 83ns * 167ns * 333ns * 7ns 1.33μs 2.67μs 5.33μs 10.67μs *

1 MHz 62.5ns * 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs

0 MHz 50ns * 100ns * 200ns * 400ns * 800ns 1.6μs 3.2μs 6.4μs

A/D Clock Period Examples

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theENADCbitintheSADC0register.ThisbitmustbesethightopowerontheA/Dconverter.WhentheENADCbit issethigh topoweron theA/Dconverter internalcircuitryacertaindelay,asindicatedinthetimingdiagram,mustbeallowedbeforeanA/Dconversionisinitiated.EvenifnopinsareselectedforuseasA/Dinputsbyconfiguringthecorrespondingpin-sharedcontrolbits,iftheENADCbitishighthensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheENADCissetlowtoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

ThereferencevoltagesupplytotheA/DConvertercanbesuppliedfromeitherthepositivepowersupplypin,VDD,orfromanexternalreferencesourcessuppliedonpinVREF.ThedesiredselectionismadeusingtheSAVRS1andSAVRS0bits.WhentheSAVRSbitfieldisset to“01”, theA/DconverterreferencevoltagewillcomefromtheVDDpin.Otherwise,iftheSAVRSbitfieldissettoanyothervalueexcept“01”,theA/DconverterreferencevoltagewillcomefromtheVREFpin.AstheVREFpinispin-sharedwithotherfunctions,whentheVREFpinisselectedasthereferencevoltagesupplypin, theVREFpin-sharedfunctioncontrolbitsshouldbeproperlyconfigured todisableotherpinfunctions.

SAVRS [1:0] Reference Voltage Description00 VREF A/D Convete Refeene voltage oes fo VREF pin01 VDD A/D Convete Refeene voltage oes fo VDD pin1x VREF A/D Convete Refeene voltage oes fo VREF pin

A/D Converter Reference Voltage Selection

Rev. 1.10 80 Deee 1 01 Rev. 1.10 81 Deee 1 01



A/D Input PinsAllof theA/Danaloginputpinsarepin-sharedwiththeI/Opinsaswellasotherfunctions.Thecorrespondingpin-sharedfunctionselectionbitsforeachpinintheCTRL3andCTRL4registers,determinewhethertheexternalpinsaresetupasA/Dconverteranalogchannelinputsortheyhaveotherfunctions.IfthecorrespondingpinissetuptobeanA/Dconverteranalogchannelinput,theoriginalpinfunctionswillbedisabled.Inthisway,pinscanbechangedunderprogramcontroltochangetheirfunctionbetweenA/Dinputsandotherfunctions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedifthepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputintheportcontrolregistertoenabletheA/Dinputaswhentherelevantpin-sharedfunctionselectionbitsenableanA/Danalogchannelinput,thestatusoftheportcontrolregisterwillbeoverridden.

TheA/Dconverterhasitsownreferencevoltagepin,VREF.However,thereferencevoltagecanalsobesuppliedfromthepowersupplypin,achoicewhichismadethroughtheSAVRS1andSAVRS0bitsintheSADC1register.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF.

Conversion Rate and Timing DiagramAcompleteA/Dconversioncontains twoparts,data samplinganddataconversion.ThedatasamplingwhichisdefinedastADStakes4A/Dclockcyclesandthedataconversiontakes12A/Dclockcycles.Thereforeatotalof16A/DclockcyclesforanA/DconversionwhichisdefinedastADCarenecessary.

MaximumsingleA/Dconversionrate=A/Dclockperiod/16

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKclockcycleswheretADCKisequaltotheA/Dclockperiod.

ENADC

START

ADBZ

SACS[3:0]

off on off on

tONST

tADS

A/D sapling tietADS

A/D sapling tie

Stat of A/D onvesion Stat of A/D onvesion Stat of A/D onvesion

End of A/D onvesion

End of A/D onvesion

tADC

A/D onvesion tietADC

A/D onvesion tietADC

A/D onvesion tie

0011B 0010B 0000B 0001B

A/D hannel swith

A/D Conversion Timing

Rev. 1.10 80 Deee 1 01 Rev. 1.10 81 Deee 1 01



Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbyproperlyprogrammingtheSACKS2~SACKS0bitsintheSADC1register.

• Step2EnabletheA/DconverterbysettingtheENADCbitintheSADC0registertoone.

• Step3SelectwhichsignalistobeconnectedtotheinternalA/DconverterbycorrectlyconfiguringtheSAINS2~SAINS0bitsSelecttheexternalchannelinputtobeconverted,gotoStep4.Selecttheinternalanalogsignaltobeconverted,gotoStep5.

• Step4IftheA/DinputsignalcomesfromtheexternalchannelinputselectingbyconfiguringtheSAINSbitfield,thecorrespondingpinsshouldfirstbeconfiguredasA/Dinputfunctionbyconfiguringtherelevantpin-sharedfunctioncontrolbits.ThedesiredanalogchannelthenshouldbeselectedbyconfiguringtheSACSbitfield.Afterthisstep,gotoStep6.

• Step5BeforetheA/DinputsignalisselectedtocomefromtheinternalanalogsignalbyconfiguringtheSAINSbitfield,theSACSbitfieldmustbefirstconfiguredtoavaluefrom“0110”to“1111”todisconnecttheexternalchannelinput.ThedesiredinternalanalogsignalthencanbeselectedbyconfiguringtheSAINSbitfield.Afterthisstep,gotoStep6.

• Step6SelectthereferencevoltgagesourcebyconfiguringtheSAVRS1~SAVRS0bits.

• Step7SelecttheA/DconverteroutputdataformatbyconfiguringtheADRFSbit.

• Step8IfA/Dconversioninterruptisused,theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dinterruptfunctionisactive.Themasterinterruptbontrolbit,EMI,andtheA/Dconversioninterruptcontrolbit,ADE,mustbothbesethighinadvance.

• Step9TheA/DconversionprocedurecannowbeinitializedbysettingtheSTARTbitfromlowtohighandthenlowagain.

• Step10IfA/Dconversion is inprogress, theADBZflagwillbesethigh.After theA/Dconversionprocess iscomplete, theADBZflagwillgo lowand then theoutputdatacanbe readfromSADOHandSADOLregisters.

Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheADBZbitintheSADC0registerisused,theinterruptenablestepabovecanbeomitted.

Rev. 1.10 8 Deee 1 01 Rev. 1.10 83 Deee 1 01



Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,bysettingbitENADClowin theSADC0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAsthedevicescontaina12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheVDDorVREFvoltage,thisgivesasinglebitanaloginputvalueofVDDorVREFdividedby4096.

1LSB=(VDDorVREF)÷4096

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×(VDDorVREF)÷4096

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDorVREFlevel.

Ideal A/D Transfer Function

Rev. 1.10 8 Deee 1 01 Rev. 1.10 83 Deee 1 01



A/D Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheADBZbit intheSADC0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an ADBZ polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov SADC1,a ; select fSYS/8 as A/D clockset ENADCmov a,01H ; setup CTRL3 to configure pin AN0mov CTRL3,amov a,20Hmov SADC0,a ; enable and connect AN0 channel to A/D converter:start_conversion:clr START ; high pulse on start bit to initiate conversionset START ; reset A/Dclr START ; start A/D:polling_EOC:sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversionjmp polling_EOC ; continue polling:mov a,SADOL ; read low byte conversion result valuemov ADRL_buffer,a ; save result to user defined registermov a,SADOH ; read high byte conversion result valuemov ADRH_buffer,a ; save result to user defined register:jmp start_conversion ; start next A/D conversion

Rev. 1.10 8 Deee 1 01 Rev. 1.10 85 Deee 1 01



Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov SADC1,a ; select fSYS/8 as A/D clockset ENADCmov a,01h ; setup CTRL3 to configure pin AN0mov CTRL3,amov a,20hmov SADC0,a ; enable and connect AN0 channel to A/D converter:Start_conversion:clr START ; high pulse on START bit to initiate conversionset START ; reset A/Dclr START ; start A/Dclr ADF ; clear ADC interrupt request flagset ADE ; enable ADC interruptset EMI ; enable global interrupt::ADC_ISR: ; ADC interrupt service routinemov acc_stack,a ; save ACC to user defined memorymov a,STATUSmov status_stack,a ; save STATUS to user defined memory:mov a, SADOL ; read low byte conversion result valuemov adrl_buffer,a ; save result to user defined registermov a, SADOH ; read high byte conversion result valuemov adrh_buffer,a ; save result to user defined register:EXIT_INT_ISR:mov a,status_stackmov STATUS,a ; restore STATUS from user defined memorymov a,acc_stack ; restore ACC from user defined memoryreti

Rev. 1.10 8 Deee 1 01 Rev. 1.10 85 Deee 1 01



Complementary PWM output ThedeviceprovidesacomplementaryoutputpairofsignalswhichcanbeusedasaPWMdriversignal.ThesignalissourcedfromtheTM0outputsignal,TP0.ForPMOStypeuppersidedriving,thePWMoutputisanactivelowsignalwhileforNMOStypelowersidedrivingthePWMoutputisanactivehighsignal.WhenthesecomplementaryPWMoutputsarebothusedtodrivetheupperandlowsides,thedeadtimegeneratormustbeenabledusingtheDTENbitintheCPRregister,andthenadeadtime,whichisprogrammableusingtheDTPSCandDTbitfieldsintheCPRregister,willbe insertedtopreventexcessiveDCcurrents.Thedeadtimewillbe insertedwhenever therisingedgeofthedeadtimegenerator inputsignaloccurs.Withadeadtimeinsertion, theoutputsignalsexperienceadelaybeforebeingeventually sentout to theexternalpower transistors.ThePWM0HorPWM0Lsignal,canbecontrolledbythePWMHorPWMLsignalsrepectivelyor remainsatacertain level, thesearedeterminedby theDCPD_CTL1andDCPD_CTL0bitsrepectively.ThePWM0HandPWM0Lpinsarepin-sharedwithotherfuncitonsandcanbeselectedascomplementaryPWMoutputsbytherevelantpin-sharedcontrolbitsintheCTRL4register.

TP0

Dead Tie Geneato

DTPSC [1:0]

PesalefH

A

B

DT [:0]

E

C D PWMH

PWML

fD

MUX

0

0

1

DCPD_CTL0

PWM0L

PWM0H

DCPD_CTL1

MUX

1

0

1

Complementary PWM Output Block Diagram

TP0

A

B

C

D

E

Dead Tie

Dead Tie

Dead Tie

Dead Tie

Dead Tie

Dead Tie

Complementary PWM Output Waveform

Rev. 1.10 8 Deee 1 01 Rev. 1.10 87 Deee 1 01



CPR Register Bit 7 6 5 4 3 2 1 0

Nae DTEN PWMHPOL PWMLPOL DTPSC1 DTPSC0 DT DT1 DT0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 0 0 0 0 0 0 0

Bit7 DTEN:Deadtimeenable0:Disable1:Enable

Bit6 PWMHPOL:PWMHOutputpolaritycontrol0:Non-invert1:Invert

Bit5 PWMLPOL:PWMLOutputpolaritycontrol0:Non-invert1:Invert

Bit4~3 DTPSC1~DTPSC0: Deadtimeprescalerdivisionratioselect00:fD=fH/101:fD=fH/210:fD=fH/411:fD=fH/8

Bit2~0 DT2~DT0: Deadtimeselect000:deadtimeis[(1/fD)-(1/fH)]~(1/fD)001:deadtimeis[(2/fD)-(1/fH)]~(2/fD)010:deadtimeis[(3/fD)-(1/fH)]~(3/fD)011:deadtimeis[(4/fD)-(1/fH)]~(4/fD)100:deadtimeis[(5/fD)-(1/fH)]~(5/fD)101:deadtimeis[(6/fD)-(1/fH)]~(6/fD)110:deadtimeis[(7/fD)-(1/fH)]~(7/fD)111:deadtimeis[(8/fD)-(1/fH)]~(8/fD)


Nae — HV_S1 HV_S0 DCPD_CTL1 DCPD_CTL0 BZ_S1 BZ_S0 BZ_CTLR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6~5 HV_S1~HV_S0:ControlsignaltypeselectionforHV_EN

Describedelsewhere.Bit4 DCPD_CTL1:DCtoDCPWUPControl

0:PWM0Halwayshighandbuild-inM4PMOSalwaysoff1:PWM0HsignalfromPWMH

Bit3 DCPD_CTL0:DCtoDCPWDNControl0:PWM0Lalwayslow1:PWM0LsignalfromPWML

Bit2~1 BZ_S1~BZ_S0:ControlsignaltypeselectionforBuzzer_ENDescribedelsewhere.

Bit0 BZ_CTL:BuzzerControlDescribedelsewhere.

Rev. 1.10 8 Deee 1 01 Rev. 1.10 87 Deee 1 01



Over Current Protection Thedeviceincludesanovercurrentprotectionfunctionwhichprovidesaprotectionmechanismforapplications.Topreventthebatterychargeorloadcurrentfromexceedingaspecificlevel,thecurrentontheOCP0andOCP1pinsandfromtheseriesresistorsareconvertedtoarelevantvoltagelevelaccordingtothecurrentvalueusingtheOCPoperationalamplifier.Itisthencomparedwithareferencevoltagegeneratedbyan8-bitD/Aconverter.Whenanovercurrenteventoccurs,anOCPinterruptwillbegeneratedifthecorrespondinginterruptcontrolisenabled.

Over Current Protection OperationTheOCPcircuitisusedtopreventtheinputcurrentfromexceedingareferencelevel.ThecurrentontheOCP0orOCP1pinorfromtheseriesresistorsisconvertedtoavoltageandthenamplifiedbytheOCPoperationalamplifierwithaprogrammablegainfrom1to50selectedbytheG2~G0bitsintheOCPC1register.ThisisknownastheProgrammableGainAmplifierorPGA.ThisPGAcanalsobeconfiguredtooperateinthenon-inverting,invertingorinputoffsetcancellationmodedeterminedbytheENOCP1andENOCP0bitsintheOCPC0register.Afterthecurrentisconvertedandamplifiedtoaspecificvoltagelevel,itwillbecomparedwithareferencevoltageprovidedbyan8-bitD/Aconverter.The8-bitD/Aconverterpowercanbesuppliedbytheexternalpowerpin,VDDorVREF,selectedbytheOCPVSbitintheOCPC0register.Thecomparatoroutput,CPOUT,willfirstbefilteredwithacertainde-bouncetimeperiodselectedbytheFLT2~FLT0bitsintheOCPC1register.ThenafilteredOCPdigitalcomparatoroutput,OCPO,isobtainedtoindicatewhetheranovercurrentconditionoccursornot.TheOCPObitwillbeset to1ifanovercurrentconditionoccurs.Otherwise, theOCPObit iszero.Onceanovercurrenteventoccurs, i.e., theconvertedvoltageoftheOCPinputcurrentisgreaterthanthereferencevoltage,thecorrespondinginterruptwillbegeneratediftherelevantinterruptcontrolbitisenabled.

8-itD/AOCPDA[7:0]

Filte

(To A/D intenal input)

R1R(R1=K)

Gain=1/5/10/15/0/30/0/50

OCPO

S1

S0

S

S3

G[:0]

fFLT=fH

ENOCP[1:0]

OPAMP

VDD VREF

OCPVS

OCPCHY

CPOUT

FLT[:0]

OCPAO

OCPINTCMP

(OCP flag)OCP0

OCP1

Seies esistos

OCPS[1:0]

S

Over Current Protection Block Diagram

Rev. 1.10 88 Deee 1 01 Rev. 1.10 89 Deee 1 01



Over Current Protection Control RegistersOveralloperationoftheovercurrentprotectioniscontrolledusingseveralregisters.Oneregisterisusedtoprovidethereferencevoltagesfortheovercurrentprotectioncircuit.Therearetworegistersusedtocancelouttheoperationalamplifierandcomparatorinputoffset.TheremainingtworegistersarecontrolregisterswhichcontroltheOCPfunction,D/Aconverterreferencevoltageselect,PGAgainselect,comparatorde-bouncetimetogetherwiththehysteresisfunction.Therearetwocontrolbits,OCPS1andOCPS0,intheCTRL2registerusedtoconfiguretheOCPinputcomingfromOCP0orOCP1pinorfromtheseriesresistors.AsfortheOCP0orOCP1pincontrol,therearerevelantpin-sharedcontrolbitstoconfiguretheOCPinputpins.Foramoredetaileddescriptionregardingtheinputoffsetvoltagecancellationprocedures,refertothecorrespondinginputoffsetcancellationsections.

Register Name

Bit

7 6 5 4 3 2 1 0

OCPC0 ENOCP1 ENOCP0 OCPVS OCPCHY — — — OCPO

OCPC1 — — G G1 G0 FLT FLT1 FLT0

OCPDA D7 D D5 D D3 D D1 D0

OCPOCAL OOFM ORSP OOF5 OOF OOF3 OOF OOF1 OOF0

OCPCCAL CPOUT COFM CRSP COF COF3 COF COF1 COF0

CTRL SW_EN — LED_S1 LED_S0 LED_CTL OCPS1 OCPS0 HV_CTL

OCP Register List

OCPC0 RegisterBit 7 6 5 4 3 2 1 0

Nae ENOCP1 ENOCP0 OCPVS OCPCHY — — — OCPOR/W R/W R/W R/W R/W — — — RPOR 0 0 0 0 — — — 0

Bit7~6 ENOCP1~ENOCP0:OCPfunctionoperatingmodeselection00:OCPfunctiondisabled,S1andS3on,S0andS2off01:OCPoperatesinnon-invertermode,S0andS3on,S1andS2off10:OCPoperatesininvertermode,S1andS2on,S0andS3off11:OCPoperatesincalibrationmode,S1andS3on,S0andS2off

Bit5 OCPVS:OCPD/AConverterreferencevoltageselection0:FromVDDpin1:FromVREFpin

Bit4 OCPCHY:OCPComparatorHysteresisfunctioncontrol0:Disable1:Enable

Bit3~1 Unimplemented,readas“0”Bit0 OCPO:OCPComparatorFiltereddigitaloutputflag

0:NoOverCurrentconditionoccurs1:OverCurrentconditionoccurs

Rev. 1.10 88 Deee 1 01 Rev. 1.10 89 Deee 1 01



OCPC1 RegisterBit 7 6 5 4 3 2 1 0

Nae — — G G1 G0 FLT FLT1 FLT0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5~3 G2~G0:PGAR2/R1ratioselection

000:Unitygainbuffer(non-invertingmode)orgain=1(invertingmode)001:R2/R1=5010:R2/R1=10011:R2/R1=15100:R2/R1=20101:R2/R1=30110:R2/R1=40111:R2/R1=50

ThesebitsareusedtoselecttheR2/R1ratiotoobtainvariousgainvaluesforinvertingandnon-invertingmode.Thecalculatingformulaof thePGAgainfor theinvertingandnon-invertingmodeisdescribedinthe“InputVoltageRange”section.

Bit2~0 FLT2~FLT0:OCPoutputfilterde-bouncetimeselection000:Nodebounce001:(1~2)×tFLT010:(3~4)×tFLT011:(7~8)×tFLT100:(15~16)×tFLT101:(31~32)×tFLT110:(63~64)×tFLT111:(127~128)×tFLT

Note:fFLT=fH,tFLT=1/fFLT

OCPDA RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 OCPD/AConverterDataRegisterbit7~bit0OCPD/AConverterOutput=(DACreferencevoltage/256)×D[7:0]

OCPOCAL RegisterBit 7 6 5 4 3 2 1 0

Nae OOFM ORSP OOF5 OOF OOF3 OOF OOF1 OOF0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 OOFM:OCPOperationalAmplifierInputOffsetCancellationModeEnablecontrol0:InputOffsetCancellationModeDisabled1:InputOffsetCancellationModeEnabled

Thisbit isused tocontrol theOCPoperationalamplifier inputoffsetcancellationfunction.TheENOCP1andENOCP0bitsmustfirstbesetto“11”andthentheOOFMbitmustbesetto1followedbytheCOFMbitbeingsettingto0,thentheoperationalamplifier inputoffsetcancellationmodewillbeenabled.Refer to the“OperationalAmplifier InputOffsetCancellation”section for thedetailedoffsetcancellationprocedures.

Rev. 1.10 90 Deee 1 01 Rev. 1.10 91 Deee 1 01



Bit6 ORSP:OCPOperationalAmplifierInputOffsetCancellationReferenceInputselect0:Operationalamplifiernegativeinputisselected1:Operationalamplifierpositiveinputisselected

Bit5~0 OOF5~OOF0:OCPOperationalAmplifierInputOffsetCancellationvalueThis6-bitfieldisusedtoperformtheoperationalamplifierinputoffsetcancellationoperationandthevaluefortheOCPoperationalamplifierinputoffsetcancellationcanberestoredintothisbitfield.Moredetailedinformationisdescribedinthe“OperationalAmplifierInputOffsetCancellation”section.

OCPCCAL RegisterBit 7 6 5 4 3 2 1 0

Nae CPOUT COFM CRSP COF CF3 COF COF1 COF0R/W R R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 1 0 0 0 0

Bit7 CPOUT:OCPComparatororOperationAmplifierDigitalOutputinInputOffsetCancellationMode0:Positiveinputvoltage<Negativeinputvoltage1:Positiveinputvoltage>Negativeinputvoltage

Thisbit isused to indicatewhether thepositive inputvoltage isgreater than thenegativeinputvoltagewhentheOCPoperatesintheinputoffsetcancellationmode.IftheCPOUTissetto1,thepositiveinputvoltageisgreaterthanthenegativeinputvoltage.Otherwise,thepositiveinputvoltageislessthanthenegativeinputvoltage.

Bit6 COFM:OCPComparatorInputOffsetCancellationModeEnablecontrol0:InputOffsetCancellationModeDisabled1:InputOffsetCancellationModeEnabled

ThisbitisusedtocontroltheOCPcomparatorinputoffsetcancellationfunction.TheENOCP1andENOCP0bitsmustfirstbeset to“11”andthentheCOFMbitmustbesetto1followedbytheOOFMbitbeingsettingto0, thenthecomparatorinputoffsetcancellationmodewillbeenabled.Refer to the“Comparator InputOffsetCancellation”sectionforthedetailedoffsetcancellationprocedures.

Bit5 CRSP:OCPComparatorInputOffsetCancellationReferenceInputselect0:Comparatornegativeinputisselected1:Comparatorpositiveinputisselected

Bit4~0 COF4~COF0:OCPComparatorInputOffsetCancellationvalueThis5-bitfieldisusedtoperformthecomparatorinputoffsetcancellationoperationandthevaluefortheOCPcomparatorinputoffsetcancellationcanberestoredintothisbitfield.Moredetailedinformationisdescribedinthe“ComparatorInputOffsetCancellation”section.

Rev. 1.10 90 Deee 1 01 Rev. 1.10 91 Deee 1 01




Nae SW_EN — LED_S1 LED_S0 LED_CTL OCPS1 OCPS0 HV_CTLR/W R/W — R/W R/W R/W R/W R/W R/WPOR 0 — 0 0 0 0 0 1

Bit7 SE_EN:SWControlDescribedelsewhere.

Bit6 Unimplemented,readas“0”Bit5~4 LED_S1~LED_S0:ControlsignaltypeselectionforLED_EN

Describedelsewhere.Bit3 LED_CTL:LEDControl

Describedelsewhere.Bit2~1 OCPS1~OCPS0:OCPinputselection

00:FromOCP0pin01:FromOCP1pin1x:Fromseriesresistors

Bit0 HV_CTL:HighVoltageControlDescribedelsewhere.

Input Voltage RangeTogetherwithdifferentPGAoperatingmodes,theinputvoltageontheOCPpincanbepositiveornegativetoprovidediverseapplicationsforthedevice.ThePGAoutputforthepositiveornegativeinputvoltageisrespectivelycalculatedbasedondifferentformulasanddescribedbythefollowing.

• ForinputvoltageVIN>0,thePGAoperatesinthenon-invertingmodeandthePGAoutputisobtainedusingtheformulabelow:

IN

1

2OUT Vx )

RR(1V +=

• WhenthePGAoperatesinthenon-invertingmodebysettingtheENOCP1andENOCP0bitsto“01”withunitygainselectbysettingtheG2~G0to“000”,thePGAwillactasanunit-gainbufferwhoseoutputisequaltoVIN.

INOUT VV =

• Forinputvoltage0>VIN>-0.4,thePGAoperatesintheinvertingmodeandthePGAoutputisobtainedusingtheformulabelow.Notethatiftheinputvoltageisnegative,itcannotbelowerthan-0.4Vwhichwillresultincurrentleakage.

IN

1

2OUT Vx

RRV −=

Rev. 1.10 9 Deee 1 01 Rev. 1.10 93 Deee 1 01



Offset CalibrationTooperateintheinputoffsetcancellationmodefortheOCPcircuit,theENOCPC1andENOCPC0bitsshouldfirstbesetto“11”.Foroperationalamplifierandcomparatorinputoffsetcancellation,theproceduresaresimilarexceptforsettingtherespectivecontrolbits.

Operational Amplifier Input Offset Cancellation • Step1:SetENOCP[1:0]=11,OOFM=1andCOFM=0,theOCPwilloperateintheoperationalamplifierinputoffsetcancellationmode.

• Step2:SetOOF[5:0]=000000andreadtheCPOUTbit.

• Step3:IncreasetheOOF[5:0]valueby1andthenreadtheCPOUTbit.♦ IftheCPOUTbitstatehasnotchanged,thenrepeatStep3untiltheCPOUTbitstatehaschanged.

♦ IftheCPOUTbitstatehaschanged,recordtheOOFvalueasVOOS1andthengotoStep4.

• Step4:SetOOF[5:0]=111111andreadtheCPOUTbit.

• Step5:DecreasetheOOF[5:0]valueby1andthenreadtheCPOUTbit.♦ IftheCPOUTbitstatehasnotchanged,thenrepeatStep5untiltheCPOUTbitstatehaschanged.

♦ IftheCPOUTbitstatehaschanged,recordtheOOFvalueasVOOS2andthengotoStep6.

• Step6:RestoretheoperationalamplifierinputoffsetcancellationvalueVOOSintotheOOF[5:0]bitfield.Theoffsetcancellationprocedureisnowfinished.

Where 2

VOOS2VOOS1OSV +=O

Comparator input Offset Cancellation • Step1:SetENOCP[1:0]=11,COFM=1andOOFM=0,theOCPwillnowoperateinthecomparatorinputoffsetcancellationmode.S4ison(S4isusedforcalibrationmode,innormalmodeoperation,itisoff).

• Step2:SetCOF[4:0]=00000andreadtheCPOUTbit.

• Step3:IncreasetheCOF[4:0]valueby1andthenreadtheCPOUTbit.♦ IftheCPOUTbitstatehasnotchanged,thenrepeatStep3untiltheCPOUTbitstatehaschanged.

♦ IftheCPOUTbitstatehaschanged,recordtheCOFvalueasVCOS1andthengotoStep4.

• Step4:SetCOF[4:0]=11111andreadtheCPOUTbit.

• Step5:DecreasetheCOF[4:0]valueby1andthenreadtheCPOUTbit.♦ IftheCPOUTbitstatehasnotchanged,thenrepeatStep5untiltheCPOUTbitstatehaschanged.

♦ IftheCPOUTbitstatehaschanged,recordtheCOFvalueasVCOS2andthengotoStep6.

• Step6:RestorethecomparatorinputoffsetcancellationvalueVCOSintotheCOF[4:0]bitfield.Theoffsetcancellationprocedureisnowfinished.

Where 2

VCOS2VCOS1VCOS +=

Rev. 1.10 9 Deee 1 01 Rev. 1.10 93 Deee 1 01



Emergency Light Application DescriptionIn theemergency lightproducts,aMCUdetermines tobuckchargeorboostcharge toprovidetherequiredemergencylightingpoweraccording to theconditionsof themainssupplyand thechargeablebattery.Thisdevicehasincludesarangeoffunctionsrelatedtoemergencylights.UsinganinternalpowerMOS,thedevicecaneasilyimplementtheabovefunctionswhilemeetingtheassociatedChinesenationalstandards.Therelatedoperationsaredescribedasbelow.

Charge under Normal Mains SupplyAnemergencylightisusuallypoweredbythemainssupplywithACpowerbeingconvertedtoDCpower.Whenthevoltageiswithin12V,itcanbedirectlyconnectedtotheHV_INpintoprovidepowerfortheMCUandothercircuits.Inthiscase,fora1.2Vchargeablebattery,buckchargecanbeimplementedbyturningontheM0andM4(controlledbyPWMoutputs)aswellastheBAT_INpinexternallyconnectedwithaninductor,aschottkydiodeandthebattery.TheA/Dconvertercanbeusedforchargingcurrentcontrol.Forabetterbuckchargeresult,connectanexternalNMOStothePA7pinforsynchronousrectification.

Analog Battery Boost Charge under Normal Mains SupplyTurnoff theM0,usetheM4andPA7pinforcomplementaryPWMcontrol,andthenexternallyconnectanNMOSandaninductortoboostthebatteryvoltageorcurrenttoahighlevelrequiredbytheLEDlighting.Afterthehighvoltagehasbeengenerated,itcanbereadbytheinternalresistordividerwhichisenabledusingtheSW_ENbittoimplementconstantvoltagefeedbackcontrol.Forabetterboostchargeresult,connectaschottkydiodeinparallelbetweentheBAT_INpinandtheHV_OUTpin.Refertotheapplicationcircuitsectionformoredetails.

Buzzer DrivingTheM1andM2togetherformthebuzzerdedicatedoutputpin,it iscontrolledbytheBZ_S0andBZ_S1bitstooutputaPWMsignaloraconstanthigh/lowlevel.

LED DrivingTheLED_OUTpinisaLEDdrivingoutputpin.TheinternalhighvoltagepoweristransmittedtothispinbytheM3MOStodrivingtheLED.WhethertouseaPWMsignalforLEDdimmingandconstantcurrentcontrolortoenable/disabletheLDO_OUTpinoutputisdeterminedbytheLED_S0andLED_S1bits.

Rev. 1.10 9 Deee 1 01 Rev. 1.10 95 Deee 1 01



High Voltage MOSThisdeviceintegratesseveralhighvoltageMOStransistorswithlevelshiftfunctions,whichalongwiththeLDOregulatorareusedforPowercontrol,LEDcontrol,buzzerdrivercontrolandcharge/dischargecontrol.

LDO(5V/50A)

HV_IN

(7V~1V)

Charge/Discharge Control

Buzzer Driver Circuit

Level Shift

Copleentay PWM

Level Shift

Level ShiftLe

vel S

hift

LED Control Circuit

HV_OUT

VIN

LED_OUT

BZ

BAT_IN

VDD

M0

M1

M

M3

MLED_EN

HV_EN

HV

PA7/PWM0L

5V

00K

100K

SW0

SW1

To ADC o OCP InputSW_EN

PWM0H

Rev. 1.10 9 Deee 1 01 Rev. 1.10 95 Deee 1 01



ThedrivingsignalsforeachMOScontrolarefurtherlydescribedinthefollowingcontrolcircuits.

HV_S0

HV_CTL

M0

(Powe SW)

Leve

l-Shi

ft

MUX

PWM Signal (TM)

PWM Signal (TM1)

PWM Signal (TM0)

HV_S1

00

01

10

11

BZ_S0

MUX

PWM Signal (TM)

BZ_CTL

M1

M

(Buzze Dive)

Leve

l-Shi

ft

BZ_S1

PWM Signal (TM1)

PWM Signal (TM0)

00

01

10

11

LED_S0

M3

LED_CTL

(LED SW)

Leve

l-Shi

ft

MUX

PWM Signal (TM)

PWM Signal (TM1)

PWM Signal (TM0)

LED_S1

00

01

10

11

Rev. 1.10 9 Deee 1 01 Rev. 1.10 97 Deee 1 01



Leve

l-Shi

ft

MMUX

1 0

1

PWML

PWMH

1

0

DCPD_CTL0

0

PWM0L

PWM0H

DCPD_CTL1

MUX

Control RegistersThesetworegitersarecontrolregiterswhichselectthedrivingsignalforlevelshiftfunctionineachcontrolcircuitshownintheaboveblockdiagram.


Nae SW_EN — LED_S1 LED_S0 LED_CTL OCPS1 OCPS0 HV_CTLR/W R/W — R/W R/W R/W R/W R/W R/WPOR 0 — 0 0 0 0 0 1

Bit7 SE_EN:SWControl0:Disable1:Enable

Bit6 Unimplemented,readas“0”Bit5~4 LED_S1~LED_S0:ControlsignaltypeselectionforLEDenable

00:Normalsignal(High/Low)01:PWMsignalfromTM010:PWMsignalfromTM111:PWMsignalfromTM2

Whenthesebitsaresetto00,thecontrolsignalisdeterminedbytheLED_CTLbit.Bit3 LED_CTL:LEDControl

0:Off1:On

Bit2~1 OCPS1~OCPS0:OCPinputselectionDescribedelsewhere.

Bit0 HV_CTL:HighVoltageControl0:Off1:On

Rev. 1.10 9 Deee 1 01 Rev. 1.10 97 Deee 1 01




Nae — HV_S1 HV_S0 DCPD_CTL1 DCPD_CTL0 BZ_S1 BZ_S0 BZ_CTLR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6~5 HV_S1~HV_S0:ControlsignaltypeselectionforHVenable

00:Normalsignal(High/Low)01:PWMsignalfromTM010:PWMsignalfromTM111:PWMsignalfromTM2

Whenthesebitsaresetto00,thecontrolsignalisdeterminedbytheHV_CTLbit.Bit4 DCPD_CTL1:DCtoDCPWUPControl

0:PWM0Halwayshigh1:PWM0HsignalfromPWMH

Whenthisbitisclearedtozero,PWM0Hisalwayshighlevel,M4isturnedoff.Whenthisbit issethigh,M4iscontrolledbyPWM0Hwhosesignal is fromPWMH, itmeansthatM4isonlycontrolledbyTM0,itcannotuseTM1andTM2.RefertotheComplementaryPWMOutputsectionformoredetails.

Bit3 DCPD_CTL0:DCtoDCPWDNControl0:PWM0Lalwayslow1:PWM0LsignalfromPWML

Bit2~1 BZ_S1~BZ_S0:ControlsignaltypeselectionforBuzzerenable00:Normalsignal(High/Low)01:PWMsignalfromTM010:PWMsignalfromTM111:PWMsignalfromTM2

Whenthesebitsaresetto00,thecontrolsignalisdeterminedbytheBZ_CTLbit.Bit0 BZ_CTL:BuzzerControl

0:Off1:On

Rev. 1.10 98 Deee 1 01 Rev. 1.10 99 Deee 1 01



InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontroller todirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternalinterruptand internal interrupts functions.Theexternal interrupt isgeneratedby theactionoftheexternalINT0andINT1pins,while the internal interruptsaregeneratedbyvarious internalfunctionssuchastheTMs,OverCurrentProtectionfunction,TimeBase,LVD,EEPROMandtheA/Dconverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Theinterruptregistersfallintothreecategories.ThefirstistheINTC0~INTC2registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI3registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

Function Enable Bit Request Flag NotesGloal EMI — —INTn Pin INTnE INTnF n=0 o 1OCP OCPE OCPF —A/D Convete ADE ADF —Multi-funtion MFnE MFnF n=0~3Tie Base TBnE TBnF n=0 o 1LVD LVE LVF —EEPROM DEE DEF —

TMTnPE TnPF

n=0~TnAE TnAF

Interrupt Register Bit Naming Conventions

Interrupt Register ContentsName Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0INTC0 — INT0F OCPF — INT0E OCPE — EMIINTC1 MF3F MFF MF1F MF0F MF3E MFE MF1E MF0EINTC INT1F TB1F TB0F ADF INT1E TB1E TB0E ADEMFI0 — — T0AF T0PF — — T0AE T0PEMFI1 — — T1AF T1PF — — T1AE T1PEMFI — — TAF TPF — — TAE TPEMFI3 — — DEF LVF — — DEE LVE

Rev. 1.10 98 Deee 1 01 Rev. 1.10 99 Deee 1 01



INTEG Register Bit 7 6 5 4 3 2 1 0

Nae — — — — INT1S1 INT1S0 INT0S1 INT0S0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3~2 INT1S1, INT1S0:DefinesINT1interruptactiveedge

00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

Bit1~0 INT0S1, INT0S0:DefinesINT0interruptactiveedge00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

INTC0 RegisterBit 7 6 5 4 3 2 1 0

Nae — INT0F OCPF — INT0E OCPE — EMIR/W — R/W R/W — R/W R/W — R/WPOR — 0 0 — 0 0 — 0

Bit7 Unimplemented,readas“0”Bit6 INT0F:Externalinterrupt0requestflag

0:Norequest1:Interruptrequest

Bit5 OCPF:Overcurrentprotectioninterruptrequestflag0:Norequest1:Interruptrequest

Bit4 Unimplemented,readas“0”Bit3 INT0E:Externalinterrupt0control

0:Disable1:Enable

Bit2 OCPE:Overcurrentprotectioninterruptcontrol0:Disable1:Enable

Bit1 Unimplemented,readas“0”Bit0 EMI:GlobalInterruptControl

0:Disable1:Enable

Rev. 1.10 100 Deee 1 01 Rev. 1.10 101 Deee 1 01



INTC1 RegisterBit 7 6 5 4 3 2 1 0

Nae MF3F MFF MF1F MF0F MF3E MFE MF1E MF0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 MF3F:Multi-functioninterrupt3requestflag0:Norequest1:Interruptrequest




Bit3 MF3E:Multi-functioninterrupt3control0:Disable1:Enable




INTC2 Register Bit 7 6 5 4 3 2 1 0

Nae INT1F TB1F TB0F ADF INT1E TB1E TB0E ADER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 INT1F:Externalinterrupt1requestflag0:Norequest1:Interruptrequest

Bit6 TB1F:TimeBase1interruptrequestflag0:Norequest1:Interruptrequest

Bit5 TB0F:TimeBase0interruptrequestflag0:Norequest1:Interruptrequest

Bit4 ADF:A/Dconverterinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 INT1E:Externalinterrupt1control0:Disable1:Enable

Rev. 1.10 100 Deee 1 01 Rev. 1.10 101 Deee 1 01



Bit2 TB1E:TimeBase1interruptcontrol0:Disable1:Enable

Bit1 TB0E:TimeBase0interruptcontrol0:Disable1:Enable

Bit0 ADE:A/Dconverterinterruptcontrol0:Disable1:Enable

MFI0 RegisterBit 7 6 5 4 3 2 1 0

Nae — — T0AF T0PF — — T0AE T0PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas“0”Bit5 T0AF:TM0comparatorAmatchinterruptrequestflag


Bit4 T0PF:TM0comparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas“0”Bit1 T0AE:TM0comparatorAmatchinterruptcontrol

0:Disable1:Enable

Bit0 T0PE:TM0comparatorPmatchinterruptcontrol0:Disable1:Enable

MFI1 Register Bit 7 6 5 4 3 2 1 0

Nae — — T1AF T1PF — — T1AE T1PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0





0:Disable1:Enable


Rev. 1.10 10 Deee 1 01 Rev. 1.10 103 Deee 1 01




Nae — — TAF TPF — — TAE TPER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0





0:Disable1:Enable



Nae — — DEF LVF — — DEE LVER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas“0”Bit5 DEF:DataEEPROMinterruptrequestflag


Bit4 LVF:LVDinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas“0”Bit1 DEE:DataEEPROMinterruptcontrol

0:Disable1:Enable

Bit0 LVE:LVDinterruptcontrol0:Disable1:Enable

Rev. 1.10 10 Deee 1 01 Rev. 1.10 103 Deee 1 01



Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorPorComparatorAmatchorA/Dconversioncompletionetc, therelevant interruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagrams with theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

Rev. 1.10 10 Deee 1 01 Rev. 1.10 105 Deee 1 01



INT0 Pin

INT1 Pin

INT0F

INT1F

INT0E

INT1E

EMI

0H

EMI

08H

EMI

0CH

Tie Base 0 TB0F TB0E EMI

1CH

Inteupt Nae

Request Flags

Enale Bits

Maste Enale Vector

EMI auto disaled in ISR

PioityHigh

Low

TM0P T0PF T0PE

TM0A T0AF T0AE M. Funt. 0 MF0F MF0E

Inteupts ontained within Multi-Funtion Inteupts

xxE Enale Bits

xxF Request Flag auto eset in ISR

LegendxxF Request Flag no auto eset in ISR

EMI

0H

EMI

H

M. Funt. 1 MF1F MF1E

Tie Base 1 TB1F TB1E

A/D ADF ADE EMI

18HEMI

10H

LVD LVF LVE M. Funt. 3 MF3F MF3E

EEPROM DEF DEE

TM1P T1PF T1PE

TM1A T1AF T1AE

OCP OCPF OCPE EMI

8H

1HEMIM. Funt. MFF MFETMP TPF TPE

TMA TAF TAE

Interrupt Structure

External InterruptTheexternal interruptsarecontrolledbysignal transitionsonthepinsINT0~INT1.Anexternalinterruptrequestwill takeplacewhentheexternalinterruptrequestflags,INT0F~INT1F,areset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternalinterruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INT0E~INT1E,mustfirstbeset.AdditionallythecorrectinterruptedgetypemustbeselectedusingtheINTEGregistertoenabletheexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwithI/Opins, theycanonlybeconfiguredasexternal interruptpins if theirexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregisteraswellastherelevantpin-sharedfunctionselectionbits.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,will takeplace.Whentheinterruptisserviced,theexternalinterruptrequestflags,INT0F~INT1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinswillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Rev. 1.10 10 Deee 1 01 Rev. 1.10 105 Deee 1 01



OCP InterruptAnOCP interruptrequestwill takeplacewhentheOverCurrentProtectionInterruptrequestflag,OCPF, isset,whichoccurswhen theOverCurrentProtection functiondetectsanovercurrentcondition.Toallowtheprogramtobranch to its respective interruptvectoraddress, theglobalinterruptenablebit,EMI,andOverCurrentProtectionInterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheOCPInterruptvector,will takeplace.WhentheOverCurrentProtectionInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterruptsandtheinterruptrequestflagwillbealsoautomaticallycleared.

Multi-function InterruptWithinthedevicetherearefourMulti-functioninterrupts.Unliketheotherindependentinterrupts,these interruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namely theTMInterrupts,LVDInterruptandEEPROMInterrupt.AMulti-functioninterruptrequestwill takeplacewhenanyoftheMulti-functioninterruptrequestflags,MFnFareset.TheMulti-functioninterruptflagswillbesetwhenanyof their includedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-function interruptoccurs,asubroutinecall tooneof theMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhen the interrupt is serviced, the request flags from theoriginal sourceof theMulti-functioninterrupts,namelytheTMInterrupts,LVDInterruptandEEPROMInterruptwillnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

A/D Converter InterruptTheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwilltakeplacewhentheA/DConverterInterruptrequestflag,ADF,isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Rev. 1.10 10 Deee 1 01 Rev. 1.10 107 Deee 1 01



Time Base InterruptsThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall totheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TB0ForTB1F,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.TheirclocksourcesoriginatefromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.

TBC RegisterBit 7 6 5 4 3 2 1 0

Nae TBON TBCK TB11 TB10 — TB0 TB01 TB00R/W R/W R/W R/W R/W — R/W R/W R/WPOR 0 0 1 1 — 1 1 1

Bit7 TBON:TB0andTB1Controlbit0:Disable1:Enable

Bit6 TBCK:SelectfTBClock0:fTBC1:fSYS/4

Bit5~4 TB11 ~ TB10:SelectTimeBase1Time-outPeriod00:212/fTB

01:213/fTB

10:214/fTB

11:215/fTB

Bit3 Unimplemented,readas“0”Bit2~0 TB02 ~ TB00:SelectTimeBase0Time-outPeriod

000:28/fTB

001:29/fTB

010:210/fTB

011:211/fTB

100:212/fTB

101:213/fTB

110:214/fTB

111:215/fTB

Time Base Interrupt

Rev. 1.10 10 Deee 1 01 Rev. 1.10 107 Deee 1 01



EEPROM InterruptTheEEPROMinterrupt iscontainedwithintheMulti-functionInterrupt.AnEEPROMInterruptrequestwill takeplacewhen theEEPROMInterrupt request flag,DEF, is set,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchto itsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,andassociatedMulti-functioninterruptenablebit,MF3E,mustfirstbeset.Whentheinterrupt isenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveEEPROMInterruptvector,will takeplace.WhentheEEPROMInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheDEFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

LVD InterruptTheLVDinterruptiscontainedwithintheMulti-functionInterrupt.AnLVDInterruptrequestwilltakeplacewhentheLVDInterruptrequestflag,LVF,isset,whichoccurswhentheLowVoltageDetector functiondetectsa lowpower supplyvoltage.Toallow theprogram tobranch to itsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andLowVoltageInterruptenablebit,LVE,andassociatedMulti-functioninterruptenablebit,MF3E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheLVDInterruptvector,willtakeplace.WhentheLowVoltageInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheLVDinterruptrequestflag,LVF,willnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

TM InterruptsThePeriodicTypeTMseachhastwointerrupts.AlloftheTMinterruptsarecontainedwithintheMulti-functionInterrupts.ForthePeriodicTypeTMstherearetwointerruptrequestflagsTnPFandTnAFandtwoenablebitsTnPEandTnAE.ATMinterruptrequestwilltakeplacewhenanyoftheTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorPorcomparatorAmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtherespectiveTMInterruptenablebit,andassociatedMulti-functioninterruptenablebit,MFnF,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecall to therelevantTMInterruptvector locations,will takeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

Rev. 1.10 108 Deee 1 01 Rev. 1.10 109 Deee 1 01



Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpinsoralowpowersupplyvoltagemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptserviceroutineisexecuted,asonlytheMulti-functioninterruptrequestflags,MF0F~MF3F,willbeautomaticallycleared, the individualrequestflagfor thefunctionneeds tobeclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Rev. 1.10 108 Deee 1 01 Rev. 1.10 109 Deee 1 01



Low Voltage Detector – LVDThedevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenablesthedevicetomonitorthepowersupplyvoltage,VDD,andprovidesawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebitsinthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetemined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbitisusedtocontroltheoverallon/offfunctionofthelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC Register Bit 7 6 5 4 3 2 1 0

Nae — — LVDO LVDEN — VLVD VLVD1 VLVD0R/W — — R R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetect1:LowVoltageDetect

Bit4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable

Bit3 Unimplemented,readas“0”Bit2~0 VLVD2 ~ VLVD0:SelectLVDVoltage

000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V

Rev. 1.10 110 Deee 1 01 Rev. 1.10 111 Deee 1 01



LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatinga lowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,at thevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

LVD Operation

TheLowVoltageDetectoralsohasitsowninterruptwhichiscontainedwithinoneof themulti-functioninterrupts,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.Inthiscase,theLVFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPorIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPorIDLEMode.

Configuration OptionConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopment tools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. Options

Oscillator Option

1

HIRC Fequeny Seletion: 1. 0MHz. 1MHz3. 1MHz

Rev. 1.10 110 Deee 1 01 Rev. 1.10 111 Deee 1 01



Application Circuit

Emergency Light Application Circuit (LED under 0.6W)

AC Input220V

VIN

HV_IN

VSS

LED <0.6W

330Ω

HV_OUT

VIN

HV_OUT

LED_OUT

BZ

BAT_IN

PA0

PA2

HT45FH4J 16NSOP

OCP0/PA6AN0/PA1

AN1/PA3

PA4

AN3/OCP1/PA5

0.1µF

47µF/16V

0.5Ω

1.2V47µH

10ΩPWM0/PA7

HVSS

220µF

1.5kΩ

20kΩ

RCC Circuits(Output DC 7V)

HV_OUT

1.2VBattery

0.1µF

100µF

VDD4.7µF

5V

V_BAT

HV_OUT

7~12V 140mA

Reduce Standby Current Circuits

100mA

0.1µF

0.1µF20kΩ

18kΩ

100kΩ

100Ω

1MΩ

VIN

Rev. 1.10 11 Deee 1 01 Rev. 1.10 113 Deee 1 01



Emergency Light Application Circuit (LED over 1W)

AC Input220V

VIN

HV_IN

VSS

330Ω

HV_OUT

VIN

HV_OUT

BZ

BAT_IN

PA0

PA2

HT45FH4J 16NSOP

AN0/PA1

AN1/PA3

PA4

AN3/OCP1/PA5

0.1µF

100µF/16V

1.2V47µH

10ΩPWM0/PA7

HVSS

220µF

1.5kΩ

20kΩ

RCC Circuits(Output DC 7V)

HV_OUT

1.2VBattery

0.1µF

100µF

VDD4.7µF

5V

V_BAT

HV_OUT

7~12V140mA

Reduce Standby Current Circuits

0.1µF

20kΩ18kΩ

100kΩ1MΩ

VIN

LED >0.6W

LED_OUT

OCP0/PA6

0.5Ω

HV_OUT

20kΩ0.1µF100Ω

Rev. 1.10 11 Deee 1 01 Rev. 1.10 113 Deee 1 01



Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.10 11 Deee 1 01 Rev. 1.10 115 Deee 1 01



Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

Rev. 1.10 11 Deee 1 01 Rev. 1.10 115 Deee 1 01



Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A[] Add Data Meoy to ACC 1 Z C AC OVADDM A[] Add ACC to Data Meoy 1Note Z C AC OVADD Ax Add iediate data to ACC 1 Z C AC OVADC A[] Add Data Meoy to ACC with Cay 1 Z C AC OVADCM A[] Add ACC to Data eoy with Cay 1Note Z C AC OVSUB Ax Sutat iediate data fo the ACC 1 Z C AC OVSUB A[] Sutat Data Meoy fo ACC 1 Z C AC OVSUBM A[] Sutat Data Meoy fo ACC with esult in Data Meoy 1Note Z C AC OVSBC A[] Sutat Data Meoy fo ACC with Cay 1 Z C AC OVSBCM A[] Sutat Data Meoy fo ACC with Cay esult in Data Meoy 1Note Z C AC OVDAA [] Deial adjust ACC fo Addition with esult in Data Meoy 1Note CLogic OperationAND A[] Logial AND Data Meoy to ACC 1 ZOR A[] Logial OR Data Meoy to ACC 1 ZXOR A[] Logial XOR Data Meoy to ACC 1 ZANDM A[] Logial AND ACC to Data Meoy 1Note ZORM A[] Logial OR ACC to Data Meoy 1Note ZXORM A[] Logial XOR ACC to Data Meoy 1Note ZAND Ax Logial AND iediate Data to ACC 1 ZOR Ax Logial OR iediate Data to ACC 1 ZXOR Ax Logial XOR iediate Data to ACC 1 ZCPL [] Copleent Data Meoy 1Note ZCPLA [] Copleent Data Meoy with esult in ACC 1 ZIncrement & DecrementINCA [] Ineent Data Meoy with esult in ACC 1 ZINC [] Ineent Data Meoy 1Note ZDECA [] Deeent Data Meoy with esult in ACC 1 ZDEC [] Deeent Data Meoy 1Note ZRotateRRA [] Rotate Data Meoy ight with esult in ACC 1 NoneRR [] Rotate Data Meoy ight 1Note NoneRRCA [] Rotate Data Meoy ight though Cay with esult in ACC 1 CRRC [] Rotate Data Meoy ight though Cay 1Note CRLA [] Rotate Data Meoy left with esult in ACC 1 NoneRL [] Rotate Data Meoy left 1Note NoneRLCA [] Rotate Data Meoy left though Cay with esult in ACC 1 CRLC [] Rotate Data Meoy left though Cay 1Note C

Rev. 1.10 11 Deee 1 01 Rev. 1.10 117 Deee 1 01



Mnemonic Description Cycles Flag AffectedData MoveMOV A[] Move Data Meoy to ACC 1 NoneMOV []A Move ACC to Data Meoy 1Note NoneMOV Ax Move iediate data to ACC 1 NoneBit OperationCLR [].i Clea it of Data Meoy 1Note NoneSET [].i Set it of Data Meoy 1Note NoneBranchJMP add Jup unonditionally NoneSZ [] Skip if Data Meoy is zeo 1Note NoneSZA [] Skip if Data Meoy is zeo with data oveent to ACC 1Note NoneSZ [].i Skip if it i of Data Meoy is zeo 1Note NoneSNZ [].i Skip if it i of Data Meoy is not zeo 1Note NoneSIZ [] Skip if ineent Data Meoy is zeo 1Note NoneSDZ [] Skip if deeent Data Meoy is zeo 1Note NoneSIZA [] Skip if ineent Data Meoy is zeo with esult in ACC 1Note NoneSDZA [] Skip if deeent Data Meoy is zeo with esult in ACC 1Note NoneCALL add Suoutine all NoneRET Retun fo suoutine NoneRET Ax Retun fo suoutine and load iediate data to ACC NoneRETI Retun fo inteupt NoneTable ReadTABRD [] Read table (specific page) to TBLH and Data Memory Note NoneTABRDC [] Read tale (uent page) to TBLH and Data Meoy Note NoneTABRDL [] Read tale (last page) to TBLH and Data Meoy Note NoneMiscellaneousNOP No opeation 1 NoneCLR [] Clea Data Meoy 1Note NoneSET [] Set Data Meoy 1Note NoneCLR WDT Clea Wathdog Tie 1 TO PDFCLR WDT1 Pe-lea Wathdog Tie 1 TO PDFCLR WDT Pe-lea Wathdog Tie 1 TO PDFSWAP [] Swap niles of Data Meoy 1Note NoneSWAPA [] Swap niles of Data Meoy with esult in ACC 1 NoneHALT Ente powe down ode 1 TO PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the"CLRWDT1"and"CLRWDT2"instructions theTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDF flagsareclearedafterboth "CLRWDT1"and"CLRWDT2"instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

Rev. 1.10 11 Deee 1 01 Rev. 1.10 117 Deee 1 01



Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

Rev. 1.10 118 Deee 1 01 Rev. 1.10 119 Deee 1 01



CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

Rev. 1.10 118 Deee 1 01 Rev. 1.10 119 Deee 1 01



CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

Rev. 1.10 10 Deee 1 01 Rev. 1.10 11 Deee 1 01



JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

Rev. 1.10 10 Deee 1 01 Rev. 1.10 11 Deee 1 01



RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

Rev. 1.10 1 Deee 1 01 Rev. 1.10 13 Deee 1 01



RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

Rev. 1.10 1 Deee 1 01 Rev. 1.10 13 Deee 1 01



SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

Rev. 1.10 1 Deee 1 01 Rev. 1.10 15 Deee 1 01



SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

Rev. 1.10 1 Deee 1 01 Rev. 1.10 15 Deee 1 01



TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

Rev. 1.10 1 Deee 1 01 Rev. 1.10 17 Deee 1 01



Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• TheOperationInstructionofPackingMaterials

• Cartoninformation

http://www.holtek.com/en

http://www.holtek.com/en/package_carton_information

Rev. 1.10 1 Deee 1 01 Rev. 1.10 17 Deee 1 01



16-pin NSOP (150mil) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max.A — 0.3 BSC —

B — 0.15 BSC —

C 0.01 — 0.00C’ — 0.390 BSC —D — — 0.09E — 0.050 BSC —F 0.00 — 0.010G 0.01 — 0.050H 0.00 — 0.010α 0° — 8°

SymbolDimensions in mm

Min. Nom. Max.A — BSC —B — 3.9 BSC —C 0.31 — 0.51C’ — 9.9 BSC —D — — 1.75E — 1.7 BSC —F 0.10 — 0.5G 0.0 — 1.7H 0.10 — 0.5α 0° — 8°

Rev. 1.10 18 Deee 1 01 Rev. 1.10 19 Deee 1 01



20-pin SSOP (150mil) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max.A — 0.3 BSC —

B — 0.155 BSC —

C 0.008 — 0.01

C’ — 0.31 BSC —

D — — 0.09

E — 0.05 BSC —

F 0.00 — 0.0098

G 0.01 — 0.05

H 0.00 — 0.01

α 0° ― 8°

SymbolDimensions in mm

Min. Nom. Max.A — BSC —

B — 3.9 BSC —

C 0.0 — 0.30

C‘ — 8. BSC —

D — — 1.75

E — 0.35 BSC —

F 0.10 — 0.5

G 0.1 — 1.7

H 0.10 — 0.5

α 0° ― 8°

Rev. 1.10 18 Deee 1 01 Rev. 1.10 19 Deee 1 01



Copyight© 01 y HOLTEK SEMICONDUCTOR INC.

The infoation appeaing in this Data Sheet is elieved to e auate at the tie of puliation. Howeve Holtek assues no esponsiility aising fo the use of the specifications described. The applications mentioned herein are used solely fo the pupose of illustation and Holtek akes no waanty o epesentation that suh appliations will e suitale without futhe odifiation no eoends the use of its poduts fo appliation that ay pesent a isk to huan life due to alfuntion o othewise. Holtek's poduts ae not authoized fo use as itial oponents in life suppot devies o systes. Holtek eseves the ight to alte its products without prior notification. For the most up-to-date information, please visit ou we site at http://www.holtek.o.tw.

Documents

Emergency Light Flash MCU · PWM outputs with a dead time insertion, are used to drive an internal PMOS transistor and an external NMOS transistor to implement the synchronous rectification