POWER ANALYSIS OF D FLIP-FLOP USING LEAKAGE ...M2 is o , pull-down path is disabled and static current will not ow in the circuit. When s=1, PMOS transistor M1 is o and NMOS transistor

POWER ANALYSIS OF D FLIP-FLOPUSING LEAKAGE REDUCTION

TECHNIQUE

Ayesha Firdous1, Dr.M.Anand2,A.Mohammed Ishak3,

1Research Scholar, 2Professor,ECE Department,

Dr. M.G.R. Educational and Research Institute3Assistant Professor,ECE Department,

Saveetha School of Engineering

July 8, 2018

Abstract

The fast advance in semiconductor innovation hasdriven the element sizes to be contracted using profoundsubmicron forms; along these lines, the amazingly complexusefulness is empowered to be incorporated on a solitarychip. In the developing business sector of versatilehand-held gadgets utilized everywhere throughout theworld today, the battery controlled electronic frameworkshapes the spine. With scaling down and the developingpattern towards remote correspondence, control scatteringhas turned into an extremely basic outline metric. Themore extended the battery keeps going, the better is thegadget. Power reduction in CMOS circuit is achieved bycombining two leakage reduction techniques Sleep modeapproach with LECTOR technique and the simulation iscarried out with and without power reduction techniqueusing microwind DSCH software. This leakage power

1

International Journal of Pure and Applied MathematicsVolume 120 No. 6 2018, 2487-2508ISSN: 1314-3395 (on-line version)url: http://www.acadpubl.eu/hub/Special Issue http://www.acadpubl.eu/hub/

2487

reduction technique is applied to design D flip-flop and theperformance and power consumption was measured. Theresults clearly provide the data that the power has beenreduced drastically.

Keywords: LECTOR, sleep transistor, D flip-flop,Leakage power

1 INTRODUCTION

In this modern world, due to advancement of battery-baseddevices with limited power capabilities needs major requirementof power efficiency and power-delay product. These two factorsare of great challenge to the electronic designers. Similarly, inVLSI circuit design power consumption of circuit is of majorconcern. The demand for low power device is not because ofdevelopment of mobile application alone. The problem of powerconsumption is major issue before the evolution of mobile era. Toresolve power dissipation issue numerous techniques and methodshas been proposed by researchers in terms of architectural, devicelevel and even some higher levels. Till today there is not standardapproach is evolved for factors to overcome problem of areaconsumption, delay and power utilization of the designed circuit.Based on the product and the application requirements the userneeds to select most appropriate technique. In case of highperformance portable devices power dissipation is the majorconcern. Three components in the circuit plays a vital role forpower consumption which are all leakage current, short circuitand dissipation of power from dynamic switching. In CMOScircuit total power dissipation becomes a dominant componentbecause of continuous scaling of threshold voltage. Through therecycling of stored energy in the nodes dynamic dissipation getsreduced in adiabatic computing. Even in adiabatic processdissipation of energy occurred for constant input values. However,energy dissipation occurs even for constant input signals of theadiabatic circuits where power clocks are used for charging anddischarging of output nodes. Due to continuous scaling in CMOStechnology in adiabatic process dissipation, leakage in the circuitdesign will perform as dominant component for overall dissipationof power same as traditional logic function of the CMOS devices.

2

International Journal of Pure and Applied Mathematics Special Issue

2488

In adiabatic circuit power gating approach is adopted forminimizing leakage and dynamic power of the system. In thistechnique at idle state power gating system shut down the units.The adiabatic circuit is significantly differing from CMOS circuitdue to signal waveforms and clocking schemes in conventionalapproaches. In this scheme it is necessary that their need to beenough distinguish between switch with Power-gating and powerclock utilized for turning-off. In adiabatic schemes various powergating are applied. Among the numerous gating approachesvoltage scaling approach outperforms in case of adiabatic basedCMOS logic circuits. In the mid performance ranges from (5MHzto 100MHz) supply voltage scaling in medium-voltage regionperforms effectively. Based on this numerous adiabatic circuitwith near-threshold has been proposed without the use of gatingpower. Switching power dissipation is minimized to quadratic inthis scenario minimization of power consumption by the use ofsupply voltage technique. This technique has the serious issues ofperformance degradation. Subsequently, the high performancerequirements were fulfilled by scaled value of threshold voltage.But this technique has the serious drawback of increased leakagecurrent which put forth the major concern for high performancecircuit with low power utilization.

2 VARIOUS TECHNIQUES TO

REDUCE LEAKAGE POWER

In this section various leakage reduction techniques are summarized.Each practice provides a proficient way to decrease leakage power

2.1 Sleep Transistor Technique

This is a State-ruinous method which cuts off either pull-up orpull-down or both the systems from supply voltage or ground orboth utilizing rest transistors. This procedure includes high-Vthrest transistors between pull-up systems and Vdd and pull-downsystems and gnd while for quick exchanging speeds, low-Vthtransistors are utilized as a part of rationale circuits discussed inPowell et al. (2000). Secluding the rationale arranges, this

3


2489

method significantly diminishes spillage control amid rest mode.Be that as it may, the range and deferral are expanded because ofextra rest transistors. Amid the rest mode, the state will be lostas the pull-up and pull-down systems will have drifting esteems.These qualities affect the wake-up time and vitality fundamentallybecause of the prerequisite to energize transistors which lost stateamid rest.

2.2 Forced Stack

In this method, each transistor in the system is copied with boththe transistors bearing a large portion of the first transistor widthis said by Deepak Subramanyan and Nunez (2007). Copiedtransistors cause a slight invert predisposition between the gateand source when the two transistors are killed. Since asubthreshold current is exponentially subject to gate inclination,it acquires significant current decrease. It beats the constraintwith rest system by holding state however it requires morewake-up investment.

2.3 Dual Vt Technique

Dual Vt was the most punctual recommended system to diminishthe spillage control. Dual Vt method is a variety in MTCMOS, inwhich low threshold voltage and high threshold voltage gates areused in critical and non critical path respectively. Both thetechniques require extra cover layers for each estimation of Vt increation, which is a muddled assignment storing two distinctoxides thickness, consequently making the manufacture procedurecomplex. In addition, the systems additionally experience the illeffects of turning on idleness i.e., the sit out of gear circuit can’tbe utilized promptly after reactivated since some time is expectedto come back to ordinary working condition.

The inertness is commonly a couple of cycles for the previousstrategy, and for Dual innovation, is significantly higher. At thepoint when the circuit is dynamic, these systems are not viable incontrolling the spillage control.

4


2490

2.4 LECTOR Technique

This is one of the low power maintenance strategies. This methodproposed a CMOS circuit in which two additional LeakageControl Transistors are embedded, in which the gate terminal ofevery Leakage Control Transistor is controlled by the wellspring ofthe other. The circuit can be seen in the Fig. 1 given below

Figure 1: LECTOR circuit design

The fundamental thought behind this approach was for thedecrease of spillage control is the powerful stacking of transistorsin the way from the supply voltage to ground. It is watched that“a state with more than one transistor OFF in a way from asupply voltage to ground is far less flawed than a state with just asingle transistor OFF in any supply to the ground way”. In theirtechnique, they presented two spillage control transistors (LCTs)in each CMOS gate to such an extent that one of the LCTs isclose to its cutoff area of operation.

5


2491

3 COMBINED EFFECT OF SLEEP

MODE APPROACH AND

LECTOR TECHNIQUE FOR

REDUCING LEAKAGE POWER

The power consumption could be migrated at different levels suchas Layout level, Circuit Level, Architectural level and FabricationProcess Technology Level. The significant method to minimizethe level of power usage is to disable part of the circuit when thepart is not under operation. By reducing the switching activity ofa circuit, the power dissipation could be minimized. Variousmethods are used to optimize the power such as MTCMOS, Bodybiasing, Sleep, Zigzag, Leakage Feedback Approach, DualThreshold Transistor Stacking, etc., In addition consumption ofpower in the circuit is data dependent. In this section powerreduction is achieved by combining two leakage reductiontechniques and the simulation is carried out with and withoutpower reduction technique using microwind and DSCH software.

In sleep mode approach, PMOS transistor is placed betweensupply voltage to pull up network and NMOS transistor is placedin between pull down network and GND. Sleep transistor is turnedon when the circuit is in active mode. Sleep transistor is turnedoff when it is in standby mode. To prevent high leakage currentthreshold voltage of sleep transistor is kept high. Fig. 2 shows theblock diagram of sleep mode approach. The proposed work takes anadvantage of sleep mode approach. Number of transistor needed todesign a circuit in this approach is 2+2N. Where, N is the numberof transistor. Compare to CMOS technology, sleep mode approachuses two more transistors in addition to the normal circuit.

The noteworthy feature of LECTOR is that it works well inboth active and idle states of the circuit, this leads in betterleakage reduction. In this approach NMOS and PMOS transistorsare added in between pull up network and pull down network.Gate terminal of PMOS, NMOS transistors are controlled bysource of the other. LECTOR method is more effective in bothactive and standby mode. The block diagram of LECTORapproach is shown in Fig. 3.

In the proposed circuit (Fig. 4), when s=0, NMOS transistor

6


2492

Figure 2: Sleep Mode Approach

Figure 3: LECTOR Approach

7


2493

M2 is off, pull-down path is disabled and static current will not flowin the circuit. When s=1, PMOS transistor M1 is off and NMOStransistor M2 is turned on. Based on the input values and pulldown topology circuit output is conditionally discharged. LCT1and LCT2 are Leakage control transistors it is controlled by sourceof the other. This ensures that one of the Leakage control transistoralways operates in its near cut-off region. From supply voltage toground, if more than one transistor is OFF in a path the leakagecurrent of the circuit will be less compare to only one transistorOFF in the path from supply to ground.

Figure 4: Sleep mode with LECTOR circuit

4 D FLIP-FLOP DESIGN

4.1 D flip-flop without sleep transistors

D flip-flop is used as a delay element. In this section D flip-flop isdesigned using conventional method. The design is implemented inDSCH software. Using two inputs CMOS NAND gate the circuitis designed. Fig.5 shows the D flip-flop implementation in DSCH

8


2494

software. Fig. 6 shows the layout diagram of D flip-flop withoutsleep transistors.

Figure 5: D flip-flop without sleep transistors

Figure 6: Layout diagram of D flip-flop without sleep transistors

9


2495

4.2 D flip-flop with Sleep Transistors

Two input CMOS NAND gate is designed using sleep modeapproach and it is used to implement D flip-flop. Fig 4.13 showsimplementation of D flip-flop with Sleep Transistors. Fig 4.14shows the layout diagram of D flip-flop with Sleep Transistors.

Figure 7: D flip-flop with Sleep Transistors

Figure 8: Layout diagram of D flip-flop with Sleep Transistors

10


2496

4.3 D flip-flop with LECTOR Configuration

LECTOR configuration is used to design D flip-flop for this twoinput NAND gate is designed by LECTOR approach. Fig 4.15shows D flip-flop with LECTOR configuration the implementationin DSCH software. Fig 4.16 shows layout diagram of D flip-flopwith LECTOR configuration

Figure 9: D flip-flop with LECTOR configuration

4.4 Proposed D flip-flop

Two leakage current techniques sleep mode approach andLECTROR approach are combined to design D flip-flop. Fig. 11shows proposed D flip-flop implementation in DSCH software.Fig. 12 shows layout diagram of proposed D flip-flop

11


2497

Figure 10: Layout diagram of D flip-flop with LECTORconfiguration

Figure 11: Proposed D flip-flop

12


2498

Figure 12: Layout diagram of proposed D flip-flop

5 RESULTS

5.1 Power consumption analysis of D flip-flopfor various configurations

Figure 13: Power consumption analysis of D flip-flop with No SleepTransistors

13


2499

Figure 14: Power consumption analysis of D flip-flop with SleepTransistors

Figure 15: Power consumption analysis of D flip-flop with LECTORConfiguration

14


2500

Figure 16: Power consumption analysis of D flip-flop of proposedcircuit

15


2501

Figure 17: Power consumption of D flip-flop with differenttechnologies

From the experimental evaluation the power reductiontechnique for VLSI circuits is verified as efficient. D flip-flop isdesigned using the leakage reduction technique. The experimentalresults show the proposed circuit provides a better solution forleakage reduction.

References

[1] Ajay Kumar Dadoria & Kavita Khare 2014, “A novel approachfor leakage power reduction techniques in 65nm technologies”,International Journal of VLSI design & CommunicationSystems, vol. 5, no. 3, pp. 1-11

[2] Akanksha Dixit 2016, “Transistor Leakage Mechanisms andPower Reduction Techniques in CMOS VLSI Design”,International Journal of Advanced Research in Computer andCommunication Engineering, vol. 5, no. 3, pp. 102-107

[3] Akhila Abba & Amarender, K 2014, “Improved Power GatingTechnique for Leakage Power Reduction”, InternationalJournal Of Engineering And Science, vol. 4, no. 10, pp. 6-10

16


2502

[4] Aruljothi, K, Prajitha, PB & Rajaprabha, R 2014,“Leakage Power Reduction Using Power Gating And Multi-Vt Technique”, International Journal of Advanced Researchin Computer Engineering & Technology, vol. 3, no. 1, pp. 12-19

[5] Ayesha Firdous, Anand, M & Saravana Kumar, G 2017,“Combined Effect of Sleep Mode Approach And LECTORTechnique For Reducing Leakage Power”, InternationalJournal of Control Theory and Applications, vol. 10, no. 30,pp. 135-141

[6] Benini, L, Bogliolo, A & De Micheli, G 2000, “Asurvey of design techniques for system-level dynamic powermanagement”, IEEE Transactions on Very Large ScaleIntegration Systems, vol. 8, no. 3, pp. 299-316

[7] Bhasker, J 1988, “Implementation of an optimizing compilerfor VHDL”, ACM SIGPLAN Notices, vol. 23, no. 1, pp. 92-108

[8] Bollen, MHJ, Ribeiro, P, Gu, IYH & Duque, CA 2010,“Trends, challenges and opportunities in power qualityresearch”, European Transactions on Electrical Power, vol. 20,no. 1, pp. 3-18

[9] Chattopadhyay, A, Kammler, D, Witte, EM, Schliebusch,O, Ishebabi, H, Geukes, B et al. 2006, in Proceedings ofthe International Symposium on VLSI Design, Automationand Test, April 26-28, Automatic Low Power OptIimizationsduring ADL-driven ASIP Design, Hsinchu

[10] Chen, RY, Irwin, MJ & Bajwa, RS 2001, “Architecture-levelpower estimation and design experiments”, ACM Transactionson Design Automation of Electronic Systems, vol. 6, no. 1, pp.50-66

[11] Danielsson, PE 1984, “Serial/parallel convolvers”, IEEETransactions on Computers, vol. 33, no. 7, pp. 652-667

[12] Das Gautam, G, Akashe, S & Sharma, S 2011, “TransistorSizing for Low Power Cmos Circuits”, International Journal ofPower Elecronics and Technology, vol. 1, no. 1, pp. 37-59

17


2503

[13] Deepak Subramanyan, BS & Nunez, A 2007, in Proceedings ofthe 2007 50th Midwest Symposium on Circuits and Systems,August 5-8, Analysis of subthreshold leakage reduction inCMOS digital circuits, Montreal

[14] Dhiman, G & Rosing, TS 2006, in Proceedings of the2006 IEEE/ACM international conference on Computer-aideddesign, November 5-9, Dynamic power management usingmachine learning, New York

[15] Dilip, B & Surya Prasad, P 2012, “Design of Leakage PowerReduced Static RAM using LECTOR”, International Journalof Computer Science and Information Technologies, vol. 3, no.3, pp. 4127-4130

[16] Dufour, C, Cense, S, Jalili-Marandi, V & Belanger, J 2013,in Proceedings of the 15th European Conference on PowerElectronics and Applications , September 2-6, Review of state-of-the-art solver solutions for HIL simulation of power systems,power electronic and motor drives, Lille

[17] Faruque, MDO, Strasser, T, Lauss, G, Jalili-Marandi, V,Forsyth, P, Dufour, C et al. 2015, “Real-Time SimulationTechnologies for Power Systems Design, Testingand Analysis”,IEEE Power and Energy Technology Systems Journal, vol. 2,no. 2, pp. 63-73

[18] Gerez, SH 1999, Algorithms for VLSI Design Automation, 1stedn, John Wiley & Sons, New York

[19] Grailoo, M, Nikoubin, T & Navi, K 2009, “EnergyConsumption Optimization for Basic Arithmetic Circuits withTransistor Sizing Based on Genetic Algorithm”, InternationalJournal of Recent Trends in Engineering, vol. 1, no. 1, pp.425-429

[20] Hosny, MS & Yuejian, W 2008, in Proceedings of the 2008IEEE International Conference on Integrated Circuit Designand Technology and Tutorial, June 2-4, Low power clockingstrategies in deep submicron technologies, Austin

18


2504

[21] Iqbal, SMA, Mekhilef, S, Soin, N & Omar, R 2011, inProceedings of theInternational Conference and Seminar onMicro/Nanotechnologies and Electron Devices,June 30 - July4, Buck and boost converter design optimization parametersin modern VLSI technology, Erlagol

[22] Kamaraju, M, Lal Kishore, K & Tilak, AVN 2010,“Power Optimized Programmable Embedded Controller”,International Journal of Computer Networks &Communications, vol. 2, no. 4, pp. 97-107

[23] Kamaruzzaman, MD & Soumitra Kumar Mandal 2016, “ANovel Approach For Leakage Power Reduction Techniques InCMOS VLSI Circuits”, International Journal of IndustrialElectronics and Electrical Engineering, vol. 4, no. 8, pp. 6-10

[24] Kaushik, PG, Gulhane, SM & Athar Ravish Khan2013, “Dynamic Power Reduction of Digital Circuits byClock Gating”, International Journal of Advancements inTechnology, vol. 4, no. 1, pp. 79-88

[25] Kavali, K, Rajendar, S & Naresh, R 2015, in Proceedingsof the 2nd International Conference on Nanomaterial’s andTechnologies, October 17-18, The design of Low PowerAdaptive Pulse Triggered Flip-Flop Using Modified ClockGating Schemeat 90nm Technology, Hyderabad

[26] Kim, S, Kosonocky, S & Knebel, D 2003, in Proceedings ofthe 2003 International Symposium on Low Power Electronicsand Design, August 27, Understanding and minimizing groundbounce during mode transition of power gating structures,Seoul

[27] Lajolo, M, Raghunathan, A, Dey, S & Lavagno, L 2002,“Costimulation-based power estimation for system-on-chipdesign”, IEEE Transactions on Very Large Scale Integration,vol. 10, no. 3, pp. 253-265

[28] Li-ChuanWeng, Xiao Jun Wang & Bin Liu 2003, inProceedings of the 3rd IEEE International Workshop onSystem-on-Chip for Real-Time Applications, June 30 - July 2,A survey of dynamic power optimization techniques, Canada

19


2505

[29] Lim, Y & Liu, B 1992, “Pipelined recursive filter withminimum order augmentation”, IEEE Transactions on SignalProcessing, vol. 40, no. 7, pp. 1643-1651

[30] Loomis, HH & Sinha, B 1984, “High-speed recursive digitalfilter realization”, Circuits, Systems and Signal Processing, vol.3, pp. 267-294

[31] Luk, W & Jones, G 1988, “Systolic recursive filters”, IEEETransactions on Circuits and Systems, vol. 35, no. 8, pp. 1067-1068

[32] Mahalingam, V & Ranganathan, N 2005, in Proceedings ofthe IEEE Computer Society Annual Symposium on VLSI:New Frontiers in VLSI Design, May 11-12, A nonlinearprogramming based power optimization methodology for gatesizing and voltage selection, Tampa

[33] Manolakis, DG & Proakis, JG 1992, Digital Signal Processing:Principles, Algorithms, and Applications, 4th edn, MacmillanPublishing Company, Indianapolis

[34] Mrazek, V & Vasicek, Z 2015, in Proceedings of the IEEE13th International Conference on Embedded and UbiquitousComputing, October 21-23, Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers,Portugal

[35] Muchnick, SS 1997, Advanced Compiler Design andImplementation, 1st edn, Elsevier Science & Technology, SanFrancisco

[36] Mutoh, S, Douseki, T, Matsuya, Y, Aoki, T, Shigematsu, S& Yamada, J 1995, “1-V Power Supply High-Speed DigitalCircuit Technology”, IEEE Journal of Solid-State Circuits, vol.30, no. 8, pp. 847-854

[37] Narender Hanchate & Nagaranjan Ranganathan 2004,“LECTOR: A technique for leakage reduction in CMOScircuits”, IEEE transactions on VLSI systems, vol. 2, no. 2,pp. 196-200

20


2506

[38] Oklobdzija, VG, Stojanovic, VM, Markovic, DM & Nedovic,NM 2003, Digital System Clocking High-Performance andLow-Power Aspects, 1st edn, Wiley Interscience and IEEEPress, New Jersy

[39] Pardhi, AW & Deshmukh, AY 2012, “Design of FoldedCascode Operational Amplifier with Power Optimization usingGeometric Programming”, International Journal of ElectronicsCommunication and Computer Engineering, vol. 3, no. 3, pp.406-409

[40] Parhi, KK 1999, VLSI Digital Signal Processing System Designand Implementation, 1st edn, John Wiley & Sons, New York

[41] Rogenmoser, R & Kaeslin, H 1997, “The impact of transistorsizing on power efficiency in submicron CMOS circuits”, IEEEJournal of Solid-State Circuits, vol. 32, no. 7, pp. 1142-1145

[42] Snider, G, Shackleford, B & Carter, RJ 2001, in Proceedingsof the 2001 ACM/SIGDA ninth international symposium onField programmable gate arrays, February 11-13, Attackingthe semantic gap between application programming languagesand configurable hardware, Monterey

[43] Soteriou, V & Li Shiuan Peh 2003, in Proceedings of the 11thSymposium on High Performance Interconnects, August 20-22, Dynamic power management for power optimization ofinterconnection networks using on/off links, Stanford

[44] Srinivasan, K, Telkar, N, Ramamurthi, V & Chatha, KS2004, in Proceedings of the IEEE Computer Society AnnualSymposium on VLSI, February 19-20, System-level DesignTechniques for Throughput and Power Optimization ofMultiprocessor SoC Architectures.

[45] Lafayette Sumita Gupta & Sukanya Padave 2016, “PowerOptimization for Low Power VLSI Circuits”, InternationalJournal of Advanced Research in Computer Science andSoftware Engineering, vol. 6, no. 3, pp. 96-99

21


2507

2508

Documents

POWER ANALYSIS OF D FLIP-FLOP USING LEAKAGE ...M2 is o , pull-down path is disabled and static current will not ow in the circuit. When s=1, PMOS transistor M1 is o and NMOS transistor