Upload
dinhdan
View
219
Download
4
Embed Size (px)
Citation preview
Embedded Packaging Technology –
The Opportunities and Challenges
Huili FU Chief IC Packaging Expert, Hisilicon
The Driving Force for
Embedded Pkg Technologies
Driving Force
Embedded packaging?
From system point of view, all
(almost) packages are embedded
packages
Why we need to re-address the
embedded packaging
technologies ?
D3 D2 D1
FCCSP
WBPBGA
SiP
Fan-out
Sub-Embedded (TDK)
FCBGA
Fan-out 2.5D
Driving Force
The scale gap
1
0.62
0.39
0.25 0.23 0.15
0
0.2
0.4
0.6
0.8
1
1.2
65nm 40nm 28nm 20nm 16nm 10nm
Ch
ip S
ize
Sc
ali
ng
0
5
10
15
20
25
2009 2010 2011 2012 2013 2014 2015 2016
Su
bst
rate
Lin
e W
idth(
um)
MP
R&D
0
50
100
150
200
250
2009 2010 2011 2012 2013 2014 2015 2016
Bu
mp
Pit
ch(
um)
Solder
bumpCu-
pillar
Assembly bump pitch
Substrate Line/Space Progress
Wafer scale shrinkage
With the wafer process progress, the gap between
the nano-world and reality increasing.
Driving Force
The space budget (Margin)
Space margin needed separately for front-end and back-end for
traditional business model
No more DOUBLE space margins for due to system integration
density demand
Embedded packaging technologies is to solve the space
margin problem
System integration density demand / space margin drives
embedded technologies
Space budget is the key driver. Embedded technologies is the
one but not the only one to solve the problem.
Driving Force
Low power
Shorter interconnections leads to low power
Power supply efficiency improves
EMI noise reduction
Conformal shielding with zero footprint increase
Highly integrated compartment shielding for mixed digital and RF
applications
Performance improvement is the demand for the adoption of the
embedded technologies.
Embedded technologies with EMI coating
show better EMI performance
1
SPEC
SPEC
Shorter interconnections improve the
PMU efficient
Embedded Opportunities and
Challenges
Fan-out
Opportunities
Inherently embedded solution – bridge the
scale gap
Multi-die integration
Heterogeneous integration
Time to market
Yield improvement (by die partition)
Single Die Fan-out PKG
Fan-out 2.5D PKG
Die C Die B Die A
3D Fan-out PKG
Die A Die B
Fan-out 2.5D PKG
Fan-out
Challenges
Mid-end manufacturing capability
Warpage control
Fine/line space (for die to die interconnection)
Cost and Yield
Accurate patterning (for fine pitch layout in
wafer/panel level operation)
Reliability (board level) Fine line interconnection
(L/S 2/2um)
Wafer level warpage control Fine line strength
Fan-out
Application considerations
Mobile/IoT
Multi-function integration: PMIC/RF/BB/AP/Connectivity (Single
die or SIP)
Small form factor (Thinner and smaller)
Engineering issues: package strength, board level reliability
Cost competitiveness
Networking/CPU
Heterogeneous dies integration: server + memory: die partition
Large package size
Fine line space
Thermal and reliability issue
Cost benefit
Substrate Embedded Pkg
Opportunities
Small form factor
Low profile (Si thickness down to 50um)
Sub-system / small system integration
(including discrete components)
Better performance
Multi-Die embedded technology combine
with conventional DB process lead to
various sub-system in SIP format Embedding IC saves PCB area up to 38%
compare to High-density PCBA
Ultra thin IC
(Die grinding down to 50um)
50um
IC Die
Substrate Embedded Pkg
Challenges
High-density substrate implementation
Process & material
Reliability (Moisture, Delam)
Yield / cost
Resin Film Void between Die and
polymer layer
50.8um
All the defect in the substrate process will
introduce yield loss
High-density substrate can not be used here
L/S: 50um/50um
Substrate Embedded Pkg
Application considerations
Mobile/IoT
PMIC/RF/BB/Connectivity (Single die or SIP)
Small form factor (Thinner and smaller)
Engineering issues: substrate process and chip compatibility
Cost competitiveness
High-density substrate technology
Opportunities
Existing assembly process
Panel/strip level technology for low cost
Known-good-substrate assembly for better yield
Better reliability
High-density substrate development
Panel level vs. wafer level for low cost
AOI & ICT test for KGS assembly
2/2 um
15/15
High-density substrate technology
Challenges
Thickness--difficult to implement very thin sub.
Fine line assembly
Large panel & fine pitch manufacturing
Fine pitch manufacturing environment control
ELK stress issue
Foreign material introduced short/open
testing failed in high-density substrate
DoE for different combination DoE1 DoE2 DoE3 DoE4
ELK stress on bump top ratio @DB 1X 1.03X 1.06X 1.2X
Bump stress ratio @ DB 1X 1.06X 1.08X 1.24X
Die corner stress ratio @ TCT 1X 1.02X 1.04X 1.18X
Bump stress ratio @ TCT 1X 1.01X 1.05X 1.19X
Structure and Material combination used for fine pitch
substrate prone to larger stress problem
DOE1: Structure and Material combination for L/S 15/15
DOE2: Structure and Material combination for L/S 7/7
DOE3: Structure and Material combination for L/S 5/5
DOE4: Structure and Material combination for L/S 2/2
Bump bridge
in fine line substrate assembly
High-density substrate technology
Application considerations
Mobile/IoT
Multi-function integration: PMIC/RF/BB/AP/Connectivity (Single
die or SIP)
Small form factor (smaller and relatively thin)
Engineering issue: ELK stress
Cost competitiveness
Networking/CPU
Heterogeneous dies integration: server + memory; die partition
Large package size and warpage control
Cost benefit
Concluding Remarks
Concluding Remarks
From system point of view, (almost) all packages are embedded
packages
With the evolution of wafer process, the gap between wafer nano-
scale and reality increases, bring huge challenges to IC
packaging technology
Space budget is key demand. Embedded is one but not the only
one to solve the space budget problem.
In the era beyond Moore's law, embedded package technologies
will be an important way to extend the Moore's law in the package
level
Thank You ---
QUESTIONS?