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Electrical Power and Energy Systems

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LVRT capability enhancement of DFIG-based wind farms by using capacitiveDC reactor-type fault current limiter

Hossein Shahbabaei Kartijkolaiea, Masoud Radmehra,⁎, Mehdi Firouzib

a Department of Electrical Engineering, Aliabad Katoul Branch, Islamic Azad University, Aliabad Katoul, IranbDepartment of Electrical Engineering, Abhar Branch, Islamic Azad University, Abhar, Iran

A R T I C L E I N F O

Keywords:Low-voltage ride-through (LVRT)Capacitive DC reactor-type fault current limiter(CDRFCL)Doubly-fed induction generator (DFIG)

A B S T R A C T

Low-voltage ride-through (LVRT) is the core of grid code requirements for grid connection of wind farms (WFs).This paper presents a capacitive DC reactor-type fault current limiter (CDRFCL) for LVRT capability enhance-ment of doubly-fed induction generator (DFIG)-based WFs. The CDRFCL is based on the conventional DC reactor-type fault current limiter (DRFCL), which is modified to overcome its limitations of operation and is adaptedwith the WF environment. To check the effectiveness of the proposed CDRFCL, its performance is compared withthe series dynamic braking resistor (SDBR). The WF is modeled with equivalent aggregated DFIG. The PSCAD/EMTDC simulation results show that the CDRFCL is an effective solution for enhancement of LVRT capability andlimitation of fault current contribution (FCC) of WFs.

1. Introduction

Due to increased penetration level of wind power into powersystem, grid code concerns have altered from the power quality issuesof wind farms (WFs) to stability issues [1]. Generally, the squirrel-cageinduction generator (SCIG) and doubly-fed induction generator (DFIG)-based wind turbines (WTs) are utilized in WFs [1,2]. At present, DFIG-based WTs are widely utilized for WFs due to high efficiency and outputpower, light weight, good speed control and capability of decoupledcontrol of active and reactive powers. However, they are more vul-nerable to grid connecting point (GCP) voltage sag due to direct con-nection of the DFIG stator windings to grid and partial capacity of therotor-side converter (RSC) and the grid-side converter (GSC). Voltagesag at the GCP of WFs results in high rotor over currents at the be-ginning and end of the fault period and a DC-link over voltage duringfault period. It may damage the RSC of the DFIG and cause the WF trip,despite of the low-voltage ride-through (LVRT) requirements. Based onthe LVRT requirement, WFs must remain connected to grid during faultconditions. In addition, WFs have to provide reactive power to con-tribute the GCP voltage recovery after fault clearance. The technicaldevelopments in response to the LVRT requirements of DFIG-based WTsare classified in two modified control system of the DFIG and auxiliaryhardware application. The control-based solutions have drawn moreattention in recent years [5–11]. Several studies have been proposedthe modified control methods such as: demagnetization current method[5,6], virtual damping flux-based control [7,8], a flux linkage tracking

control [9], a robust control [10], sliding mode control [11], energyfunction-based optimal control strategy [12,13] to fulfill the LVRT re-quirements of DFIG-based WTs. However, modification only controlsystems cannot ensure the LVRT requirements in the case of severvoltage sag. In addition, the most of them are too complicated forpractical applications and need proper tuning of control parameters ofthe DFIG converters.

Crowbar system [14,15], reactive power injection (RPI) bySTATCOM [16,17], unified inter-phase power controller (UIPC)[18,19], dynamic voltage restorer (DVR) [20,21],series grid side con-verter (SGSC) [22], DC link chopper [23], energy storage system (ESS)[24], super-capacitor energy [25,26], stator damping resistor (SDR)[27], and series dynamic braking resistor (SDBR) [28], are the knownauxiliary hardware-based solutions used to satisfy the LVRT require-ments of DFIG-based WTs. In some cases, the crowbar system has beenused to protect the RSC [14,15]. However, when the crowbar is acti-vated, the DFIG behaves as a conventional IG and absorbs large amountof reactive power from the power system. It may lead to further de-crease of the GCP voltage which is adverse to stability of the powersystem when the penetration of WFs is high. In [16,17], the applicationof the STATCOM to improve the LVRT capability of DFIG has beenproposed. However, it cannot limit the RSC over current and DC linkover voltage of the DFIG during fault. The application of DVR, SGSCand UIPC offers a reliable interface to fulfill the LVRT requirements ofthe DFIG by injecting a series voltage to restore the stator voltage of theDFIG [18–22]. However, this method requires a full-rated series

https://doi.org/10.1016/j.ijepes.2018.04.031Received 2 September 2017; Received in revised form 9 March 2018; Accepted 25 April 2018

⁎ Corresponding author.E-mail addresses: h-shahbabaei@aliabadiau.ac.ir (H. Shahbabaei Kartijkolaie), m_radmehr@aliabadiau.ac.ir (M. Radmehr), m.firouzi@abhariau.ac.ir (M. Firouzi).

Electrical Power and Energy Systems 102 (2018) 287–295

0142-0615/ © 2018 Elsevier Ltd. All rights reserved.

T

transformer and voltage source converter (VSC). DC-link protectionsolutions such as energy storage system (ESS) and DC-link chopperresistance have been proposed to limit the DC link overvoltage of theDFIG [23,24]. In [25], the super-capacitor type ESS has been used toenhance the LVRT performance of the DFIG-based WFs. In [26], asuper-capacitor has been incorporated in DC link of STATCOM tocontrol GCP voltage of the DFIG during fault. In [27], a new schemebased on the stator–damping resistor and rotor current control has beenproposed. The results of the study show that the system becomes stableduring fault. But, such LVRT solutions cannot fulfill the all LVRT re-quirements of the new grid codes. In [28], the application of the SDBRis proposed to improve the LVRT performance of the DFIG.

On the other hand, direct grid connection of DFIG-based WFs resultin increasing the level of fault current contribution, which leads tosurpass circuit breakers (CBs) interruption capacity beyond the its ratedpeak withstand current [29,30]. In recent years, the application of faultcurrent limiters (FCLs) was found to be an effective solution for faultcurrent limitation and LVRT performance enhancement of WFs[31–36]. In [31,32], the application of superconducting FCL (SFCL) hasbeen proposed for LVRT performance enhancement of DFIG-based WTs.Due to high cost and technical limitations of producing super-conducting materials, they are not commercially obtainable. In[33–35], the conventional bridge-type FCL (BFCL) has been used forLVRT performance enhancement and fault current limitation of WFsduring fault condition. In [36], the conventional DC reactor-type FCL(DRFCL) has been suggested for LVRT performance enhancement ofWFs for the first time. Although, the utilization of the DRFCL effectivelyimproves the LVRT performance of WFs, however, transient over-voltage due to semiconductor turn on and turn off, high value of the DCreactor and cost of its transformer are main problems of the DRFCL forLVRT performance enhancement.

With this background, in this paper a capacitive DC reactor-typeFCL (CDRFCL) is proposed with different configuration of the conven-tional DRFCL to overcome the DRFCL drawbacks for LVRT performanceenhancement of the DFIG-based WF. The proposed CDRFCL limits theWFs contribution in fault current like other types of the FCLs [31–36],however, it is transformer less and the DC reactor value used in itsconfiguration is smaller than the conventional DRFCL [36], which re-sults in considerable cost savings. Also, by incorporation an AC capa-citor to the configuration of the CDRFCL, it can provide the reactivepower to support the GCP voltage, which is the main advantage of theCDRFCL to improve the LVRT performance of WFs. The efficiency of theCDRFCL is compared with the SDBR. The PSCAD/EMTDC software isused for simulation study.

2. Description of the power system and WF model

The power system depicted in Fig. 1 has been utilized for simulationstudy in this paper. It consists of an aggregated 20MW DFIG-based WF,which is connected to an infinite bus through a double circuit trans-mission lines. The CDRFCL is connected in series with one of thetransmission lines (i.e. L2). Three phase short circuit fault is applied to

the test system to evaluate performance of the proposed CDRFCL. Also,to show the efficacy of the proposed CDRFCL for LVRT performanceenhancement, its capability is compared with the SDBR. The SDBR is aproved solution for LVRT performance enhancement, and previousstudies show that it has the ability to fulfill LVRT requirements of WFs[27,28]. The SDBR is connected in series with the transmission linesand placed in the same position where the CDRFCL is placed in the testsystem. The parameters of the simulated system are listed in Table 1.The turbine and generator are two key components of a WF, which theirmodeling is as follows:

2.1. Wind turbine

The kinetic energy captured from the wind is converted to themechanical power (Pm) by the WT and is expressed, as follows [37]:

=P πρR C λ β V0.5 ( , )m p w2 3 (1)

where, Vw is the wind speed, ρ is the air density, R is the blade radiusand CP (β λ, ).

2.2. DFIG model

As shown in Fig. 2(a), the DFIG consists of the rotor side converter(RSC), DC link, grid side converter (GSC) and IG. Fig. 2(b) shows the dqequivalent circuits of the DFIG that are modeled in a synchronous dqreference frame. The voltage equations of the stator and rotor circuits ofthe generator are expressed as follow [38]:

= + −V R idλdt

ω λqs s qsqs

s ds (2)

= + −V R i dλdt

ω λds s dsds

s qs (3)

= + − −V R i dλdt

ω ω λ( )dr r drdr

s r qr (4)

= + − −V R idλdt

ω ω λ( )qr r qrqr

s r dr (5)

where, Rs and Rr are the stator and rotor resistance, Vdqs and Vdqr are thedq stator and rotor voltages, idqs and idqs are the dq stator and rotorcurrents, ωs is supply angular frequency, ωr is rotor angular frequencyand λdqs and λdqr are the dq stator and rotor flux linkage. The active andreactive power of the DFIG, Ps and Qs can be calculated, as follows:

⎜ ⎟= + = − ⎛⎝

⎞⎠

P V i V i LL

V i32

( ) 32S qs qs ds ds

m

Sqs qr

(6)Fig. 1. Test system with DFIG-based WF and CDRFCL.

Table 1Parameters of test system.

Parameters Value

Grid Supply 33 kVFrequency 50 HzX/R ratio 5

Induction generator Power 2MWVoltage 690 VRated frequency 50 HzNumber of poles 4Stator resistance 0.0053ΩStator reactance 0.0791ΩRotor resistance 0. 0161ΩRotor reactance 0.1021ΩMagnetizing reactance 2.4341ΩInertia constant 1 s

CDRFCL DC reactor (Ld) 0.01 HCd 20 uFRd 10Ω

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= − = −Q V i V i LL

V i i32

( ) 32

( )S qs ds ds qsm

Sqs ms dr

(7)

= +L L Ls ls m (8)

= +L L Lr lr m (9)

where, Ls, Lm and Lr are the stator and rotor and magnetizing in-ductance, respectively.

Fig. 2(c) shows the RSC control system of the DFIG. It regulates thestator active power through the q-axis rotor current component (iqr) andthe reactive power exchange between the stator and the grid throughthe d-axis rotor current component (idr). The actual d-q current signalsiqr and idr are compared with their respective reference signals to pro-duce the reference values vqr and vdr. These signals are used to generatethe PWM signal for driving the switching devices of the RSC. The re-ference power for the DFIG is obtained through the maximum powerpoint tracking (MPPT) lookup table [1,2]. Fig. 2(d) shows the GSCcontrol system of the DFIG. The main objective of the GSC is to keep theDC link capacitor voltage regardless of the direction of rotor powerflow. In such a scheme, the q-axis current is controlled to keep the DClink voltage constant. Also, d-axis current component is used to controlthe reactive power flow between the GSC and grid to keep PCC voltageat desired level.

2.3. Drive train model

The two mass shaft model is sufficient for modeling of WTs for theLVRT performance study [37]. Therefore, it is used to model the WTdrive train system. The drive train of a WT in general includes bladeswith hub, rotor shaft, gear box and generator. The blades and hub ispresented as inertia Ht. The gearbox and DFIG rotor is presented asinertia Hg, which are coupled with turbine shaft with stiffness coeffi-cient Ktg. The equations of this system are given as follows:

⎡

⎣

⎢⎢

⎤

⎦

⎥⎥

=

⎡

⎣

⎢⎢⎢⎢−

⎤

⎦

⎥⎥⎥⎥

⎡

⎣⎢⎢

⎤

⎦⎥⎥

⎡

⎣

⎢⎢⎢

⎤

⎦

⎥⎥⎥

⎡

⎣⎢⎢

⎤

⎦⎥⎥

−

− −

−ωωδ

ωωδ

TT

1 1 0

0 0

0 0

0 0 00

g

t

tg

DH

DH

KH

DH

DH

KH

g

t

tg

H

H

g

t

2 2 2

2 2 2

12

12

tg

g

tg

g

tg

g

tg

t

tg

t

tg

t

g

t

(10)

2.4. LVRT requirement

The LVRT is a major requirement for connection of WFs to powersystem and is described by a voltage against time characteristic [3,4].Based on this requirement, WFs must withstand voltage dips down to acertain percentage of nominal voltage and for a specific duration. Fig. 3shows a typical LVRT limit curve. It has four main parameters includevoltage dip duration (TD), percentage minimum voltage level (VM) andvoltage restoration time (TR), percentage minimum voltage restoration(VR), as shown in this figure. The parameters of LVRT curve for dif-ferent countries depend on the characteristics of each power system andprotection employed. The parameters of LVRT curve for differentcountries have been listed in Table 2.

Fig. 4(a) shows the GCP voltage profile, when a fault occurs. As

Fig. 2. (a) Schematic diagram of the DFIG-based WT, (b) equivalent circuit ofthe DFIG, (c) RSC control system, (d) GSC control system.

Fig. 3. Typical limit curve for LVRT requirement.

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shown in this figure, voltage sag at the GCP of the DFIG-based WT re-sults in rotor over current at the beginning and end of the fault period(i.e., voltage falling and recovering stages) as shown in Fig. 4(b). Also,it results in a DC-link over voltage during fault period as shown inFig. 4(c) [3]. Based on the LVRT requirement, WFs must remain con-nected to grid during fault conditions. Therefore, to meet the LVRTrequirements of DFIG-based WTs, appropriate measures should have

been taken In addition, WFs have to provide reactive power to con-tribute the GCP voltage recovery after fault clearance as shown inFig. 4(d) [4].

3. Capacitive DC reactor-type fault current limiter (CDRFCL)

In the past works [39–41], the configuration and principle operationof the DRFCL have been described. It has been depicted in Fig. 5(a). In[36], it has been proposed for LVRT performance enhancement of theWF. Although, the utilization of the DRFCL in this configuration [36],effectively limits FCC and improves the LVRT performance of WFs,however, it has problems with its operation as follows:

• IGBT turn on and turn off produces transient overvoltage, whichmight damage the semiconductor switches,

• Owing to the pick value of the fault current flow through DC reactorduring fault, the value of the DC reactor increases according to thepeak value of fault current during fault conditions,

• It needs a high cost transformer which its voltage rating is almostequal to line voltage for coupling the bridge circuit in series withline.

In this paper, in the first step, the configuration of the DRFCL hasbeen modified in DC side to overcome the mentioned problems asshown in Fig. 5(b). Also, in the next step, it is adapted with WFs en-vironment to satisfy reactive power compensation requirements of thenew grid codes by incorporation an AC capacitor in parallel with theDRFCL as shown in Fig. 5(c).

Table 2The parameters of LVRT curves for different countries.

Grid code Voltage dipduration (TD)

Minimumvoltage level(%VM)

Voltagerestoration time(TR)

Voltagerestoration level(%VR)

Germany 150ms 0 1500ms 90UK 140ms 0 1200ms 80Denmark 140ms 25 750ms 75Canada 150ms 0 1000ms 95USA 625ms 15 3000ms 90Spain 500ms 20 1000 80

Fig. 4. DFIG behavior under voltage sag (a) Grid connecting point voltage, (b)rotor current, (c) DC link voltage, (d) reactive current to be delivered to grid.

Fig. 5. The power circuit of, (a) conventional DRFCL used in [20], (b) modifiedDRFCL, (c) CDRFCL.

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3.1. Configuration of CDRFCL

As shown in Fig. 5(c), it consists of the DC side circuit, bridge circuitand AC side circuit. The bridge circuit includes a full diode bridge (D1-D4). The DC side circuit includes an IGBT switch (Q) connected in serieswith a small DC reactor parallel with freewheeling diode (Dm). To in-clude the resistance of the DC reactor, it has been modeled by rd inseries with Ld, the resistance and inductance of DC reactor. Also adischarging resistor (Rd) is connected in parallel with the bridge circuitin DC side. The third circuit is an AC capacitor (Cd), which connected inparallel with the bridge circuit in the AC side.

3.2. CDRFCL operation and control

The circuit depicted in Fig. 6(a) is used for analytical studies of thebasic operating principle of the proposed CDRFCL. The source and loadimpedance are modeled by = +Z r jXs s s and = +Z r jXL L L, respectively.Fig. 6(b) shows the DC reactor current (id), fault current (iL) duringnormal and fault operation modes in case of using the CDRFCL, re-spectively.

In normal operation mode, the IGBT switch (Q) is in ON state andline current (iL) flows through the D1-Ld-rd-D4-Q and D2-Ld-rd-D3-Q pathsin the positive and negative half cycle of electrical frequency, respec-tively. The diode bridge converts the AC current to DC current andflows through the DC reactor. After few cycles, the DC reactor currentreaches to the peak value of the line current (i0), and the limiter entersits steady state operation.

Therefore, as shown in Fig. 6(b), the DC reactor current (id) is ap-proximately constant and offers no impedance. Since, the impedance ofthe Cd and the Rd is relatively large, the line current flows through thebridge circuit and DC reactor path and the current flow through the Cd

and Rd is approximately equal to zero.The rd, the IGBT switch and diodes of bridge circuit switching

produce some voltage drop and power losses, but they are negligiblecompared to line drop and losses. During the fault operation mode, thecircuit operations divided in two before and after fault detection modesas shown in Fig. 6(b). The first mode starts at t = t0 and ends at t = t1.During this mode, the IGBT is in ON state and a fault current flowthrough the bridge circuit and the DC reactor. Therefore, the rate ofincrement of the fault current is limited by DC reactor without anydelay. It causes the DC reactor current increases with a constant rate, asshown in Fig. 6(b), approximately.

When the DC reactor current reaches to the threshold current (i1),the CDRFCL control system generates low voltage gate signal to makethe IGBT turn off as shown in Fig. 6(c). After, turn off the IGBT, thesecond mode begins at t = t1. During this mode, the IGBT switch isturned off by the control circuit and the bridge path is open circuited.Therefore, the discharging resistor (Rd) and AC capacitor (Cd) is in-serted in series with the line and short circuit current is limited duringthis mode. Also, the energy stored in the DC reactor is discharged infreewheeling diode (Dm), DC reactor resistance (rd) and DC reactor in-ductance (Ld) path. After fault clearing time at t = t2, The PCC voltagestarts to restore to the pre-fault value. Voltage dip at PCC has been usedto sense this mode and generate the IGBT gate control signal. As shownin Fig. 6(c), a comparator compares the PCC voltage (Vpcc) and pre-defined threshold voltage (VT). When the Vpcc reaches to the VT due tofault clearance, the IGBT receive a high voltage gate signal and theIGBT switch is turned on, and the system brought back to normal op-eration mode.

3.3. Effect of the CDRFCL on the performance of the DFIG

To investigate the effect of the CDRFCL on performance of the DFIGunder fault conditions, the simplified test system includes a DFIG andCDRFCL utilized as shown in Fig. 7(a). Fig. 7(b) shows the equivalentcircuit of this system under fault condition. The grid is represented bythévenin voltage (Vg) and impedance (Zg). The DFIG is representedinternal EMF (E') and reactance (X') [9], and the CDRFCL is presentedby Rd parallel with Cd, during fault.

When a fault occurs, the increment rise of the fault current is limitedby DC reactor without any delay and instantaneously deep voltage sagis prevented before fault detection. This characteristic of the CDRFCLcauses the spike of the rotor current, is effectively reduced at the be-ginning of the fault period. After fault detection, the Rd and Cd in DCand AC side of the CDRFCL is inserted in series with faulted line and hasthree effects, as follows:

1- The Rd dissipates output power from the DFIG during the faultperiod. Therefore, it prevents the DFIG rotor speed acceleration andmitigates DC link over voltage.

2- As shown in Fig. 7(b), the Cd provides the reactive power (Qd) tosupport the GCP voltage during fault. Since, the electrical torque isproportional to the square of the GCP voltage; it prevents the elec-trical torque reduction and DFIG rotor acceleration.

3- The Cd provides the reactive power needed by the DFIG (QI) afterfault clearance, which causes the reactive power absorption from

Fig. 6. (a) Test circuit includes the CDRFCL for analytical study, (b) effect of theCDRFCL during fault, (c) control system of the CDRFCL.

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grid (Qg), is effectively reduced after fault clearance. It helps to fastrecovery voltage and improves stability of power system.

3.4. DC reactor design

To design the DC reactor inductance, the value of the thresholdcurrent (i1) and its corresponding time with (t1) are two importantdecisive factors. The inductance of the DC reactor should be sufficientto damp the rise of the DC reactor current before fault detection, so thatthe id doesn't exceed the i1, after determined delay time for fault de-tection and the IGBT is completely turned off. The main purpose ofusing the DC reactor in DC side of the bridge circuit is to slow the ramprate of the increment of the fault current sufficiently, so that the con-troller can turn off the IGBT switch. During this mode, the DC reactorcurrent increases linearly and is approximately given by the followingequation:

= − +i t VL

t t i( ) ( )dd

d0 0

(11)

where, the i0 is the value of the DC reactor current at the instant of thefault inception (t = t0) and the Vd is the mean value of the source vol-tage on dc side and is approximately as follow:

=V Vπ

2d

m(12)

where, Vm is the magnitude of the source voltage. The effect of the rd isnot considered in (11), because its value in comparison with Ld is verysmall. By using (11), the minimum inductance of the DC reactor re-quired is obtained as follow:

= −−

L t ti i

Vd d1 0

1 0 (13)

Furthermore, by determining the t1 and i1, it is possible to design theDC reactor inductance.

3.5. DC side resistor (Rd) design

As shown in Fig. 7(a), each of lines (i.e., L1 and L2) transfers half ofthe active power generated by the DFIG (PI), during normal operationmode. To make sure the least disturbance reaches to the DFIG duringfault operation mode, the Rd should be sufficient to dissipate the sameactive power transferred by the faulted line. Therefore, the Pd is de-termined as follow:

= =PVR

P2d

pcc

d

I2

(14)

Using (14), the minimum value of the Rd can be derived as follow:

=RVP

2d

pcc

I

2

(15)

Eq. (15) shows that value of the Rd depends on the active powergenerated by the WF.

3.6. AC side capacitor (Cd) design

The value of the Cd should be sufficient to provide the reactivepower needed of the DFIG after fault clearance. Therefore, the Qd isdetermined as follow:

= =Q C ωI Qd d c I2 (16)

Using Fig. 6(b), the Ic is defined as follow:

=I C ωVc d PCC (17)

By using (16) and (17), the minimum required value of the Cd can bederived:

=C QV ωd

I

PCC2 (18)

Eq. (18) shows that value of the Cd depends on the reactive powerneeded of the DFIG.

5. Series dynamic braking resistor (SDBR)

To show the efficacy of the proposed CDRFCL for LVRT performanceenhancement, its capability is compared with the SDBR. The per-phaseschematic diagram and control system of the SDBR is depicted in Fig. 8.It consists of a fixed resistor connected in parallel with a bypass switchand is modeled as following equation:

= ⎧⎨⎩

⩾<R

V VR V V0 | |

| |SDBRPCC T

m PCC T (19)

where, Rm is the resistance value of the RSDBR. The bypass switch isbased on the insulated-gate bipolar transistor (IGBT) technology. ThePCC voltage (VPCC) is used as actuating signal of the bypass switch asshown in Fig. 7. The bypass switch is closed in order to bypass theresistor under normal condition. Once the PCC voltage falls below thethreshold value (VT), the bypass switch is opened and the SDBR resistoris dynamically inserted in series with line.

The SDBR resistor (RSDBR) would remain in the circuit as long as theVPCC is below the threshold value. As the VPCC reaches to the VT due tofault clearance, the IGBT switch will be closed and the system will re-turn to normal operation mode.

Fig. 7. (a) the simplified test system includes the DFIG connected to grid withCDRFCL (b) equivalent circuit of system with CDRFCL during fault.

Fig. 8. Schematic diagram of the SDBR.

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6. Simulation results

The simulations were carried out using PSCAD/EMTDC software. Athree-line-to-ground (3LG) fault is applied on transmission line 2 (L2) asshown in Fig. 1. The fault is applied at t = 10 s. After 0.15 s, the circuitbreaker isolates the faulted line. For the short circuit fault analysis, thewind speed is assumed constant at 16m/s. In order to show the effec-tiveness of the proposed CDRFCL, the simulations are carried out forthree following scenarios:

Scenario A: Direct connection to grid without using any FCL andSDBR,Scenario B: Connecting through SDBRScenario C: Connecting through CDRFCL

Fig. 9(a) shows the voltage profile of the WF at the PCC bus for allscenarios. As shown in this figure, the CDRFCL has the best perfor-mance with lowest voltage sag during fault compared with scenario Aand B. Also, the voltage recovery process is considerably shortened inthe scenario C. Fig. 9(b) shows the rotor currents of the DFIG for allscenarios. As shown in this figure, the rotor transient spike current issignificantly limited and is lowest at the beginning and end of faultperiod in the scenario C. Fig. 9(c) shows the total active power gener-ated by the WF. In the scenario A, the active power generated by the WFreaches to zero during fault, approximately. The CDRFCL and SDBRprevent the abrupt active power generated drop.

But, the CDRFCL has the minimum power drop and oscillationduring fault. Fig. 9(d) shows the reactive power exchange between theWF and the grid. As shown in this figure, the absorbed reactive powerfrom the grid is -2.8 pu in the scenario A. it is effectively reduced inscenario B and C, however, it is clear that the absorbed and the oscil-lation of the reactive power from the grid is lowest in the scenario C,during and after fault clearance.

Fig. 10(a) shows the DC link voltage of the DFIG for all scenarios. Itis obvious that the CDRFCL application effectively decreases the over-voltage of the DC link voltage compared with scenario B and C, duringfault and after fault clearance. The DFIG speed response for 3LG fault is

shown in Fig. 10(b). The rate of rising of the DFIG speed is limited inboth scenarios B and C, which ensures better stability. But, the CDRFCLis more competent to do this than the SDBR because it gives loweroscillation and faster stabilization.

Fig. 10(c) shows the reactive power flow in the line 1. As shown inthis figure, the absorbed reactive power from grid through line 1 are−0.5 pu and −2.5 pu in the scenario A and B, respectively. But, in thescenario C, the reactive power generated by the AC capacitor of theCDRFCL is injected through line 1 to grid to support the grid voltage,which leads to satisfy the LVRT requirements.

Fig. 10(d) shows the reactive power flow in the line 2, which theCDRFCL and SDBR are inserted in this line. As shown in this figure, inthe scenario C, the AC capacitor of the CDRFCL generates the reactivepower to support the grid connecting point voltage, which caused thePCC voltage sag, is lowest in the scenario C.

Fig. 11(a) shows the electrical torque of the DFIG. As shown in thisfigure, the CDRFCL and SDBR decrease the oscillation of the electricaltorque. Fig. 11(b) shows the enlargement of Fig. 11(a). Fig. 11(b) and(c) shows the d-q axes rotor current for all scenarios. As shown in thisfigure, there was a considerable decrease in oscillations in the d-q axesrotor current in scenario C. Fig. 12(a) and (b) shows the d-q axes statorcurrent for all scenarios. As shown in this figure, the CDRFCL and SDBRdecrease the oscillation of the d-q axes stator current. But, the CDRFCLis more competent to do this than the SDBR because it gives loweroscillation.

7. Conclusion

In this paper, in the first step, the configuration of the DRFCL ismodified to overcome its limitations of operation. In the next step, it isadapted with WF environment for improving the LVRT performanceand limiting the fault current contribution of DFIG-based WFs. Based onsimulation results, the following points can be drawn:

• The ramp rate of the increment of the fault current has been limitedby DC reactor without any delay. This characteristic of the CDRFCLsuppresses the instantaneous voltage drop, which causes limitation

Fig. 9. Response of WF subject to three phase short-circuit fault for all scenarios (a) PCC voltage, (b) Rotor current, (c) WF active power, (d) WF reactive power.

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of the rotor and stator transient over currents at the beginning andend of the fault period.

• The CDRFCL not only provide the needed reactive power of the WF,but also support the grid connecting point voltage by capacitivecompensation during and after fault period. This characteristic ofthe CDRFCL fulfills reactive power compensation requirements ofthe DFIG-based WF.

• The discharging resistor of the DC side of the CDRFCL consumesexcess active power from the WF during the fault period. Therefore,it prevents the DC link over voltage during and after fault clearance.

• The comparison with SDBR shows that the CDRFCL is more effectivefor enhancement of LVRT performance than SDBR.

Fig. 10. Response of WF subject to three phase short-circuit fault for all scenarios (a) DC link voltage, (b) Rotor speed of DFIG, (c), reactive power flow of the line 1(d) reactive power flow of the line 2.

Fig. 11. Response of WF subject to three phase short-circuit fault for all scenarios (a) Electrical torque, (b) Enlargement of Fig. 11(a), (c) d-axis rotor current variation(d) q-axis rotor current variation.

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Appendix A. Supplementary material

Supplementary data associated with this article can be found, in theonline version, at http://dx.doi.org/10.1016/j.ijepes.2018.04.031.

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