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Solid-State Electronics 54 (2010) 965–971
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Solid-State Electronics
journal homepage: www.elsevier .com/locate /sse
Effective passivation and high-performance metal–oxide–semiconductordevices using ultra-high-vacuum deposited high-j dielectrics on Gewithout interfacial layers
L.K. Chu a, R.L. Chu a, T.D. Lin a, W.C. Lee a, C.A. Lin b, M.L. Huang a, Y.J. Lee a, J. Kwo b,c, M. Hong a,*
a Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu, Taiwanb Department of Physics, National Tsing Hua University, Hsinchu, Taiwanc Center for Condensed Matter Science, National Taiwan University, Taipei, Taiwan
a r t i c l e i n f o a b s t r a c t
Article history:Available online 21 May 2010
The review of this paper was arranged byS. Cristoloveanu
Keywords:GeHigh-j dielectricMOSCAPMOSFETCF4
0038-1101/$ - see front matter � 2010 Elsevier Ltd. Adoi:10.1016/j.sse.2010.04.034
* Corresponding author.E-mail addresses: [email protected] (M. Hon
(J. Kwo) .
Without using any interfacial passivation layers, high-j dielectric Y2O3, HfO2, and Ga2O3(Gd2O3) [GGO],by electron beam evaporation in ultra-high-vacuum (UHV), have been directly deposited on Ge substrate.Comprehensive investigations have been carried out to study the oxide/Ge interfaces chemically, struc-turally, and electronically: hetero-structures of all the studied oxides on Ge are highly thermally stablewith annealing to 500 �C, and their interfaces remain atomically sharp. The electrical analyses have beenconducted on metal–oxide–semiconductor (MOS) devices, i.e. MOS capacitors (MOSCAPs) and MOS field-effect-transistors (MOSFETs). Dielectrics constants of the Y2O3, HfO2, and GGO have been extracted to be�17, 20, and 13–15, respectively, indicating no interfacial layer formation with 500 �C annealing. A lowinterfacial density of states (Dits), as low as 3 � 1011 cm�2 eV�1, has been achieved for GGO/Ge near mid-gap along with a high Fermi-level movement efficiency as high as 80%. The GGO/Ge pMOSFETs with TiNas the metal gate have yielded very high-performances, in terms of 496 lA/lm, 178 lS/lm, and 389 cm2/V s in saturation drain current density, maximum transconductance, and effective hole mobility, respec-tively. The gate width and gate length of the MOSFET are 10 lm and 1 lm.
� 2010 Elsevier Ltd. All rights reserved.
1. Introduction
The drive beyond the 16 nm node complementary metal–oxide–semiconductor (CMOS) technology using Si channel hasencountered formidable challenges, as further scaling in the tran-sistors may not provide device performance advantages [1]. Newmaterials of high-j dielectrics on high carrier mobility channels,and novel device architectures have to be employed for fulfillingthe required performance [2–6]. Ge has been considered as oneviable contender as the channel material because of its carriermobility advantages compared to Si. Beyond question, a high-qual-ity interface between the high-j dielectrics and Ge is the key torealize the applications of high-performance Ge MOS devices.However, it is difficult to achieve a high-quality oxide/Ge interfacewith integrity like SiO2/Si due to the unfavorable surface propertiesand water-soluble native oxides of Ge [7]. Over the past few years,several interfacial layers have been used to passivate Ge surface forsubsequent deposition of high-j dielectrics; GeOxNy, formed with
ll rights reserved.
nitridizing GeOx [8] and epitaxial Si layers (followed by partiallyoxidizing the Si layer to form SiO2/Si, thus eliminating/minimizingthe passivation difficulty in oxide/Ge [9]) are the two notableexamples. Moreover, stoichiometric GeO2 grown by exposing Gesurface to pure oxygen atmosphere at �550–600 �C has exhibitedgood passivation for Ge [10,11]. However, the efforts of using theinterfacial passivation layers may encounter an obstacle in furtherreducing the equivalent oxide thickness (EOT) due to the low per-mittivity of the interfacial layers (jGeOxNy � 7, jSi � 12, jSiO2 � 4,jGeO2 � 7), especially for the projecting technology beyond the16 nm node that requires an EOT significantly less than 1 nm[12]. To meet the requirement for the ultimate EOT down-scaling,direct deposition of high-j dielectrics on Ge without interfaciallayers is imperative while maintaining a high permittivity and de-cent interface quality between high-j dielectrics and Ge [4,13–16].
In this work, electron beam evaporated high-j dielectrics ofY2O3, HfO2, and Ga2O3(Gd2O3) [GGO] have been deposited directlyon Ge substrate in ultra-high-vacuum (UHV). The physical andchemical interfacial characteristics have been investigated withreflection high-energy electron diffraction (RHEED), high resolu-tion transmission electron microscopy (HR-TEM), and angle-re-solved X-ray photoelectron spectroscopy (AR-XPS). The electrical
966 L.K. Chu et al. / Solid-State Electronics 54 (2010) 965–971
characteristics of capacitance–voltage (C–V) behaviors, dielectricconstant of the oxides, interfacial density of states (Dits), and gateleakage current densities (J) have been obtained on MOS capacitors(MOSCAPs) and MOS field-effect-transistors (MOSFETs).
In the case of GGO on Ge, CF4 plasma treatment has been intro-duced [17–19] as one of the post deposition treatments to furtherreduce the Dits towards low 1011 cm�2 eV�1. In addition, the Fermi-level movement efficiency (FLME) of 80% has been measured usingquasi-static C–V (QSCV). FLME is the Fermi-level response at semi-conductor surface to the applied gate bias, evaluating the quality ofoxide/semiconductor interface [20]. Gate length (1 lm) GGO/GepMOSFETs with TiN as the metal gate have given excellent deviceperformances in including saturation drain current density (Id),peak transconductance (gm), and hole mobility.
2. Experimental
Two-inch n-type and p-type Ge (1 0 0) wafers with Sb-dopedand Ga-doped, respectively, were dipped in diluted HF (2%) andrinsed in de-ionized water, followed by UHV annealing at�450 �C for 10 min to remove the residual native oxides. CleanGe surface was obtained, as evidenced by sharp and streaky2 � 2 RHEED patterns. Y2O3, HfO2, and GGO films electron beamevaporated from three respective compact oxide sources, with Gesubstrates being at room temperature. In situ Al2O3 cap layers(�3 nm) were deposited on Y2O3 and HfO2 to protect the under-neath oxides from absorbing moisture and contaminations duringthe fabrication of MOS devices [21]. Y2O3, HfO2, and GGO layerswere all found to be amorphous, as confirmed by featurelessRHEED patterns and HR-TEM. No oxygen was added during theoxide deposition. Samples for in situ AR-XPS were separately pre-pared with thinner dielectric films (<3 nm) for probing the oxide/Ge interfaces; the samples were in situ transferred into the XPSchamber right after the oxide deposition. To exam the thermal sta-bility of the oxide/Ge entity, AR-XPS analyses were conducted be-fore and after an in situ 500 �C anneal for the HfO2/Ge and GGO/Gesamples.
After removing the samples from the UHV system, nitrogen an-neals were performed at 500 �C to all samples prior to metal gatedeposition. CF4 plasma treatment was applied to GGO (�14 nm)/Ge samples, prior to the nitrogen anneal using an inductively-cou-pled plasma system with a total pressure of 10 Pa, where CF4 andO2 sources were introduced with a CF4/O2 ratio of 10/1 and a rfpower of 20 W.
Ti/Au, deposited through a shadow mask with 100 lm in diam-eter by electron beam and thermal evaporation, respectively, wasused as the gate metals for the MOSCAPs. For the GGO/Ge pMOS-FETs’ fabrication, after the CF4 treatment and nitrogen anneal,sputtering TiN was patterned as the metal gates. The detailedself-aligned process flow is listed in Table 1. HR-TEM analyses werecarried out using a JEOL, JEM2100F type TEM. Mg Ka(ht = 1253.6 eV) and Al Ka (ht = 1486.6 eV) X-ray source and a
Table 1Process flow of the self-aligned GGO/Ge pMOSFET.
� Diluted HF dip + de-ionized water rinse� UHV annealing �450 �C� GGO deposition �14 nm� CF4 plasma and N2–500 �C treatment� TiN metal gate by sputtering� ICP-RIE for pattering TiN gate� S/D implantation with B� S/D activation: 450 �C, 20 min� S/D with Ti/Al� Wet etching GGO� Contact metal deposition
SPECS-PHOIBOS-150 hemispherical electron analyzer were usedfor AR-XPS analyses. The take-off angle is defined as the angle be-tween the direction of surface normal and detector.
Agilent 4284 was used for the measuring capacitance–voltage(CV) and conductance–voltage characteristics. Agilent 4156C wasused for studying current–voltage (I–V) and quasi-static CV (QSCV)characteristics of the MOS devices. For charge pumping (CP) mea-surement, Agilent 81110A pulse generator was used for constant-amplitude gate pulse generation and Agilent 4156C for obtainingcharge pumping currents (Icp).
3. Results and discussion
3.1. Y2O3 on Ge
A thin Y2O3 layer 2.6 nm thick was deposited on Ge for the AR-XPS characterizations. As shown in Fig. 1a, the Ge 2p core levelspectra indicate Ge inter-diffusion into the as-deposited Y2O3 filmas there is a peak appearing at a binding energy of �1219.8 eV inaddition to the peak at �1217.8 that represents the signals fromGe substrate. The extra peak at a higher binding energy impliesthe formation of Ge–O–Y bonding [16]. Nevertheless, the generalreduction in dielectric constant resulted from the Ge inter-diffu-sion was not observed, indicating the inter-diffusion may not besignificant. This is also confirmed with HR-TEM (Fig. 1b), wherethe Y2O3/Ge interface remains abrupt after 500 �C anneal.
For the Al2O3(3 nm)/Y2O3(4.4 nm)/n-Ge (resistivity of�0.3 X cm) MOSCAPs with a post deposition anneal (PDA) of500 �C for 10 min, the Y2O3 layer possesses a favorable dielectricconstant of 17 and a low J of �10�8 A/cm2 at flat-band voltage(Vfb) + 1 V. However, the Ge inter-diffusion may account for theabnormal C–V behavior in the depletion region at low measure-ment frequencies [22]. As shown in Fig. 1c, the C–V curvesstretched out as the measurement frequencies decrease, indicatinga high Dit. Indeed, a high mean Dit value of �6.7 � 1012 cm�2 eV�1
was extracted near mid-gap by charge pumping. Icp is related to theequation
Icp ¼ 2qDitfAkT ln v thniffiffiffiffiffiffiffiffiffiffiffirnrp
p� �þ ln
Vt � V fbj jVh � Vbj j
ffiffiffiffiffiffiffiffiffiTrTf
q� �� �ð1Þ
where Dit is the mean Dit, f the measurement frequency, A the gatearea, kT the thermal energy, vth the thermal velocity, (rn, rp) thecapture electron and hole cross section, (Vt, Vfb) the threshold andflat-band voltage, (Vh, Vb) the gate pulse high and base level, and(Tr, Tf) the rise and fall time. Fig. 1d displays the Icp versus the baselevel sweeping from �0.8 V to 1.5 V with a constant amplitude of0.8 V, where the measurement setup is also denoted.
3.2. HfO2 on Ge
Two stacks of Al2O3(3 nm)/HfO2(2.8 nm) and Al2O3(3 nm)/HfO2(2.4 nm) on n-Ge (resistivity of �4 X cm) and p-Ge(�0.02 X cm) were prepared for pMOS and nMOS analyses, respec-tively. In situ AR-XPS analyses have been performed on theHfO2(2.8 nm)/Ge prior to the Al2O3 cap deposition. For the as-deposited condition no Ge inter-diffusion has been observed with-in the detection limit of XPS (�1% in atomic amount), as evidencedby the absence of any extra peaks in the Ge 2p core level spectra inaddition to the peak coming from Ge substrate [15]. This behavioris similar to the earlier observation for HfO2 on Ge by evaporatingHf under atomic oxygen source [14]. After an in situ 500 �C annealfor 20 min, slight Ge inter-diffusion has occurred as the Ge 2p spec-tra show a small bump contiguous to the peak from Ge substrate(not shown). The Ge inter-diffusion, however, was insignificantsince the corresponding Hf 4f core level spectra remained un-
Fig. 1. (a) Ge 2p3/2 core level spectra for the as-deposited Y2O3(�2.6 nm)/Ge sample. a Indicates the take-off angle. (b) HR-TEM micrograph of Al2O3/Y2O3/Ge hetero-structures after a 500 �C–10 min anneal. (c) C–V characteristics at 5–500 kHz of the AuTi/Al2O3 (�2.9 nm)/Y2O3(�4.4 nm)/n-Ge MOSCAP. (d) Charge pumping current versusbase level from �1 V to 1.5 V at 1 MHz.
Fig. 2. (a) Hf 4f core level spectra at various take-off angles for the 500 �C annealed sample. (b) HR-TEM micrograph of Al2O3/HfO2/Ge hetero-structures after a 500 �C–10 minanneal. (c) C–V characteristics at 1 k and 500 k Hz of the AuTi/Al2O3/HfO2/Ge p and nMOSCAPs.
L.K. Chu et al. / Solid-State Electronics 54 (2010) 965–971 967
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changed at different take-off angles from 0� to 75�, as shown inFig. 2a, indicating the intactness of the entire HfO2 layer. The highthermal stability of the Al2O3/HfO2/Ge hetero-structure to 500 �Cwas revealed by HR-TEM, as shown in Fig. 2b. The C–V curves forthe p- and n-type MOSCAPs with the aforementioned bi-layers ofAl2O3/HfO2 as the gate dielectrics are shown in Fig. 2c. A N2 PDAat 500 �C for 20 min was applied to the samples. Capacitanceequivalent thicknesses (CETs) of the pMOSCAP and the nMOSCAPswere extracted to be 2 nm and 1.8 nm, respectively. A high j valueof the HfO2 up to 20 again suggests no formation of interfacial layerthat would lower the j value. The Js of the MOSCAPs are around10�4 A/cm2 at Vfb ± 1 V, exhibiting a reduction of gate leakage by
Fig. 3. (a) Ge 3d core level spectra for the CF4 and N2–500 �C–5 min treated GGO/Ge samafter a 500 �C–5 min anneal.
Fig. 4. (a) C–V characteristics at 1 M Hz of the AuTi/GGO(�14 nm)/n-Ge MOSCAPs wittreatment durations. The attachment picture shows the corresponding J–E characteristics5 min and a 500 �C annealing in N2 for 5 min. QSCV is also demonstrated. (d) W–V relat
�2 orders of magnitude compared to SiO2/Si at the same CET[23]. The frequency-dispersion (FD) (from 1 to 500 kHz) of �11%and frequency-dependent Vfb shift of �0.28 V in the pMOSCAPsare larger than 5% and 0.13 V in the nMOSCAPs, indicating a higherDit in the former. Indeed, Dits close to mid-gap extracted using Ter-man method [24,25] are 5 � 1012 and 2 � 1012 cm�2 eV�1 for thepMOSCAPs and nMOSCAPs, respectively.
3.3. GGO on Ge
Low Dits and low electrical leakage currents have beenachieved with direct deposition of GGO on Ge and (In)GaAs at a
ple. The take-off angle is zero. (b) HR-TEM micrograph of GGO/Ge hetero-structures
h different CF4 treatment durations. (b) Frequency dispersions as functions of CF4
. (c) C–V characteristics of AuTi/GGO/n-Ge MOSCAPs with CF4 plasma treatment forionship extracted from the QSCV.
L.K. Chu et al. / Solid-State Electronics 54 (2010) 965–971 969
substrate temperature of �500 �C [4,26]. The high-quality GGO/semiconductor interfaces, without forming any interfacial layers,have given rise to the excellent device performances [2,4,27].
In this work, GGO has been deposited at room temperature tofurther suppress the Ge inter-diffusion. The sharp GGO/Ge inter-face has sustained a thermal process of 500 �C for 5 min withoutnoticeable Ge inter-diffusion and formation of interfacial layer[19], as revealed by AR-XPS and HR-TEM results shown in Fig. 3aand b, respectively.
For the MOS devices, an n-Ge substrate with a resistivity of0.07–0.2 X cm was used. Fig. 4a displays the C–V characteristicsmeasured at 1 MHz for the MOSCAPs with 0, 3 min, 5 min CF4 plas-ma treatment plus an anneal at 500 �C for 5 min in nitrogen. Vfb
shifts towards negative values as the treatment time increases.
Fig. 5. Schematic cross-section picture and SEM micrograph of the MOSFETs.
Fig. 6. (a) Output characteristics Id versus Vd of the Ge pMOSFET with 10 lm in gate widregion (Vd = �4 V). (c) C–V curves of the GGO/Ge MOSCAPs with TiN gate; the inset shomobility versus effective field. Si universal hole mobility is included.
The negative shift of the Vfb may be resulted from the incorporationof fluorine ion and the slight oxygen deficiency in the electronbeam evaporated GGO. The presence of F�1 in place of the O�2 sitesmay contribute to the presence of positive charges [28]. This isconsistent with the reduction in j value of the GGO that receivedthe CF4 treatment for the 5 min duration. A small amount of Gdfluoride formed near the oxide surface according to the XPS analy-ses (not shown) and the permittivity decreased from �14–15 to 13.
Comparisons of the FDs in both accumulation region (from 1 to500 kHz) and depletion region (frequency-dependent Vfb shift)were made in Fig. 4b, where FDs of less than 3.5% and 0.1 V havebeen achieved in accumulation and depletion regions, respectively,for the sample with 5 min CF4 treatment. Moreover, as exhibited inFig. 4c, the nearly-ideal C–V behaviors, in terms of the negligibleFDs and excellent inversion behavior, indicate the high-qualityGe MOS, particularly the GGO/Ge interface. To minimize the effectsof bias sweeping rate in ac measurements, a QSCV was measured(also in Fig. 4c) with a gate bias sweep of 1 mV/s from �2.5 V to1 V, showing good consistency with the C–Vs obtained at variousfrequencies. Quasi-static measurement has effectively alleviatedthe influence of parasitic resistance, thus providing a more perti-nent evaluation. A CET of 4.18 nm (EOT � 3.8 nm) was derived, giv-ing a dielectric constant of 13 for the GGO dielectric. The GGOcomposes of rare-earth Gd2O3, which tends to absorb moistureafter air exposure [29]. Despite the degradation of the GGO film,very low Js in the range of 10�8–10�9 A/cm2 have been obtained,as shown in the inset of Fig. 4b.
From the QSCV data, the surface potential (W), extracted by uti-lizing the Berglund’s integral [30], was plotted as a function of ap-plied gate bias (Fig. 4d), showing the Fermi-level movement (FLM)across the entire band gap of Ge (0.66 eV). Compared to the idealcurve of Dit = 0, a FLME of �80% near the mid-gap region on theGGO/Ge has been obtained: FLME (%) = 100% � (measured W–Vslope)/(ideal W–V slope) [20]. This high efficiency suggests FLM re-sponses well to the applied gate biases. In other words, the Ge sur-face is unpinned and Fermi-level moves freely.
th, and 1 lm in gate length. (b) Corresponding Id–Vg and gm–Vg curves in saturationws the Id–Vg and gm–Vg relations in linear region (Vd = �50 mV). (d) Effective hole
Table 2Comparisons of basic parameters and electrical performances for the Ge pMOS devices.
Passivation/dielectric Treatment Mid-gap Dit(�l011 cm2 eV�l) lh (cm2/V s) EOT (nm) Id � Lg (lA) (@Vg) Ref.
Si(SiO2)/HfO2 H2 2 (CP) 358 1.3 170a (�2 Vb) [34]GeO2/SiO or Al2O3 H+ 0.9 (LTCM) 400 >15 76 (�3 V) [11]GeO2/HfO2 CF4 + FG 2 (CM) 396 1 378 (�1.2 Vb) [17]GGO/GGO CF4 + N2 3 (CP) 389 3.8 496 (�4 V) This work
CP = charge pumping, CM = conductance method, LT = low temperature.a Short channel effect (Lg = 0.125 lm).b Vg–Vt.
970 L.K. Chu et al. / Solid-State Electronics 54 (2010) 965–971
To study the effectiveness of the CF4 plasma treatment in reduc-ing the interfacial traps, Dits have been extracted using a room-temperature conductance method. Note that overestimations ofthe Dits are expected in the small band-gap Ge [31]. A reductionin mid-gap Dits has been observed with the CF4 plasma treatmenttime. For 5-min CF4 treatment, Dit value of 7.7 � 1011 cm�2 eV�1
was extracted. In order to avoid the possible overestimations, CPmeasurements have also been carried out to accurately determinethe Dits with a sweep of the gate base level from �2 V to 0 V and agate pulse with a constant amplitude of 0.8 V. The relation be-tween Icp and Dits has been discussed earlier in this paper. Conse-quently, a mean value of Dits of �3 � 1011 cm�2 eV�1 was obtainednear the mid-gap (±0.15 eV). A reduction in Dits by about eighttimes has been observed compared to the sample with only nitro-gen anneal at 500 �C for 5 min. Detailed analyses for the CF4-trea-ted GGO/Ge system based on CP technique are introduced [32].
Ge pMOSFETs have been fabricated with gate lengths varyingfrom 20 lm to 1 lm. The cross-sectional schematic and scanningelectron micrograph of the finished device patterns are shown inFig. 5. The drain current density (Id)–drain voltage (Vd) curves fora MOSFET with a gate width (Wg) and a gate length (Lg) of 10 lmand 1 lm are shown in Fig. 6a. A saturation Id of 496 lA/lm wasmeasured at gate voltage (Vg) of �4 V. The corresponding maxi-mum transconductance (gm) reaches 178 lS/lm at Vd of �4 V, asshown in Fig. 6b, where the Id–Vg characteristics are demonstratedas well. A subthreshold slope of �195 mV/dec was measured andexpected to be improved as the oxide thickness and off-state leak-age current are further reduced. The threshold voltage (Vt) is ex-tracted to be ��0.7 V from the linear Id–Vg curve, as shown inthe inset of Fig. 6c. This value of Vt is in good agreement with thatobserved in the C–V curves using TiN as the metal gate, as illus-trated in Fig. 6c. Split C–V measurements have been carried outto obtain the inversion charge (Qinv) for the extraction of effectivehole mobility (lh,eff) according to the equation
lh;eff ¼LgId
WgVdQ invð2Þ
The patterns designed for the split C–V measurement have agate dimension of 40 lm in length and 100 lm in width. Fig. 6dshows lh,eff as a function of effective field (Eeff), in which Eeff is de-fined as
Eeff ¼Cox
esVg � 1� gð ÞðVg � VtÞ
ð3Þ
g and es are the constant parameter (0.3 for hole) and the permittiv-ity of Ge (16.2), respectively [33]. A high lh,eff of 389 cm2/V s hasbeen obtained at a low Eeff. This value is in line with the highest holemobility for unstrained Ge and comparable to �2.8� of the Si uni-versal hole mobility. Our pMOSFETs’ performances are comparedfavorably with the previously published Ge pMOS devices usinginterfacial passivation layers, as shown in Table 2 [11,17,34].
4. Conclusion
Without any interfacial layers, ultra-high vacuum depositedY2O3, HfO2, and GGO on Ge (1 0 0) exhibits good passivationcharacteristics for the MOS devices. Ge inter-diffusion was ob-served in the as-deposited Y2O3/Ge sample while the inter-diffu-sion in HfO2/Ge and GGO/Ge was much suppressed even beingsubjected to a 500 �C anneal. For the GGO/Ge system, CF4 plasmatreatment was conducted to improve the performance of theMOS devices. The attainment of nearly-ideal C–V characteristics,an extremely low Dit of low 1011 cm�2eV�1, a negligible fre-quency-dispersion, and a high Fermi-level movement efficiencyof 80% indicates high-quality MOS hetero-structures. Further-more, high-performance pMOSFETs with TiN/GGO/Ge structurehave also been fabricated, showing excellent electrical propertiesin terms of a high drain current, a high transconductance, and ahigh hole mobility.
Acknowledgement
This project was supported by National Nano Projects (NSC-98-2120-M-007-002 and NSC-97-3114-M-007-001) of National Sci-ence Council in Taiwan.
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