EET2141 Project 1: Using Xilinx 7.1 for Digital Simulation

Due Friday April 24th

Introduction

This project assignment is intended to familiarize you with the essential elements of the Xilinx design environment. You may use departmental laboratory facilities (EERC431, EERC421, EERC318). By the way, it is pronounced "zylinks". Project Navigator

To begin, you will need a place to store your work. If you are working on your own machine, you can choose a special place for your Xilinx project files or just use the default. Please note that Xilinx cannot read blank space in directory names such as ‘My Documents’.

Retrieve 2141proj1.zip from the EET2141 web site and store it in the EET2141

sub- directory on your PC (the one you have just created). Create a new subdirectory (folder) and name it EET2141proj1. Unzip EET2141proj1.zip using WinZip and extract the contents to the sub-directory 2141proj1. Among the files that have been extracted you will find a file named proj1.npl.

Start up the Xilinx project by double-clicking on the file proj1.npl. You can also start Xilinx ISE by double-clicking the ISE Project Navigator icon on your desktop or select Start → Programs → Xilinx ISE 7.1i → Project Navigator. This will open the Project Navigator window. Then select File → Open Project. Now browse down to proj1.npl and open it. This will open the project EET2141proj1 in the Project Navigator window (Figure 1). You may get a warning message from the Update Project window. Click Yes to update the project. This will automatically change to project name to proj1.ise.

Project Navigator is divided into four main sub-windows. The top left is the Sources in Project window, which hierarchically displays the elements included in the project. Beneath the Sources in Project window in Process View tab is the Processes for Source window, which displays available processes. The third window at the bottom of the Project Navigator is the Message Console, which shows status, error, and warning messages. It is updated during all project actions. On the right, the fourth window is the

Editor. From this window you can edit source files and view various reports that are generated by the processes.

Figure 1: Project Navigator window

Invoke the Schematic Editor

To invoke the Schematic Editor, double-click on the source named adder (adder.sch) in the Project Navigator window (shown highlighted in the above picture). This will load the circuit in the Schematic Editor window. The Options window appears on Processes for Source window. You can still view Processes for Source window by click on Process View tap. There are toolbars across the top of the window. The buttons in the toolbars have pop-up balloon help strings that appear if you leave the mouse pointer atop them for a few seconds. Explore.

This design may be too small to see, so you can zoom in. Click the Zoom In button

from the toolbar (it’s depicted as a magnifying glass with a + sign inside it). The schematic view will expand to show the entire design sheet. You may then use the scroll bar to view a particular portion of the schematic. You can use the Zoom Out button (next to Zoom In) to view the entire schematic. Take some time to explore the Xilinx environment!

Beginning the Simulation

At this point, Xilinx only knows about the circuit and nothing about how you want to simulate it. Therefore, you will need to set up the simulation before you actually simulate the circuit. First, let’s take a look at the circuit. When the schematic appears in the Schematic Editor window, notice the inputs and outputs in the schematic. (They are at the edges of the circuit and look like a box with a point at one end. They have text on the inside and a wire on the other.) In a simulation you want to watch what electrical activity is happening on various nets (wires).

Xilinx ISE is optimized for a Hardware Description Language (HDL) approach and

the simulation of circuits is carried out using testbenches. But for simulation we don’t require the knowledge of any HDL as Xilinx ISE has a Graphical User Interface (GUI) based testbench generator called HDL Bencher. After setting the input values in the HDL Bencher, we can do a simulation of the circuit using ModelSim, simulation software from ModelTech.

In your Project Navigator window, click on your schematic file adder (adder.sch)

to make it active. Now select Project → New Source. In the window (Figure 2) that opens up select the option Test Bench Waveform. Specify a name for the waveform in the File Name field and click on Next. In the following window click on Next and then finally click Finish.

Figure 2: New Source window

In the Initialize Timing window (Figure 3), select the option Combinatorial Design.

In the input boxes after Check outputs and Assign Inputs, enter the value 1, Initial Length of Test Bench to 20 ns and set the time scale to ns as shown below and click OK. This will open the HDL Bencher window (Figure 4).

Figure 3: Initialize Timing window

Figure 4: HDL Bencher window Assigning Input Values

You need to make the simulator apply all possible inputs to the logic design. We

have three primary inputs to our circuit: X, Y, and Cin. To simulate the circuit functionally, we should simulate all 8 possible combinations of the inputs. To do this, we are going to assign a square waveform (toggles between 1 and 0 in a regular pattern) to Cin and then assign similar waveforms to X and Y but the time period of successive waveforms will be twice that of the former. So the time period of X is twice that of Cin. The time period of Y is four times that of Cin. Now if we simulate the circuit for 4 time periods of Cin, we will get all the possible 8 combinations.

When you click on any of the blue areas in the row of inputs, it will toggle the

values from 0 to 1 and vice versa. To assign a square waveform, left click on the first 0 next to the input Cin at 0 ns. Select the Set Value… option (Figure 5).

Figure 5: Pattern assignment

Figure 6: Set Value window

Now click on the tab named Pattern Wizard in Set Value window (Figure 6). This

will open up the Pattern Wizard. Set the pattern as Toggle, Number of Cycles as 8, Initial Value as 0 and Other Value as 1 and Toggle Every as 1 as shown below.

Figure 7: Pattern Wizard window

Repeat the same procedure for X and Y. Only two values have to be changed – the

Toggle Every field and the Number of Cycles. For X, set the Number of Cycles value as 4 and Toggle Every value as 2. For Y, set the Number of Cycles value as 2 and Toggle Every value as 4. See the example of the final waveform assignment in Figure 8. Now in the HDL Bencher window, click on to save the waveform.

Figure 8: HDL Bencher with input assignment

After the waveform is saved to the waveform file (wave.tbw), we can simulate our

design. In the Sources in Project sub-window, click on the wave.tbw. If you can not find Processes for Source sub-window, click on Process View tab. In the sub-window Processes for Source, you will see 3 different ways to simulate your result using ModelSim: Simulate Behavioral VHDL Model, Generate Expected Simulation Results, and Simulate Post-Fit VHDL Model. We will explore different options in this project.

Figure 9: Processes for Source window

Double-click on the option Simulate Behavioral VHDL Model as shown below.

This will run ModelSim (this may take a while, so be patient!).

ModelSim will open with one main interface window and three other windows. The waveform will be displayed in the window named wave – default. Maximize this window and click on View → Zoom → Zoom Full to view the entire waveform. You can take printouts of the waveform by clicking on File → Print in your waveform window.

Figure 10: Simulate Behavioral VHDL Model ModelSim wave window

To answer the following questions, you will need to refer to the waveform. So read

through the questions and refer back to the waveform. After you have noted the answers for the questions, close all the windows of ModelSim.

Questions: 1. From the Behavioral simulation result, what is the output value for each combination of the inputs (draw the truth table)? Is it correct when compared to the Boolean equation derived from Figure 1 (Schematic Editor window)?

Now exit ModelSim and go back to the Xilinx Project Navigator window. Next, we will explore the relationship of delay and Post-Fit simulation. First, select the adder.sch in Sources in Project sub-window. Click on (+) in front of Implement Design in Processes for Sources sub-window. Right-click on Fit and select Properties… option.

Figure 11: Fit configuration

In Process Properties window, select Optimize Balance for Implementation Template. Click OK to return to Project Navigator window

Figure 12: Process Properties window

Repeat the simulation process by selecting wave.tbw in Sources in Project

sub-window. Selecting Simulate Post-Fit VHDL model in Processes for Sources sub-window. Print out the Post-Fit waveform and answer Questions 2 and 3. To note the exact time that the signals change you may need to zoom in. This can be done by clicking on the Zoom In button which looks like a magnifying glass with a plus (+) sign inside. The time value can be noted by clicking on the waveform at the desired location.

Questions: 2. From the Post-Fit simulation result, when you change one of the inputs, does the output change at the same time? (Note: Compare your result from the Behavioral waveform.) 3. What is the approximate delay (in ns) from the change in inputs to that in output Sum? (Note: From the Behavioral result (Figure 10), when is the first time output Sum changes in value? From the Post-Fit result, when is the first time that output Sum changes in value?) Drawing Circuits

In our final design, we will explore the behavior of a one-bit adder circuit with 3

inputs: X, Y, Cin and 2 outputs: Cout (carry-out) and Sum. Invoke the Schematic Editor by double-clicking on adder.sch in your Project

Navigator window or go back to it if you already have it running. You will be modifying your circuit by adding AND and OR gates to the circuit so that is it logically equivalent to the final design shown in Figure 16. You will need two 2-input AND gates named and2, and a 2-input OR gate named or2.

Figure 13: Symbol Categories window

In your Schematic Editor window, click on Add → Symbol. Expand the Symbols

sub-window. In the left side of your Schematic Editor window, under the sub-window called Categories, click on the entry Logic. Now click on the entry and2 under the Symbols sub-window. This will select a 2-input AND gate. To place the gate on the schematic, just click the mouse in the schematic sheet to place the part. Repeat this for the other gates by selecting the appropriate gates and placing them around approximately resembling the figure shown.

At this point the Schematic Editor expects you to place wires. You may move and

align the components before actually wiring them up. Press Esc and the mouse pointer will change to its normal shape. In this mode, you can drag schematic items with the mouse.

Try moving the components around the schematic sheet, zooming and panning as necessary.

Now you'll start wiring up most of the circuit. Press the button to enter the wiring mode. Begin a wire by clicking on one of the dangling wires of a device in the sheet, and terminate the wire by double-clicking on its destination. Wire the logic using this technique. Try it! You can delete a wire by selecting it and pressing the delete key. You can reroute a wire (sometimes with difficulty) by clicking and dragging it around.

You have to add an output Cout similar to the output Sum that already exists. In

Xilinx the inputs and outputs are called IO Markers. Click on the button. Expand the Options sub-window. Select the direction by clicking on Output in the Options tool bar.

Figure 14: Output Marker Options window

Now an output marker appears in your Schematic Editor. You will have to place the

output marker to directly coincide with the terminated end of your wire. You may need to zoom in on your schematic to do this. Once you have placed the output marker, you will have to change its name from the Xilinx default name to Cout. You can do this by right-clicking on the output marker and then select Rename Port.

Figure 15: Object Properties window

Before you save your changes and start the simulator, you need to check the circuit. Click on Tools → Check Schematic. If there are errors, they will be displayed in the Schematic Check Errors window. If there are no errors, then the Error Msg will display No Errors Detected.

Double-click on the text Name Lastname in the schematic sheet and a dialog box

for Object Properties will come up. Now change the name from Name Lastname to your name and click OK. Save your design. Get a print out of your new circuit for your report.

Figure 16: Final Design

Final Simulation

Simulate and print your final waveform from Simulate Behavioral VHDL Model. You should simulate the circuit with the same inputs as you had specified the last time.

Now you can see that both Behavioral and Post-Fit simulation take some time.

What can we do if we have complicated designs? Would it take forever to debug it? In general, use Generate Expected Simulation Results to test your new design. Double-click on Generate Expected Simulation Results from the Processes for Source menu as you did before. To try different input stimulus, you have to change the wave.tbw file. To do this, double-click on the wave.tbw from the Project Navigator window. The waveform opens up in the HDL Bencher window. To change the value of an input, just click on the blue regions in the input wave at any time instant and the value will get flipped. i.e., if it was previously a 1, it becomes a 0 after clicking and vice-versa.

Also, try to slide the Set end of the testbench bar while you are testing your design.

While you are repeatedly simulating the design, the simulator may ask whether you want to Back Annotation. Answer No. Remember to exit ModelSim before starting new simulation.

Report

• Answers to the questions (1-3)

• Printout of the Behavioral and Post-Fit waveform outputs from the simulation of the first circuit.

• Printout of the final design schematic circuit. (Figure 16)

• Printout of the Behavioral waveform output from the simulation of the final circuit.