EE/CS 480/481

104/20/23 06:05 PM University of Portland School of Engineering

Project YewInline Power Monitor with Cost

Analysis

TeamZubin Bagai

Kevin Eldrige

Jon Worley

AdvisorDr. Robert Albright

Dr. Peter Osterberg

Industry RepresentativeMr. John M. Haner, B.P.A.

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Overview

• Introduction

• Functional Diagrams

• Scorecard

• Additional Accomplishments

• Plans

• Issues/Concerns

• Conclusions

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ACPower

Sensing

Data Processing

Actuate Display

Prototype

Device

User Input

Display

University of Portland School of Engineering

Introduction

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Current Sensor

Voltage Sensor

MOSIS Chip

Keypad Input

5V DC Power Supply

LCD Display

PIC Microcontroller

Top Level Functional Block Diagram

Component Level Block Diagram

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Power Sensing Functional Diagram

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1

9

2

10

RA[0...5]

VoltageCurrent

1

9

2

10

RE[0..7]

1 9

2 10

RB

[0..7

]

1

9

2

10

RD[0..7]

+5 VDC

10k

DB0

LCD

DB1

DB2

DB3

DB4

DB5

DB6

DB7

RS

E

VDD

Vo

R/W_L

VSS

A

K

LCD Datasheet does not mention anything about connecting a capacitor between VDD and R/W_L nor does it

mention connecting a resistor between Vo and R/W_L. EE 433_Lab2 had the extra components mentioned above

220ohm

220ohm

220ohm

220ohm

Hours (5 bits)

1

9

2

10

RJ[0..7]

Maximum Price (8 bits)

1

9

2

10

RF[0..7]

Present Price (8 bits)

1

9

2

10

RC[0..7]

Minutes: b6-b4 = 10's place, b3-b0 = 1's place(7 bits)

Phantom Utility Signal

PIC Register Diagram

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PIC Macro-Model

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MOSIS

text

PIC

8 bit Present Price

8 bit Max Price

1 bit Clock

1 bit Reset

7 bit Minutes

5 bit Hours

3 bit Relay Control

8 Bit Comparator

24 Hour Counter

A

B

A>B

A=B

A<B

Reset

Reset

Clock

Minutes

Hours

text

text

Relay

MOSIS Functional Diagram

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CPLD

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Voltage Waveforms

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Scorecard

• PIC macro-model built

• Rebuilt sensor circuit

• Measured voltage from socket through PIC

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Completed Shortcomings•Voltage Divider circuit gave unexpected values

•Zubin was out for two weeks

•CPLD returns unexpected values

•Relay broke

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Additional Accomplishments

• We were able to get accurate A/D conversion from PIC– Sent voltages in, to get binary representations

out

• Got power supply working

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Plans

• Finish programming PIC

• Get our current sensor values in and out of the PIC

• Complete integration of components

• Test and debug entire circuit

• Get and test MOSIS with circuit

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Milestones

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Number Description Original 11 Dec 09

Previous26 Jan 10

Present23 Feb 10

19 Power Sensor Circuits Built 1/26/10 1/26/10 1/26/10

20 January Program Review 1/26/10 1/26/10 1/26/10

21 CPLD Programmed and Tested 1/31/10 1/26/10 1/26/10

22 Test Power Sensor with CPLD 2/12/10 2/12/10 2/12/10

23 PIC Programmed and Tested 2/19/10 2/19/10 2/28/10

24 February Program Review 2/23/10 2/23/10 2/23/10

25 System Integration Complete 2/26/10 2/26/10 3/5/10

26 Finish System Testing with CPLD(s) 3/5/10 N/A 3/5/10

27 Spring Break 3/8/10 N/A 3/8/10

28 Receive MOSIS Chip and Test in System 3/15/10 N/A 3/15/10

29 Implementation of Any Additional Features 3/19/10 N/A 3/19/10

30 System Testing Complete 3/26/10 N/A 3/26/10

31 March Program Review & Demo 3/30/10 N/A 3/30/10

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Concerns/Issues

• CPLD clock error• Solution: further test bug

• Backup: Use PIC internal timers

• System integration was delayed• Solution: Schedule more hours each week to catch

up

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Conclusions

• Project Yew is an Inline Power Monitor

• Bugs were found but progress was made

• Plans have been made to catch up

• Revise voltage measurement

• System integration is our next target

• Questions?

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