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EE584 (Fall 2006)
Introduction to VLSI
CAD Project
Design of Ring Oscillator using NOR gates
By,
Veerandra Alluri
Vijai Raghunathan
Archana Jagarlamudi
Gokulnaraiyn Ramaswami
Instructor: Dr. Joseph Elias
Table of Contents
1) Introduction .................................................................................................................... 4
2) The Ring Oscillator ........................................................................................................ 4
3) The Design...................................................................................................................... 5
3.1) Design of Ring Oscillator ............................................................................................ 5
3.2) The Enable circuit........................................................................................................ 6
3.3) ESD Protection Circuit ................................................................................................ 6
3.4) Output Buffer............................................................................................................... 7
4) Schematics ...................................................................................................................... 9
5) Corner Testing .............................................................................................................. 11
Why corner testing? .................................................................................................. 11
6) Layout........................................................................................................................... 19
6.1) Few points on the ring oscillator’s layout drawing ........................................... 19
6.2) Few points on the output buffer’s layout drawing............................................. 21
7) Sweet/Bitter Experiences.............................................................................................. 22
8) Conclusion .................................................................................................................... 23
References......................................................................................................................... 23
Table of Figures
Figure 1 – 5 Stage Ring Oscillator...................................................................................... 4
Figure 2 – 35 Stage NOR Ring Oscillator .......................................................................... 6
Figure 3 – Enable Circuit .................................................................................................... 6
Figure 4 – ESD Protection Circuit ...................................................................................... 7
Figure 5 – Output Buffer..................................................................................................... 7
Figure 6 – Output Buffer Circuit ........................................................................................ 8
Figure 7 – Overall Block Diagram...................................................................................... 9
Figure 8 – Enable Schematic .............................................................................................. 9
Figure 9 – Ring Oscillator Schematic............................................................................... 10
Figure 10 – Output Buffer Schematic............................................................................... 10
Figure 11 – Slow slow Simulation plot............................................................................. 12
Figure 12 – Typi typi Simulation Plot .............................................................................. 12
Figure 13 – Fast fast Simulation plot................................................................................ 13
Figure 14 – Slow Simulation Plot for 25 C....................................................................... 14
Figure 15 – Typi Simulation Plot for 25 C ....................................................................... 14
Figure 16 – Fast Simulation Plot 25 C.............................................................................. 15
Figure 17 – Slow Corner Simulation Surface Plot............................................................ 15
Figure 18 – Typi Corner Simulation Surface Plot ............................................................ 16
Figure 19 – Fast Corner Simulation Surface Plot ............................................................. 16
Figure 20 – Overall Corner Simulation Surface Plot (Vdd = 1.8 V) ................................ 17
Figure 21 – Overall Corner Simulation Surface Plot (Temperature = 25 C).................... 18
Figure 22 – Ring Oscillator Layout .................................................................................. 20
Figure 23 – Enable Circuit Layout.................................................................................... 20
Figure 24 – Output Buffer Layout .................................................................................... 21
Figure 25 – Overall Circuit inside bounding box ............................................................. 22
1) Introduction
The ring oscillator is a circuit used to calculate time delays in circuits and thereby help
measuring the speed of a technology being developed. Since it is an oscillator it can also
be used to clock other digital circuits. Designing a ring oscillator using NOR gates was
the main goal of this project. Some other essential components like an enable circuit and
an output buffer were also designed. The project dealt with a lot of learning, and
understanding of VLSI concepts and practically implementing many ideas.
2) The Ring Oscillator
The ring oscillator is a digital circuit consisting of many stages of inverters in series,
where the number of stages is always odd. Figure 1 shows a simple five stage ring
oscillator. When a digital 1 or a 0 is at the input of the first stage, it traverses through all
the stages with alternate 1’s and 0’s at the output of every adjacent stage. As it has odd
number of stages, the logic at the output is always the compliment of the input at the first
stage and this output is fed back to the input thereby enabling oscillations. The time
period for which the output is high or low is directly equal to the time delay (propagation
delay) the signal experiences in traveling from the first stage to the last stage. Hence the
period of the output waveform would be twice the time delay ideally.
1
Figure 1 – 5 Stage Ring Oscillator
1 Page 339, CMOS Circuit Design, Layout and Simulation by R. Jacob Baker
3) The Design
The primary focus would be to create a ring oscillator. The number of stages would
depend on the delay one is expecting to get from the circuit. It should be noted that the
circuit designed would be tested using an oscilloscope. A typical oscilloscope measures a
frequency of about 100 MHz which corresponds to a time period of 10 ns. So under
typical conditions it was decided to have a time delay of 15 ns, meaning a high time of
15ns and a low time of 15ns and hence a time period of about 30ns. This waveform can
be easily measured in any standard oscilloscope. The motive was to design a ring
oscillator with minimum number of stages and so the delay induced by each stage should
be as high as possible. Hence the width of the transistors used in constructing the NOR
gate should be minimum as larger width would result in more current flow reducing the
delay in each stage. Also to have equal rise and fall times, the width of the PFET would
have to be more than that of the width of the NFET to compensate for the different trans-
conductance of electrons and holes. So the widths of all the PFETs were twice as that of
the NFETs. After running a few trial simulations with NOR gates having minimum
widths, it was observed that a 35 stage Ring oscillator using NOR gates would result in
the desired time delay.
Designing just a ring oscillator might not be enough as there are other things to be taken
care of. The ring oscillator is a self starting oscillator and there must be a way to stop the
oscillations whenever necessary. Hence an enable circuit is required to turn on and off the
oscillator. Similarly the circuit needs protection from any kind of static discharge induced
during testing. Hence an ESD (electro-static discharge) protection circuit is needed.
Finally the ring oscillator must be able to drive some load. Since the circuit is designed
for testing purposes, the load is taken as the oscilloscope. Keeping this load in mind, an
output buffer circuit is also designed. These circuits are explained one after the other in
the following sections.
3.1) Design of Ring Oscillator
The objective is to create an inverter using a NOR gate. When the inputs of a NOR gate
are shorted, there is only input and one output. Now the NOR gate behaves like an
inverter. Thirty five such NOR gates were put in series to create the ring oscillator as
shown in Figure 2. The ratios of the widths of PFET to the widths of NFET are shown
above each NOR gate.
Figure 2 – 35 Stage NOR Ring Oscillator
3.2) The Enable circuit
The enable circuit was taken from CMOS Circuit Design, Layout and Simulation by R.
Jacob Baker. It is shown in Figure 3. It is a tri-state buffer where when the enable input is
1, the input goes to the output and when it is 0, the input is cut from the output and the
output is a high impedance state.
2
Figure 3 – Enable Circuit
3.3) ESD Protection Circuit
The ESD protection circuit is shown in Figure 4. “Diodes D1 and D2 are used to clamp
the input signal to within 0.7 V of VDD or ground. The resistor R is used to further
minimize any input current in the event D3 breaks down or conducts. The resistor is
usually realized by a long n+ diffusion region that might surround the contact pad.”3
2 Page 372, CMOS Design, Layout and Simulation by R. Jacob Baker
3 Page 274-275, Digital Integrated Circuit Design by Ken Martin
4
Figure 4 – ESD Protection Circuit
3.4) Output Buffer
As mentioned in the design, the circuit must be able to drive a load. In this case the load
is assumed to be the oscilloscope. After going through a few datasheets of some
oscilloscopes, it was found that the oscilloscope usually has a load comprising of a
capacitor 20pF and a resistance of 1 mega ohm. So the ring oscillator must be able to
drive it and hence we need an output buffer. The design of the output buffer is got from
CMOS Design, Layout and Simulation by R. Jacob Baker and is shown in Figure 5. The
explanation given is “Consider the inverter string (a buffer) driving a load capacitance,
labeled Cload and shown in Figure 5. Moving towards the load in a cascade of the N
inverters, each inverter larger than the previous by a factor A (that is the width of each
MOSFET is multiplied by A), a minimum delay can be obtained as long as A and N are
picked correctly. Each inverter’s input capacitance is larger than the previous inverter’s
input capacitance by a factor of A.” 5
The equations for designing the circuit are as follows:
N=ln(Cload/Cin1) and A=(Cload/Cin1)(1/N) 6
Cin1 is the input capacitance of the first stage inverter.
7
Figure 5 – Output Buffer
4 Page 274, Digital Integrated Circuit Design by Ken Martin
5 Page 344, CMOS Design, Layout and Simulation by R. Jacob Baker
6 Page 344-345, CMOS Design, Layout and Simulation by R. Jacob Baker
7 Page 344, CMOS Design, Layout and Simulation by R. Jacob Baker
The first inverter is assumed to have p-width/n-width of 2.10/1.05. The Cin1 value is
obtained by finding the Coxp and Coxn for the PFET and NFET.
Cin1=3/2*(Coxp+Coxn)
Coxp= Coxp1*W*L*(scale)
2 8
Coxn= Coxn1*W*L*(scale)
2 9
Where,
Cox1 is got from Table 6.4, CMOS Circuit Design, Layout and Simulation by R. Jacob
Baker
W – Width of the transistor
L – Length of the transistor
Scale – 50 nm (all parameters multiplied by scale to get actual values)
Solving all the above equations the value is N is obtained as 10 and value of A as ‘e’. If
N is 10 then the widths of the PFET and NFET for the 10th
stage would be very large and
difficult to implement in layout. So the buffer is stopped with just 9 stages as this would
be good enough, if not the best to drive our desired load. There is a stage before the first
stage of the actual buffer circuit. This inverter is added to make the total number of stages
even so that the output of the ring oscillator appears exactly at the load. If there are 9
stages then the output at the load would be the inverted version of the output of the ring
oscillator. This design is shown in Figure 6. The widths of the PFET/NFET are given
above each stage.
Figure 6 – Output Buffer Circuit
8 Figure 6.5, CMOS Circuit Design, Layout and Simulation by R. Jacob Baker
9 Figure 6.5, CMOS Circuit Design, Layout and Simulation by R. Jacob Baker
The overall design is shown in Figure 7.
Figure 7 – Overall Block Diagram
4) Schematics
Once the design has been decided, the next thing to do would be to draw the schematic.
This was successfully done using the Cadence software. Some of the snapshots from
Cadence are included below.
Figure 8 shows the schematic of the enable circuit, Figure 9 shows the ring oscillator
structure without any feedback, Figure 10 shows the output buffer with the series of
inverters, and Figure 10 shows the ESD protection circuit.
Figure 8 – Enable Schematic
Figure 9 – Ring Oscillator Schematic
Figure 10 – Output Buffer Schematic
5) Corner Testing
Once the schematics of the various circuits are drawn, the most important thing is to
make sure that the design actually works. Often, system being designed might not work
properly and if the layout for such a design is made then it would be a total waste of time
and money. So, the only way to avoid that is to run simulations and check if the desired
results appear. So, simulations are carried out in various temperatures to see how the
output varies with temperature.
Often in digital circuit the input voltage fluctuates a little mainly due to noise in the
power lines. So the design must be tested under these conditions also. Usually the voltage
variation is within 10% of its actual value. So the voltage was varied in this 10% range
and the corresponding changes in the output were noted.
While conducting simulations, the design has to be tested in various ‘corners’. Extreme
conditions in which the design is put to test are usually called ‘corners’. In this case the
extreme conditions are ‘fast’ and ‘slow’, and these are achieved by varying certain
internal parameters like oxide thickness. The ‘fast’ corner refers to the case where the
current flow and switching speed are very fast, while the ‘slow’ corner refers to slower
current flow and switching speed. There is also the presence of a ‘typi’ condition in
which all the internal parameters are set to typical values.
Why corner testing?
Often during the process of manufacturing the desired circuit, certain internal parameters
might change a little. There might be a slight deviation in these parameters from the
typical values. For instance, during the process of manufacturing the oxide thickness
might change by couple of nanometers. This change might induce a lot of variations in
the output generated by the design. So to make sure that the design is stable even at the
corners, corner simulations are conducted. These simulations also give the designer an
idea of whether his/her design would work in all the conditions and if it does not work,
why it does not work and under what conditions it does not work. So it is an useful tool to
analyze the design.
Some of the simulation results are shown below.
Figure11 shows the variation of time period (the time delay) with respect to temperature
for various voltages in the slow corner. From the plot, it is evident that for a particular
voltage, as temperature increases the time delay decreases. This phenomenon is present
for even the fast corner and the typical conditions as shown in Figures 12 and 13.
But it has to be observed that for a given temperature and voltage, as the simulation
environment varies from slow to fast, the time delay decreases. This is very much in line
with the expected results.
Slow_Slow Simulation
0
200
400
600
800
1000
1200
1400
-100 -50 0 50 100 150
Temperature (C)
Tim
e P
eri
od (ns)
1.8V
1.82V
1.86V
1.9V
1.94V
1.98V
1.74V
1.7V
1.66V
1.62V
Figure 11 – Slow slow Simulation plot
Typi_Typi Simulation
0
20
40
60
80
100
120
140
160
180
-100 -50 0 50 100 150
Temperature (C)
Tim
e P
eri
od (ns)
1.62V
1.7V
1.8V
1.9V
1.98V
Figure 12 – Typi typi Simulation Plot
fast_fast Simulation
0
5
10
15
20
25
30
35
40
45
-100 -50 0 50 100 150
Temperature (C)
Tim
e P
eriod (ns)
1.62V
1.66V
1.7V
1.74V
1.8V
1.82V
1.86V
1.9V
1.94V
1.98V
Figure 13 – Fast fast Simulation plot
Though it was not very necessary to plot the relation between voltage and time period for
a constant temperature, it was plotted to give a better understanding of certain concepts.
Figure 14 shows the plot between voltage and time period for a constant temperature of
25C in the slow corner, Figure 15 shows the same plot under typical conditions and
Figure 16 shows the same plot in the fast corner.
It can be observed that for a constant temperature, as the voltage increases the time delay
decreases. This is in accordance with the fact that more voltage could drive more current
through a device. As current through the device increases the time delay induced
decreases because the input capacitance of the device is charged and discharged faster.
The reduction in time delay with change in the corner from slow to fast can also be
observed (for a constant temperature and voltage).
Slow 25C
0
50
100
150
200
250
0 0.5 1 1.5 2 2.5
Voltage (V)
Tim
e P
eri
od (ns)
25C
Figure 14 – Slow Simulation Plot for 25 C
Typi 25C
0
10
20
30
40
50
60
70
0 0.5 1 1.5 2 2.5
Voltage (V)
Tim
e P
eri
od (ns)
25C
Figure 15 – Typi Simulation Plot for 25 C
Fast 25C
0
5
10
15
20
25
0 0.5 1 1.5 2 2.5
Voltage (V)
Tim
e P
eri
od (ns)
25C
Figure 16 – Fast Simulation Plot 25 C
Figures 17, 18 and 19 show the combined result of voltage, temperature and time period
in the same surface plot for slow corner, typical condition and fast corner
1.62
1.8
1.94
-55
-35
-15 5 25 45 65 85
105
125
0
200
400
600
800
1000
1200
1400
Time period(ns)
voltage(V)
Temperature(c)
'slow' Corner Simulations
1200-1400
1000-1200
800-1000
600-800
400-600
200-400
0-200
Figure 17 – Slow Corner Simulation Surface Plot
-55
85
1.6
2 1.7 1.8 1
.9 1.9
8
0
50
100
150
200
Period(ns)
Temperatu
re(c)Voltage(V)
'Typi' Corner Simulations
150-200
100-150
50-100
0-50
Figure 18 – Typi Corner Simulation Surface Plot
1.6
2
1.7
1.8
1.8
6
1.9
4
-55
-35
-15 5 25 45 65 85
105
125
0
5
10
15
20
25
30
35
40
45
time period(ns)
voltage(V)
temperature(c)
'fast' Corner Simulation
40-45
35-40
30-35
25-30
20-25
15-20
10-15
5-10
0-5
Figure 19 – Fast Corner Simulation Surface Plot
Figures 20 and 21 show the overall result of all the simulations that were conducted.
Figure 20 shows the variation of time period with the variation in temperature for each of
the three corners, at a constant voltage.
-55
85
slo
w_slo
w
typi_
typi
fast_
fast
0
50
100
150
200
250
300
Time Period (ns)
Temperature
(c)
Corner Simulation (VDD = 1.8V)
250-300
200-250
150-200
100-150
50-100
0-50
Figure 20 – Overall Corner Simulation Surface Plot (Vdd = 1.8 V)
Figure 21 shows the variation of time period with variation in voltage for all the corners
at a constant temperature.
1.62
1.8
1.98
slo
w_slo
w
typi_
typi
fast_
fast
0
50
100
150
200
250
Time period (ns)
Voltage (V)
Corner Simulation(Temp = 25 c)
200-250
150-200
100-150
50-100
0-50
Figure 21 – Overall Corner Simulation Surface Plot (Temperature = 25 C)
The following two tables show the data that were used to plot the surface plots in Figure
20 and 21.
Voltage = 1.8V Time Period (ns) Temperature© slow_slow Typi_typi Fast_fast
-55 265.235 56.42 20.93
25 88.029 30.84 15.41
85 56.916 23.93 13.16
125 45.873 21.05 12.11
Temperatre = 25C Time Period (ns) Voltage (V) slow_slow Typi_typi Fast_fast
1.62 227.381 58.1 23.65
1.7 141.842 41.65 19.15
1.8 88.029 30.84 15.41
1.9 60.765 24.11 12.86
1.98 47.473 20.37 11.34
After going through the simulations it was observed that the design worked well in all the
simulation corners, as per the predicted results. But it should be noted that in the fast
corner, when the temperature range is high, then the design’s output cannot be viewed in
an oscilloscope as the time period reduces below 10 ns, especially for voltages from 1.8V
onwards.
Similarly the time delay increases a lot in the slow corner especially when the
temperatures are low and voltages are also less. One would not prefer operating the
device in that range.
6) Layout
After the simulations have been conducted successfully, it is known that the designed
circuit works and it can be implemented. So the next task would be to draw the layout
and make sure the layout passes all the software design rules. Figure 17 is the snapshot of
the layout of the ring oscillator, Figure 18 is the snapshot of the layout of the enable
circuit, Figure 19 is the snapshot of the layout of the output buffer and Figure 20 shows
the layout of the entire circuit inside the bounding box.
6.1) Few points on the ring oscillator’s layout drawing
While drawing the basic NOR layout used in the ring oscillator (RO), it was made sure
that input and output lines were extended such that they don’t go beyond the N well. This
is done to make sure that metal is not used again to join them.
The ring oscillator’s layout was done making use of rows and columns available in the
instance tool box.
Metal crossing was eliminated by routing metal1 to licon and crossing it over another
metal1.
Figure 22 – Ring Oscillator Layout
Figure 23 – Enable Circuit Layout
Figure 24 – Output Buffer Layout
6.2) Few points on the output buffer’s layout drawing
A primary inverter cell was created using a “ptran” and “ntran” with the corresponding
widths and lengths. The area of the bounding box was considered (2700*125 micro-
meters) and the values of the cascaded stage’s areas were decided so as to fit into this.
The maximum resolution in Cadence (0.025) was used. It was found that every stage
except for the last stage was very small compared to the area between any two e-pads.
The last stage had a large length (not channel length) such that it could only fit between 2
e-pads if placed perpendicular to the long sides of the bounding box. Since there is no
restriction on placing the last stage in the bounding box (considering facts like
connections to VDD and GND and there is only one output connection), it was placed
between the two most extreme e-pads on one side of the bounding box. As the rest of the
stages are small they could be moved closer to the longer sides of the bounding box along
which the power buses were placed.
Since there was only one connection between the last stage and the remaining circuit, a
whole e-pad was used as a junction rather than routing, which causes parasitic and waste
metal. For a CMOS inverter, it is simple to bring the input and the output terminals on
either side of the inverter. This fact was used to simplify interconnecting stages.
Strapping was done till the met1 layer for the following reasons.
Met1 is the lowest layer that can be used to interconnect devices through low resistance.
Also LI has severe DRC restrictions regarding the proximity to diff areas.
Length of met1 contacts on transistors made it easy to connect a power ‘bar’
perpendicular to them to it, and in most cases no metal patches were created to connect
the power bar to met1 contacts from transistors.
There is no need to rise the routing to met2 unless there is a crossing of two met1 routes.
In such cases it was used.
Figure 25 – Overall Circuit inside bounding box
7) Sweet/Bitter Experiences While doing the project, there were a lot of good experiences and some bad ones too. The
good experiences are as follows.
• The prescribed book “CMOS Circuit Design, Layout and Simulation” by R. Jacob
Baker was very useful while designing the entire circuit.
• In Cadence software, the “tech” library had pre-defined schematic and symbols
for the inverter, two input NAND, and NOR. These symbols were directly used in
the design and it saved a lot of time and work.
• While running simulations, there was this option called ‘parametric testing’ which
eased the simulation process as the simulation could be made to run with a
variation in many parameters in a single run.
• The m-factor option in Cadence software for the transistor folding was very
helpful especially for the layout as the dimensions of the transistor could be
suitably varied in order to make it fit inside the bounding box.
The bad experiences are as follows.
• Even though the parametric analysis was a useful tool, it was extremely slow in
producing the final result and sometimes it failed to produce the result, especially
when the temperature was negative.
• The drawing of the layout was very tough and there were a lot of errors
encountered while trying to pass through the design rules. Some of these errors
were due to minimum spacing between nwells, between nwell and diff, between
poly and poly, met1 and met1. Drawing the layout required a lot of patience and
concentration, as the design rules had to be passed and several other factors such
as minimizing the layout area, having less resistance while routing and so on had
to be considered.
8) Conclusion
The various steps involved in the project are as follows.
• First, a suitable design with all the circuits was chosen and it was decided to
implement the design.
• Then, the schematic of the various components in the design were drawn and then
connected properly.
• Next, to make sure that the design was proper and would work correctly, a lot of
simulations were performed based on the schematic.
• Once the simulations yielded good acceptable results, the layout for the design
was drawn.
• The layout was made to pass all the required design rules and LVS successfully.
The project provided an opportunity to learn how the various parameters and settings
actually influenced the design. It also provided information on how different kinds of
inputs yielded different outputs. A lot of practical problems were analyzed while
performing the various tests and simulations. The project was a good learning experience.
References
• CMOS Circuit Design, Layout and Simulation by R. Jacob Baker.
• Digital Integrated Circuit Design by Ken Martin.
• www.engr.uky.edu/~elias/index_584.html
• Www.tex.com
