EE415 VLSI Design1

The WireThe Wire

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design2

The WireThe Wire

transmitters receivers

schematics physical

EE415 VLSI Design3

Interconnect Impact on ChipInterconnect Impact on Chip

EE415 VLSI Design4

Wire ModelsWire Models

All-inclusive model Capacitance-only

EE415 VLSI Design5

Impact of Interconnect ParasiticsImpact of Interconnect Parasitics

Interconnect parasitics reduce reliability affect performance and power

consumption Classes of parasitics

Capacitive Resistive Inductive

EE415 VLSI Design6

10 100 1,000 10,000 100,000

Length (u)

No

of

net

s(L

og

Sca

le)

Pentium Pro (R)

Pentium(R) II

Pentium (MMX)

Pentium (R)

Pentium (R) II

Nature of InterconnectNature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnology

SGlobal = SDie

So

urc

e:

Inte

l

EE415 VLSI Design7

INTERCONNECTINTERCONNECT

EE415 VLSI Design8

Wiring CapacitanceWiring Capacitance The wiring capacitance depends upon the length

and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates.

Wiring capacitance is growing in importance with the scaling of technology.

EE415 VLSI Design9

Capacitance of Wire InterconnectCapacitance of Wire Interconnect

VDD VDD

VinVout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CL

SimplifiedModel

EE415 VLSI Design10

Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate Model

Dielectric

Substrate

L

W

H

tdi

Electrical-field lines

Current flow

WLt

cdi

diint

LLCwire SSS

SS

1

EE415 VLSI Design11

Permittivity Values of Some DielectricsPermittivity Values of Some Dielectrics

3.1 – 3.4Polyimides (organic)

2.1Teflon AF

11.7Silicon

9.5Alumina (package)

7.5Silicon nitride

5Glass epoxy (PCBs)

3.9 – 4.5Silicon dioxide

2.6 – 2.8Aromatic thermosets (SiLK)

1.5Acrogels

1Free space

diMaterial

EE415 VLSI Design12

Fringing CapacitanceFringing Capacitance

W - H/2H

+

(a)

(b)

EE415 VLSI Design13

Fringing versus Parallel PlateFringing versus Parallel Plate

(from [Bakoglu89])

H/TH/T

W/T

HT

EE415 VLSI Design14

Sources of Interwire CapacitanceSources of Interwire CapacitanceCwire = Cpp + Cfringe + Cinterwire

= (di/tdi)WL

+ (2di)/log(tdi/H)

+ (di/tdi)HL

interwire

fringe

pp

W W

W

H

H

H

tdi

tdi

tdi

EE415 VLSI Design15

Impact of Interwire CapacitanceImpact of Interwire Capacitance

(from [Bakoglu89])

EE415 VLSI Design16

Wiring CapacitancesWiring CapacitancesField Active Poly Al1 Al2 Al3 Al4

Poly 88

54

Al1 30 41 57

40 47 54

Al2 13 15 17 36

25 27 29 45

Al3 8.9 9.4 10 15 41

18 19 20 27 49

Al4 6.5 6.8 7 8.9 15 35

14 15 15 18 27 45

Al5 5.2 5.4 5.4 6.6 9.1 14 38

12 12 12 14 19 27 52

fringe in aF/m

par. plate in aF/m2

Poly Al1 Al2 Al3 Al4 Al5

Interwire Cap 40 95 85 85 85 115

per unit wire length in aF/m for minimally-spaced wires

EE415 VLSI Design17

Dealing with CapacitanceDealing with Capacitance Low capacitance (low-k) dielectrics (insulators)

such as polymide or even air instead of SiO2

family of materials that are low-k dielectrics must also be suitable thermally and mechanically and compatible with (copper) interconnect

Copper interconnect allows wires to be thinner without increasing their resistance, thereby decreasing interwire capacitance

SOI (silicon on insulator) to reduce junction capacitance

EE415 VLSI Design18

INTERCONNECTINTERCONNECT

EE415 VLSI Design19

Wire ResistanceWire Resistance

L

W

H

R = L

H WSheet Resistance R

R1 R2=

=

L

A=

Material (-m)

Silver (Ag) 1.6 x 10-8

Copper (Cu) 1.7 x 10-8

Gold (Au) 2.2 x 10-8

Aluminum (Al) 2.7 x 10-8

Tungsten (W) 5.5 x 10-8

Material Sheet Res. (/)

n, p well diffusion 1000 to 1500

n+, p+ diffusion 50 to 150

n+, p+ diffusion with silicide

3 to 5

polysilicon 150 to 200

polysilicon with silicide

4 to 5

Aluminum 0.05 to 0.1

EE415 VLSI Design20

Sources of ResistanceSources of Resistance

MOS structure resistance - Ron

Source and drain resistance Contact (via) resistance Wiring resistance

Top view

Drain n+ Source n+

W

L

Poly Gate

EE415 VLSI Design21

Contact ResistanceContact Resistance Via’s add extra resistance to a wire

keep signals wires on a single layer if possible avoid excess contacts using multiple vias to make the contact

Typical contact resistances, RC,

5 to 20 for metal or poly to n+, p+ diffusion and metal to poly

2 to 20 for metal to metal contacts More pronounced with scaling since contact

openings are smaller

EE415 VLSI Design14: Wires22

Contacts ResistanceContacts Resistance

Use many contacts for lower R Many small contacts for current crowding

around periphery

EE415 VLSI Design23

Skin EffectSkin Effect At high frequency, currents tend to flow on the surface of a

conductor with the current density falling off exponentially with depth into the wire

H

W= (/(f)) where f is frequency = 4 x 10-7 H/m

so the overall cross section is ~ 2(W+H)

= 2.6 m for Al at 1 GHz

The onset of skin effect is at fs - where the skin depth is equal to half the largest dimension of the wire.

fs = 4 / ( (max(W,H))2) An issue for high frequency, wide (tall) wires (i.e., clocks!)

EE415 VLSI Design24

Skin Effect for Different W’sSkin Effect for Different W’s

A 30% increase in resistance is observe for 20 m Al wires at 1 GHz (versus only a 1% increase for 1 m wires)

0.1

1

10

100

1000

Frequency (Hz)

% I

ncr

ease

in R

esi

stance

W = 1 um

W = 10 um

W = 20 um1E8 1E9 1E10

for H = .70 um

EE415 VLSI Design25

Dealing with ResistanceDealing with Resistance

Selective Technology Scaling Use Better Interconnect Materials

e.g. copper, silicides More Interconnect Layers

reduce average wire-length

EE415 VLSI Design26

Polycide Gate MOSFETPolycide Gate MOSFET

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi 2, TiSi2, PtSi2 and TaSi

Conductivity: 8-10 times better than Poly

EE415 VLSI Design27

Modern InterconnectModern Interconnect

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Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process

5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric

EE415 VLSI Design29

InterconnectInterconnectModelingModeling

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The Lumped ModelThe Lumped Model

Vout

Driver

cwire

VinClum pe d

RdriverVout

EE415 VLSI Design31

The Lumped RC-ModelThe Lumped RC-ModelThe Elmore DelayThe Elmore Delay

To model propagation delay time along a path from thesource s to destination i considering the loading effect of the other nodes on the path from s to k

The shared path resistance Rik

The Elmore delay

s

EE415 VLSI Design32

The Ellmore DelayThe Ellmore DelayRC ChainRC Chain

EE415 VLSI Design33

Wire ModelWire Model

Assume: Wire modeled by N equal-length segments

For large values of N:

EE415 VLSI Design34

The Distributed RC-lineThe Distributed RC-line

EE415 VLSI Design35

Step-response of RC wire as a Step-response of RC wire as a function of time and spacefunction of time and space

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

volta

ge (V

)

x= L/10

x = L/4

x = L/2

x= L

EE415 VLSI Design36

RC-ModelsRC-Models

EE415 VLSI Design37

Driving an RC-lineDriving an RC-line

Vi n

Rs Vo ut

(rw,cw,L)

EE415 VLSI Design38

Design Rules of ThumbDesign Rules of Thumb

rc delays should only be considered when tpRC >> tpgate of the driving gate

Lcrit >> tpgate/0.38rc rc delays should only be considered when the

rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line

trise < RC otherwise, the change in the input signal is slower

than the propagation delay of the wire