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•VLSI Design I; A. Milenkovic •1
CPE/EE 427, CPE 527 VLSI Design I
L04: MOS Transistor
Department of Electrical and Computer Engineering University of Alabama in Huntsville
Aleksandar Milenkovic ( www. ece.uah.edu/~milenka )www. ece.uah.edu/~milenka/cpe527-03F
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
9/8/2003 VLSI Design I; A. Milenkovic 2
Course Administration
• Instructor: Aleksandar [email protected]/~milenkaEB 217-LOffice Hrs: MW 17:30-18:30
• TA: Fathima Tareentareenf @eng.uah.eduOffice Hrs:
• Labs: Accounts on 246 machines• URL: http://www.ece.uah.edu/~milenka/cpe527-03F• Text: Digital Integrated Circuits, 2nd Edition
Rabaey et. al., ©2002 (October)
9/8/2003 VLSI Design I; A. Milenkovic 3
Review: CMOS Process at a Glance
Define active areasEtch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
• One full photolithographysequence per layer (mask)
• Built (roughly) from the bottom up5 metal 2
4 metal 12 polysilicon
3 source and drain diffusions
1 tubs (aka wells, active areas)
exception!
•VLSI Design I; A. Milenkovic •2
9/8/2003 VLSI Design I; A. Milenkovic 4
Review: Simplified CMOS Inverter Process
cut line
p well
9/8/2003 VLSI Design I; A. Milenkovic 5
Review: Intra-Layer Design Rules
Metal2 4
3
10
90
Well
Active3
3
Polysilicon2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select2
or6
2Hole
9/8/2003 VLSI Design I; A. Milenkovic 6
Review: Inter-Layer Design Rule Origins
1. Transistor rules – transistor formed by overlap of active and poly layers
Transistors
Catastrophic error
Unrelated Poly & Diffusion
Thinner diffusion,but still working
•VLSI Design I; A. Milenkovic •3
9/8/2003 VLSI Design I; A. Milenkovic 7
Review: Vias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
9/8/2003 VLSI Design I; A. Milenkovic 8
Learn more about fabrication
• http://www. leb.e-technik.uni-erlangen.de/ lehre/mm/html/start.htm
9/8/2003 VLSI Design I; A. Milenkovic 9
Design Abstraction Levels
SYSTEM
GATE
CIRCUIT
VoutVin
CIRCUIT
VoutVin
MODULE
+
DEVICE
n+S D
n+
G
•VLSI Design I; A. Milenkovic •4
9/8/2003 VLSI Design I; A. Milenkovic 10
Goal of this lecture (Chapter 3)
• Present intuitive understanding of device operation• Introduction of basic device equations• Introduction of models for manual analysis• Introduction of models for SPICE simulation• Analysis of secondary and deep-sub-micron effects• Future trends
9/8/2003 VLSI Design I; A. Milenkovic 11
The Diode
n
p
p
n
B A SiO2Al
A
B
Al
A
B
Cross-section of pn-junction in an IC process
One-dimensionalrepresentation diode symbol
Mostly occurring as parasitic element in Digital ICs
9/8/2003 VLSI Design I; A. Milenkovic 12
Depletion Region
hole diffusionelectron diffusion
p n
hole driftelectron drift
ChargeDensity
Distancex+
-
ElectricalxField
x
PotentialV
ξ
ρ
W2-W1
ψ0
(a) Current flow.
(b) Charge density.
(c) Electric field.
(d) Electrostaticpotential.
•VLSI Design I; A. Milenkovic •5
9/8/2003 VLSI Design I; A. Milenkovic 13
Diode Current
9/8/2003 VLSI Design I; A. Milenkovic 14
Ideal Diode Equation
• The ideal diode equation (for both forward and reverse-bias conditions) is
ID = IS(e VD/ φT – 1)
where VD is the voltage applied to the junction– a forward-bias lowers the potential
barrier allowing carriers to flow across the diode junction
– a reverse-bias raises the potential barrier and the diode becomes nonconducting
φT = kT/q = 26mV at 300KIS is the saturation current of the diode
+
-VD
-0.5
0.5
1.5
2.5
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
I D(m
A)
VD (V)
9/8/2003 VLSI Design I; A. Milenkovic 15
The MOS Transistor
Polysilicon Aluminum
•VLSI Design I; A. Milenkovic •6
9/8/2003 VLSI Design I; A. Milenkovic 16
The NMOS Transistor Cross Sectionn areas have been doped with donor ions (arsenic) of concentration ND - electrons are the majority carriers
p areas have been doped with acceptorions (boron) of concentration NA - holes are the majority carriers
Gate oxide
n+Source Drain
p substrate
Bulk (Body)
p+ stopper
Field-Oxide(SiO2)n+
PolysiliconGate
L
W
9/8/2003 VLSI Design I; A. Milenkovic 17
Switch Model of NMOS Transistor
Gate
Source(of carriers)
Drain(of carriers)
| V GS |
| V GS | < | VT| | V GS | > | VT|
Open (off) (Gate = ‘0’ ) Closed (on) (Gate = ‘1’)
Ron
G
DB
S
Connected to GND for NMOS
9/8/2003 VLSI Design I; A. Milenkovic 18
Switch Model of PMOS Transistor
Gate
Source(of carriers)
Drain(of carriers)
| V GS |
| V GS | > | VDD – | VT | | | V GS | < | VDD – | VT| |
Open (off) (Gate = ‘1’ ) Closed (on) (Gate = ‘0’)
Ron
G
D
B
S
Connected to VDD for PMOS
•VLSI Design I; A. Milenkovic •7
9/8/2003 VLSI Design I; A. Milenkovic 19
Threshold Voltage Concept
S D
p substrate
B
GVGS +
-
n+n+
depletion region
n channel
The value of VGS where strong inversion occurs is called the threshold voltage, VT
9/8/2003 VLSI Design I; A. Milenkovic 20
The Threshold Voltage
VT = VT0 + γ(√|-2φF + VSB| - √|-2φF|)
whereVT0 is the threshold voltage at VSB = 0 and is mostly a function of the
manufacturing process– Difference in work-function between gate and substrate material,
oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc.
VSB is the source-bulk voltageφF = -φTln(NA/ni) is the Fermi potential (φT = kT/q = 26mV at 300K is the
thermal voltage; NA is the acceptor ion concentration; ni ≈ 1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure silicon)
γ = √(2qεs iNA)/Cox is the body-effect coefficient (impact of changes in VSB) (εs i=1.053x10-10F/m is the permittivity of silicon; Cox = εox/tox is the gate oxide capacitance with εox=3.5x10-11F/m)
9/8/2003 VLSI Design I; A. Milenkovic 21
The Body Effect
0.40.450.5
0.55
0.60.650.7
0.75
0.80.850.9
-2.5 -2 -1.5 -1 -0.5 0
• VSB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground)
• A negative bias causes VT to increase from 0.45V to 0.85V
VBS (V)
VT
(V)
•VLSI Design I; A. Milenkovic •8
9/8/2003 VLSI Design I; A. Milenkovic 22
Transistor in Linear Mode
SD
B
G
n+n+
Assuming VGS > VT
VGS VDS
ID
x
V(x)- +
The current is a linear function of both VGS and VDS
9/8/2003 VLSI Design I; A. Milenkovic 23
Current flowing in the transistor
• Current flowing in the transistor: Idsn = Q/tf– Q – charge, tf – time for flight
• tf = L/vx
– Velocity of electrons: v = - µn * E• µn – electron mobility (500-1000cm2/Vs);
µp – hole mobility (100-400cm2/Vs); • E – electric field (vector)• Ex – horizontal component of E, Ex = - Vds/L• vx – horizontal component of v, vx = - µn * Ex
– tf = L/vx = L2/µn*Vds
9/8/2003 VLSI Design I; A. Milenkovic 24
Current flowing in the transistor (cont’d)
• Q = C(Vgc – Vtn)– Vgc – voltage between the gate and the channel– charge only appears on the lower plate
when Vgc exceeds Vtn
– Vgc is not constant; Vgc = Vgs at the source, Vgc = Vgs – Vds at the drain=> sum (integrate) the charge all the way across the channel from x = 0 (at the source) to x = L (at the drain)
– Assume: Vgc(x) is linear function of distance=> Vgc = [Vgs + (Vgs – Vds)]/2 = Vgs – Vds/2
– C – the gate capacitance (parallel -plate capacitor with length L, width W, a plate separation equal to the gate-oxide thickness Tox,εox – the gate oxide permittivity; εox = 3.45x10-11 F/m, Tox = 100Å)C = εox*W*L/Tox = Cox*W*L; Cox – gate capacitance per unit area
– Q = Cox*W*L*[(Vgs – Vtn) – Vds/2]
•VLSI Design I; A. Milenkovic •9
9/8/2003 VLSI Design I; A. Milenkovic 25
Current flowing in the transistor (cont’d)
• tf = L/vx = L2/µn*Vds• Q = Cox*W*L*[(VGS – VTN) – VDS/2]
• IDSN = (W/L)*µn*Cox*[(VGS – VTN) – VDS/2]*VDS
• kn’ = µn*Cox – process transconductance parameter
• βn = (W/L)*kn – transistor gain factor • Linear (triode) region: Vds < = Vgs – Vtn
– Idsn = βn*[(Vgs – Vtn) – Vds/2]*Vds
9/8/2003 VLSI Design I; A. Milenkovic 26
Voltage -Current Relation: Linear Mode
For long-channel devices (L > 0.25 micron)• When VDS ≤ VGS – VT
ID = k’n W/L [(VGS – VT)VDS – VDS2/2]
wherek’n = µnCox = µnεox/tox = is the process transconductance parameter (µn is the carrier mobility (m2/Vsec))
kn = k’n W/L is the gain factor of the device
• For small VDS, there is a linear dependence between VDS and ID, hence the name resistiveor linear region
9/8/2003 VLSI Design I; A. Milenkovic 27
Transistor in Saturation Mode
SD
B
GVGS VDS > VGS - VT
ID
VGS - VT- +n+ n+
Pinch-off
Assuming VGS > VT
VDS
The current remains constant (saturates).
•VLSI Design I; A. Milenkovic •10
9/8/2003 VLSI Design I; A. Milenkovic 28
Voltage -Current Relation: Saturation Mode
For long channel devices• When VDS ≥ VGS – VT
ID’ = k’n/2 W/L [(VGS – VT) 2]
since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at VGS – VT
• However, the effective length of the conductive channel is modulated by the applied VDS, so
ID = ID’ (1 + λVDS)
where λ is the channel-length modulation(varies with the inverse of the channel length)
9/8/2003 VLSI Design I; A. Milenkovic 29
Current Determinates
• For a fixed VDS and VGS (> V T), IDS is a function of– the distance between the source and drain – L
– the channel width – W– the threshold voltage – VT
– the thickness of the SiO2 – tox
– the dielectric of the gate insulator (SiO2) – εox
– the carrier mobility• for nfets: µn = 500 cm2/V-sec
• for pfets: µp = 180 cm2/V-sec
9/8/2003 VLSI Design I; A. Milenkovic 30
Long Channel I-V Plot (NMOS)
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5
I D(A
)
VDS (V)
X 10-4
VGS = 1.0V
VGS = 1.5V
VGS = 2.0V
VGS = 2.5V
Linear Saturation
VDS = VGS - VT
Qua
drat
icde
pend
ence
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
cut-off
•VLSI Design I; A. Milenkovic •11
9/8/2003 VLSI Design I; A. Milenkovic 31
Short Channel Effects
υsat =105
l For an NMOS device with L of .25µm, only a couple of volts difference between D and S are needed to reach velocity saturation
l Behavior of short channel device mainly due to
• Velocity saturation –the velocity of the carriers saturates due to scattering (collisions suffered by the carriers)
0
10
0 1 . 5 3
ξ(V/µm)
υn
(m/s
)
Constant velocity
Constant mobility(slope = µ)
ξc=
5
9/8/2003 VLSI Design I; A. Milenkovic 32
Voltage -Current Relation: Velocity Saturation
For short channel devices• Linear: When VDS ≤ VGS – VT
ID = κ(VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
whereκ(V) = 1/(1 + (V/ξcL)) is a measure of the degree of velocity saturation
• Saturation: When VDS = VDSAT ≥ VGS – VT
IDSat = κ(VDSAT) k’n W/L [(VGS – VT)VDSAT –VDSAT
2/2]
9/8/2003 VLSI Design I; A. Milenkovic 33
Velocity Saturation Effects
0
10 Long channel devices
Short channel devices
VDSAT VGS-VT
• VDSAT < VGS – VT so the device enters saturation before VDSreaches VGS – VT and operates more often in saturation
For short channel devices and large enough VGS – VT
• IDSAT has a linear dependence wrt VGS so a reduced amount of current is delivered for a given control voltage
VGS = VDD
•VLSI Design I; A. Milenkovic •12
9/8/2003 VLSI Design I; A. Milenkovic 34
Short Channel I-V Plot (NMOS)
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
I D(A
)
VDS (V)
X 10-4
VGS = 1.0V
VGS = 1.5V
VGS = 2.0V
VGS = 2.5V
Line
arde
pend
ence
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
Early VelocitySaturation
Linear Saturation
9/8/2003 VLSI Design I; A. Milenkovic 35
MOS ID-VGS Characteristics
0123456
0 0.5 1 1.5 2 2.5VGS (V)
I D(A
)
longlong--channel channel quadraticquadratic
short-channel linear
• Linear (short-channel) versus quadratic (long-channel) dependence of ID on VGS in saturation
• Velocity -saturation causes the short-channel device to saturate at substantially smaller values of VDS
resulting in a substantial drop in current drive
(for VDS = 2.5V, W/L = 1.5)
X 10-4
9/8/2003 VLSI Design I; A. Milenkovic 36
Short Channel I-V Plot (PMOS)
-1
-0.8
-0.6
-0.4
-0.2
00-1-2
I D(A
)
VDS (V)
X 10-4
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
• All polarities of all voltages and currents are reversed
•VLSI Design I; A. Milenkovic •13
9/8/2003 VLSI Design I; A. Milenkovic 37
The MOS Current-Source Model
-0.1-30 x 10-6-1-0.4-0.4PMOS0.06115 x 10-60.630.40.43NMOS
λ(V-1)k’(A/V2)VDSAT(V)γ(V0.5)VT0(V)
S D
G
B
ID
ID = 0 for VGS – VT ≤ 0
ID = k’ W/L [(VG S – VT)Vmin–Vmin2/2](1+λVDS)
for VGS – VT ≥ 0
with Vmin = min(VGS – VT, VDS, VDSAT)and VGT = VGS - VT
l Determined by the voltages at the four terminals and a set of five device parameters
9/8/2003 VLSI Design I; A. Milenkovic 38
The Transistor Modeled as a Switch
0
1
2
3
4
5
6
7
0.5 1 1.5 2 2.5VDD (V)
Req
(Ohm
)
x105
S DRon
VGS ≥ VT
313855115PMOS (kΩ)13151935NMOS(kΩ)
2.521.51VDD(V)
(for VGS = VDD, VDS = VDD →VDD/2)
Modeled as a switch with infinite off resistance and a finite on resistance, Ron
• Resistance inversely proportional to W/L (doubling W halves Ron)
• For VDD>>VT+VDSAT/2, Ronindependent of VDD
• Once VDD approaches VT, Ron increases dramatically
Ron (for W/L = 1)For larger devices divide Req by W/L
9/8/2003 VLSI Design I; A. Milenkovic 39
Other (Submicon) MOS Transistor Concerns
• Velocity saturation• Subthreshold conduction
– Transistor is already partially conducting for voltages below VT
• Threshold variations– In long-channel devices, the threshold is a function of the length (for
low VDS)– In short-channel devices, there is a drain-induced threshold barrier
lowering at the upper end of the VDS range (for low L)
• Parasitic resistances– resistances associated with the
source and drain contacts
• Latch-up
S
G
D
RS RD
•VLSI Design I; A. Milenkovic •14
9/8/2003 VLSI Design I; A. Milenkovic 40
Subthreshold Conductance
0 0.5 1 1.5 2 2.5
I D(A
)
VGS (V)
10-12
10-2
Subthresholdexponential region
Quadratic regionLinear region
VT
• Transition from ON to OFF is gradual (decays exponentially)• Current roll-off (slope factor) is also affected by increase in temperature
•S = n (kT/q) ln (10)•(typical values 60 to 100
mV/decade)
• Has repercussions in dynamic circuits and for power consumptionID ~ IS e (qVGS/nkT) where n ≥ 1
9/8/2003 VLSI Design I; A. Milenkovic 41
Subthreshold ID vs VGS
VDS from 0 to 0.5V
ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + λVDS)
9/8/2003 VLSI Design I; A. Milenkovic 42
Subthreshold ID vs VDS
VGS from 0 to 0.3V
ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + λVDS)
•VLSI Design I; A. Milenkovic •15
9/8/2003 VLSI Design I; A. Milenkovic 43
Threshold Variations
VT
L
Long-channel threshold Low VDS threshold
Threshold as a function of the length (for low VDS)
Drain-induced barrier lowering (for low L)
VDS
VT
9/8/2003 VLSI Design I; A. Milenkovic 44
Next Time: The CMOS Inverter
VDD
Vout
CL
Vin