EE382V: Embedded System Design and Modelingusers.ece.utexas.edu/~gerstl/ee382v_f08/notes/lecture1.pdf · EE382V: Embedded System Design and Modeling ... Introduction Embedded systems

EE382V:

Embedded System Design and Modeling

Andreas Gerstlauer

Electrical and Computer Engineering

University of Texas at Austin

[email protected]

Lecture 1 - Introduction

EE382V: Embedded Sys Dsgn and Modeling, Lecture 1 © 2008 A. Gerstlauer 2

Lecture 1: Outline

• Introduction

• Embedded systems

• Abstraction levels, design flow

• System-level design

• Design tasks, design challenges

• Course information

• Administration

• Topics

• Materials

• Policies

• Projects


Embedded Systems

• Systems that are part of a larger system

• Application-specific– Diverse application areas

• Tight constraints– Real-time, performance, power, size

– Cost, time-to-market, reliability

• Ubiquitous

• Far bigger market than general-purpose computing (PCs, servers)– $46 billion in ‘04, >$90 billion by 2010, 14% annual growth [BCC]

– 4 billion devices in ‘04 [VDC]

– 99.8% of processors sold [MPR]


Embedded System Design is hard…


… and getting harder

• Growing system complexities

• Increasing application demands– Device convergence (multimedia, infotainment, GPS, …)

• Technological advances– Multi-Core/Multi-Processor System-On-Chip (MPSoC)

� Raising the level of abstraction [ITRS]

� Electronic system-level (ESL) design

10,000

1,000

100

10

1

0.1

0.01

0.001

Logic transistors per

chip (in millions)

100,000

10,000

1000

100

10

1

0.1

0.01

Productivity

(K) Trans./Staff-Mo.

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

2007

2009

IC capacity

Productivity

Gap

Source: SEMATECH; Courtesty of: T. Givargis, F. Vahid. “Embedded System Design”, Wiley 2002.


Abstraction Levels


1E0

1E1

1E2

1E3

1E4

1E5

1E6

1E7

Number of componentsLevel

Gate

RTL

Algorithm

System

Transistor

Abstraction

Accuracy

Source: R. Doemer, UC Irvine


System levelSystem levelSystem level

Abstraction Levels


� Move to higher levels of abstraction

1E0

1E1

1E2

1E3

1E4

1E5

1E6

1E7

Number of componentsLevel

Gate

RTL

Algorithm

Transistor

Abstraction

Accuracy

Source: R. Doemer, UC Irvine


Abstraction Levels

Temporal orderLow abstraction

High abstraction

Implementation DetailImplementation Detail

Spatial order

physical layout

unstructured

StructureStructure

real time

untimed

TimingTiming


Top-Down Design Flow

Implementation

Architecture

Specification

Logic Design

Product planning

Structure

pure functional

bus functional

RTL / IS

gates

requirements

Timing

untimed

timing accurate

cycle accurate

gate delays

constraints

System Design

Processor Design


Electronic System-Level (ESL) Design

• From system specification

• Functionality, behavior– Application algorithms

– Constraints

• To system architecture

• Structure– Spatial and temporal order

– Components and connectivity

– Across hardware and software

� Design automation (EDA/CAD) at the system level

• Modeling and simulation

• Synthesis

• Verification

Proc

Proc

Proc

Proc

Proc

Memory

Memory

µProcessor

Interface

Comp.IP

Bus

Interface

Interface

Interface

Custom HW

Requirements, constraints

Implementation (HW/SW synthesis)

Computation &

Communication

Design


System Specification

• Capture requirements

• Functional– Free of any implementation details

• Non-functional– Quality metrics, constraints

• Formal representation

• Models of computation– Analysis of properties

• Executable– Validation through simulation

� Algorithm development

� Concept to precise description of desired system behavior

Proc

Proc

Proc

Proc

Proc

Natural language� Ambiguous� Incomplete


System Architecture

• Processing elements (PEs)

• Processors– General-purpose, programmable

– Digital signal processors (DSPs)

– Application-specific (ASIP)

– Custom hardware processors

– Intellectual property (IP)

• Memories

• Communication elements (CEs)

• Transducers, bus bridges

• I/O peripherals

• Busses

• Communication media– Parallel, master/slave protocols

– Serial and network media

Memory

Memory

µProcessor

Interface

Comp.

IP

Bus

Interface

Interface

Interface

Custom HW

� Heterogeneous multi-

processor systems

�MPSoCs


System Design Tasks

• Computation

• PE Allocation– Processor types and numbers

– Local and global memories

• Partitioning– Behavior to processor mapping

– Variable to storage mapping

• Scheduling– Static scheduling

– Dynamic scheduling

� Design space exploration

� Unified view across system implementation choices

• Communication

• Network allocation– Busses and CEs

• Mapping– Shared memory vs. message-passing

– Routing

• Interface synthesis– Addresses and interrupts

– Bus parameters, priorities


Design Challenges

• Design quality metrics and constraints

• Performance– Latency and throughput

• Power– Static and dynamic power consumption

• Cost– Unit and non-recurring engineering (NRE) costs

• Dependability and reliability– Fault tolerance, safety, correctness, mean time between failure (MTBF)

• Management– Time-to-market, maintainability, flexibility

• …

� Multi-objective optimization and trade-offs

� Optimize metrics while satisfying all constraints


Lecture 1: Outline

� Introduction

� Embedded systems

� Abstraction levels, design flow

� System-level design

� Design tasks, design challenges

• Course information

• Administration

• Topics

• Materials

• Policies

• Projects


Class Administration

• Schedule

• Lectures: TTh 3:30-5pm, ENS109

• Instructor

• Prof. Andreas Gerstlauer– E-mail: [email protected]

– Office: ACE 6.118

– Office hours: T 5:00-6:30pm, W 2:00-3:30pm

• Teaching Assistant

• Mahesh Prabhu

• Information

• Web page: http://www.ece.utexas.edu/~gerstl/ee382Vf08

• Announcements, assignments, grades: Blackboard

• Questions, discussions: Blackboard


Course Topics

• Modeling and languages

• Models of Computation (MoC): Process, dataflow, FSM

• System-level design languages (SLDL): SpecC, SystemC

• System specification

• Specification modeling and validation

• Profiling and analysis

• System-level design

• Methodologies, tools: System-On-Chip Environment (SCE)

• Exploration: partitioning, mapping, scheduling

• Platform modeling, refinement: transaction-level modeling (TLM)

• Implementation: hardware and software synthesis

� Prerequisites

� Algorithms and data structures

� Digital hardware design, VLSI

� Embedded systems and embedded software


System-On-Chip Environment (SCE)

Specification

System Design(“Specify-Explore-Refine”)

SWDB

Systemmodels

CPUn.bin

Implementation Model

PE/CE/BusModels

TLMnTLMnTLMi

Hardware Synthesis

Software Synthesis

RTLDB

RTLnRTLnRTLnISSnISSnISSn CPUn.binCPUn.bin

HWn.vHWn.vHWn.v

Design Decisions

ArchnArchn

Binary

Mem

IPHW

CPU Bus DSP Bus

v1v2

B5B4

HAL

RTOS

B1

Binary

HAL

RTOS

B2,B3

Bridge

Arbiter

Archn

Bridge

Arbiter

Archn

Bridge

Arbiter

TLMn

Impln

Binary

Mem

IPHW

CPU Bus DSP Bus

v1v2

B5B4

HAL

RTOS

B1

Binary

HAL

RTOS

B2,B3

Compile onto platform

Synthesize target HW/SW

Spec

� Commercial derivative

� Japanese Aerospace Exploration Agency (JAXA)

� Commercial derivative

� Japanese Aerospace Exploration Agency (JAXA)


Textbooks (1)

• Main textbook

• A. Gerstlauer, R. Doemer, J. Peng, D. Gajski, System Design: A Practical Guide with SpecC, Kluwer, 2001 (“yellow book”)– Practical, example-drive introduction using SpecC

• Optional books

• D. Gajski, J. Zhu, R. Doemer, A. Gerstlauer, S. Zhao, SpecC: Specification Language and Methodology, Kluwer, 2000(“green book”)– Additional reference for SpecC language, methodology and design examples


Textbooks (2)

• Optional books (cont’d)

• T. Groetker, S. Liao, G. Martin, S. Swan,System Design with SystemC, Kluwer, 2002 (“black book")– Reference for SystemC language and methodology

• F. Vahid, T. Givargis, Embedded System Design: A Unified Hardware/Software Introduction, Wiley, John & Sons, 2001– Background about embedded systems in general

� Additional reading material posted on class

webpage


Policies

• Grading

• Homeworks/labs: 30%

• Midterm: 20%

• Project: 50%

• Academic dishonesty

• Homeworks/labs– Discuss questions and problems with others

– Turn in own, independent solution

• Project– Project teams, one report and presentation

– Reference and quote any outside source of information


Possible Projects

• Design examples

• Develop specification model of a system design example• Validate, profile and analyze specification• Explore design space and refine using SCE

• Model-based design

• Investigate translation of domain-specific MoCs (e.g. Matlab, UML) into a SpecC specification model

• Implement automatic translator frontend• Component modeling

• Develop bus, processor or IP model (TLM) for SCE database• Use component model in system design example

• Synthesis algorithms

• Survey literature on system-level synthesis• Develop decision making algorithm(s) as plug-in for SCE• Evaluate and benchmark algorithm(s)

• Power modeling

• Survey literature on power modeling and estimation• Develop concepts for modeling power at the system level• Evaluate concepts on example

Documents

EE382V: Embedded System Design and Modelingusers.ece.utexas.edu/~gerstl/ee382v_f08/notes/lecture1.pdf · EE382V: Embedded System Design and Modeling ... Introduction Embedded systems