EE382V: Embedded System Design and Modelingusers.ece.utexas.edu/~gerstl/ee382v_f09/notes/lecture6.pdf · EE382V: Embedded Sys Dsgn and Modeling Lecture 6 © 2009 A. Gerstlauer 3 EE382V:

EE382V: Embedded Sys Dsgn and Modeling

Lecture 6

© 2009 A. Gerstlauer 1

EE382V:Embedded System Design and Modeling

Andreas GerstlauerElectrical and Computer Engineering

University of Texas at [email protected]

Lecture 6 – Specification and Refinement

EE382V: Embedded Sys Dsgn and Modeling, Lecture 6 © 2009 A. Gerstlauer 2

Lecture 6: Outline

• System specification

• Specification modeling

• System validation

• System refinement

• Computation

• Communication

• Implementation

• System design flow

• Design environment

• Vocoder design example


Lecture 6



Design Methodology

System design Validation flow

Specification model

Algor.IP

Proto.IP

Computation model

Communication refinement

Communication model

Comp.IP

Estimation

ValidationAnalysis

Compilation Simulation model

Estimation

ValidationAnalysis


Estimation

ValidationAnalysis


Implementation model

Softwaresynthesis

Interfacesynthesis

Hardwaresynthesis

Backend Estimation

ValidationAnalysis


RTOSIP

RTLIP

Computation refinement

Capture


Design Methodology

Specification Capture and Validation

Specification model

Algor.IP

Proto.IP

Computation model


Communication model

Comp.IP

Estimation

ValidationAnalysis


Estimation

ValidationAnalysis


Estimation

ValidationAnalysis



Softwarecompilation

Interfacesynthesis

Hardwaresynthesis

Estimation

ValidationAnalysis


RTOSIP

RTLIP


Capture


Lecture 6



Essential Issues in Specification

• An Example ...

Proposed by the project team Product specification Product design by senior analyst

Product after implementation Product after acceptance by user What the user wanted

Source: unknown author, Courtesy of: R. Doemer


Specification Model

• Functional and executable

• “golden model” (first functional model in the design flow)

• all other models will be derived from and compared to this one

• High abstraction level

• no implementation details

• unrestricted exploration of design space

• Separation of communication and computation

• channels and behaviors

• Pure functional

• no structural information

• No timing

• exception: timing constraints


Lecture 6



Specification Model

• Test bench

• Main, Stimulator, Monitor

• no restrictions in syntax and semantics (no synthesis)

• Design under test

• DUT

• restricted by syntax and semantic rules (synthesis!)

Stimulator DUT

v2

Monitor

v1

v4

v3Main

Source: R. Doemer, UC Irvine


Specification Modeling Guidelines

• Computation: Behaviors

• Hierarchy: explicit concurrency, state transitions, ...

• Granularity: leaf behaviors = smallest indivisible units

• Encapsulation: localization, explicit dependencies

• Concurrency: explicitly specified (par, pipe, fsm, seq, …)

• Time: un-timed, partial ordering

• Communication: Channels

• Semantics: abstract communication, synchronization(standard channel library)

• Dependencies: explicit data dependency,partial ordering, port connectivity


Lecture 6




• Example rules for SoC Environment (SCE)

• Clean behavioral hierarchy– hierarchical behaviors:

no code other than seq, par, pipe, fsm statements

– leaf behaviors:no SpecC code (pure ANSI-C code only)

• Clean communication– point-to-point communication via standard channels:c_handshake, c_semaphore, c_double_handshake, c_queue (typed or untyped)

– ports of plain ANSI C type or interface type, no pointers!

– port maps to local variables or ports only

Detailed rules for SoC Environment

“SCE Specification Model Reference Manual,”by A. Gerstlauer, R. Doemer, CECS, UC Irvine, April 2005



• C code conversion to SpecC• Functions become behaviors or channels• Functional hierarchy becomes behavioral hierarchy

– Clean behavioral hierarchy required– if-then-else structure becomes FSM– while/for/do loops become FSM

• Explicitly specify potential parallelism– Data (array) partitioning

• Explicitly specify communication– Avoid global variables– Use local variables and ports (signals, wires)– Use standard channels

• Data types– Avoid pointers, use arrays instead– Use explicit SpecC data types if suitable– Floating-point to fixed-point conversion


Lecture 6



System Validation using SpecC

• Simulation• scc DesignName –sc2out –vv –ww./DesignName

• Header file sim.sh– Access to simulation time

» macros PICO_SEC, NANO_SEC, MICRO_SEC,MILLI_SEC, SEC

» typedef sim_time, sim_delta, sim_time_string

» function now(), delta()

» conversion functions time2str(), str2time()

– Handling of bit vectors» conversion functions bit2str(), ubit2str(), str2bit(), str2ubit()

– Handling of long-long values» conversion functions ll2str(), ull2str(), str2ll(), str2ull()




• Debugging• module load gnutools (for ddd)• scc DesignName –sc2out –vv –ww –g -Ggdb ./DesignName (interactive debugger)ddd ./DesignName (graphical gdb frontend)

• Header file sim.sh– Access to simulation engine state

» functions ready_queue(), running_queue(), etc.» functions _print_ready_queue(), _print_running_queue(), etc.

» function _print_process_states()» function _print_simulator_state()

– Access to current instance» functions active_class(), active_instance()» functions current_class(), current_instance()» functions print_active_path(), print_current_path()» ...



Lecture 6




• Tracing• module load gnutools (for gtkwave)• scc DesignName –sc2out –vv –ww -Tvcds./DesignNamegtkwave DesignName.vcd

• Trace instructions in file DesignName.do• Trace log in file DesignName.vcd• Waveform display, e.g. gtkwave

Examples $SPECC/examples/trace, see README

Documentation E. Johnson, A. Gerstlauer, R. Dömer:

"Efficient Debugging and Tracing of System Level Designs", CECS Technical Report 06-08, May 2006.



Lecture 6: Outline

System specification

Specification modeling

System validation

• System refinement

• Computation

• Communication

• Implementation





Lecture 6



Specification Model

• High-level, abstract model

• Pure system functionality

• Algorithmic behavior

• No implementation details

• No implicit structure / architecture

• Behavioral hierarchy

• Untimed

• Executes in zero (logical) time

• Causal ordering

• Events only for synchronization

Specification model


Computation model

Communication model



Processor refinement


Specification Model Example

B2 B3

c2

B1

v1

B1

• Synthesizable specification model

• Hierarchical parallel-serial composition

• Communication through variables and standard channels


Lecture 6



Computation Refinement

• PE allocation / selection

• Behavior partitioning

• Variable partitioning

• Scheduling

Specification model


Computation model

Communication model





PE Allocation, Behavior Partitioning

• Allocate PEs

• Partition behaviors

• Globalize communicationB2 B3

c2

B1

v1

B1

Additional level of hierarchy to model PE structure

PE1

PE2


Lecture 6



Model after Behavior Partitioning

B3B2

B1B1 PE1

c2

v1

B13rcv

B34snd

B13snd

B34rcv

cb13

cb34

PE2

Synchronization to preserve execution order/semantics


• Map global variables to local memories

Variable Partitioning

Shared memory vs. message passing implementation

B3

B13rcv

B34snd

B2

B1B1

B13snd

B34rcv

PE1

c2

v1

cb13

cb34

PE2

v1 v1

• Communicate data over message-passing channels


Lecture 6



Model after Variable Partitioning

B3

B13rcv

B34snd

B2

B1B1

B13snd

B34rcv

PE1

c2

v1

cb13

cb34

PE2

v1

Keep local variable copies in sync• Communicate updated values at synchronization points• Transfer control & data over message-passing channel


Timed Computation

• Execution time of behaviors

• Estimated target delay / timing budget

• Granularity

• Behavior / function / basic-block level

Annotate behaviors

• Simulation feedback

• Synthesis constraints

behavior B2( in int v1, ISend c2 ) {

void main(void) { waitfor( delay1 );

c2.send( );

}};

waitfor( B2_DELAY1 );waitfor( B2_DELAY1 );

waitfor( B2_DELAY2 );waitfor( B2_DELAY2 );

1

5

10


Lecture 6



Scheduling

• Static scheduling– Fixed behavior execution order

– Flattened behavior hierarchy

Serialize behavior execution on components

B2

B1B1

B13snd

B34rcv

PE1

• Dynamic scheduling– Pool of tasks

– Scheduler, abstracted OS


Computation Model Example

B3

B13rcv

B34snd

B2

B1B1

B13snd

B34rcv

PE1

c2

v1

cb13

cb34

PE2

v1


Lecture 6



Computation Model

• Component structure/architecture

• Top level of behavior hierarchy

• Behavioral/functional component view

• Behaviors grouped under top-level component behaviors

• Sequential behavior execution

• Timed

• Estimated execution delays

Specification model

Computation model

Communication model






Communication Refinement

• Network allocation / protocol selection

• Channel partitioning

• Protocol stack insertion

• Inlining

Specification model

Computation model

Communication model






Lecture 6



Network Allocation / Channel Partitioning

B3

B34snd

B2

B1B1

B13snd

B34rcv

PE1

c2

v1

cb13

cb34

PE2

v1

B13rcv

• Allocate busses

• Partition channels

• Update communication

Additional level of hierarchy to model bus structure

Bus1


Model after Channel Partitioning

B3

B34snd

B2

B1B1

B13snd

B34rcv

PE1

v1

PE2

v1

B13rcv

c2

cb13

cb34

Bus1


Lecture 6



Protocol Insertion

c2

cb13

cb34

Bus1

ProtocolLayer

Network

Layers

Bus1

• Insert protocol layer

• Bus protocol channel from database

• Create network layers

• Implement message-passing over bus protocol

• Replace bus channel

• Hierarchical combination of complete protocol stack


Model after Protocol Insertion

B2

B1B1

B13snd

B34rcv

PE1

v1

B3

B34snd

PE2

v1

B13rcv

Bus1

IBu

sSla

ve

IBu

sMas

ter

ready

addr[16]

data[32]

BusProtocol

Master Slave

IPro

toco

lSla

ve

IPro

toco

lMas

ter

ack


Lecture 6



Inlining: Transaction-Level Model (TLM)

Bus1

IBu

sSla

ve

IBu

sMas

ter BusProtocol

PE1 PE2

ready

addr[16]

data[32]

IPro

toco

lSla

ve

IPro

toco

lMas

ter

ack

PE2PE2Bus

IBu

sSla

ve

PE1Bus

IBu

sMas

ter

PE1

• Create bus interfaces and drivers

read()/write() methods in C,

functionality + timing

IPro

toco

lSla

ve

IPro

toco

lMas

ter

BusProtocolTLM


BusProtocolTLM

Inlining: Pin-Accurate Model (PAM)

Bus1

IBu

sSla

ve

IBu

sMas

ter

PE1 PE2

PE2PE2BusPE1Bus

PE1

Transaction-LevelModel (TLM)

IPro

toco

lSla

ve

IPro

toco

lMas

ter

• Create bus interfaces and drivers

• Refine communication

BusProtocol

ready

addr[16]

data[32]

IPro

toco

lSla

ve

IPro

toco

lMas

ter

ack

IBu

sMas

ter

IBu

sSla

ve

PE

2Pro

toco

l

IPro

toco

lSla

ve

PE

1Pro

toco

l

IPro

toco

lMas

ter

control

address[15:0]

data[31:0]

IBu

sSla

ve

IBu

sMas

ter


Lecture 6



Communication Model Example

control

address[15:0]

data[31:0]

B3

B34snd

v1

B13rcv

B2

B1B1

B13snd

B34rcv

PE1

v1

PE2


Communication Model

• Component & bus structure/architecture

• Top level of hierarchy

• Bus-functional component models

• Timing-accurate bus protocols

• Behavioral component description

• Timed

• Estimated component delays

• Timing-accurate communication

Transaction-level model (TLM)

Pin-accurate model (PAM)

Bus cycle-accurate model (BCAM)

Specification model

Computation model

Communication model






Lecture 6



Processor Refinement

• Cycle-accurate implementation of PEs

• Hardware synthesis down to RTL

• Software synthesis down to IS

• Interface synthesis down to RTL/IS

Specification model

Computation model

Communication model






Hardware Synthesis

• Schedule operations into clock cycles

• Define clock boundaries in leaf behavior C code

• Create FSMD model from scheduled C code– Controller + datapath

B3

B34snd

v1

B13rcv

PE2

PE2_CLK

PE2_CLK

PE2_CLK

Clock boundaries


Lecture 6



Software Synthesis

• Implement behavior on processor instruction-set

• Code generation

• Compilation

B2

B1B1

B13snd

B34rcv

PE1

v1

Ff2MOVE r0, r1

SHL r3ADD r2, r3, r4INC r2

PUSH r1CALL Ff3POP r0


Implementation Model

Software processor Custom hardware

ready

ack

address[15:0]

data[31:0]

PE2

PE2_CLKPE1_CLK

OBJ

PORTA

PORTB

INTA

PORTC

PE1

Instruction Set Simulator (ISS)

S0

S1

S2

S3

S4


Lecture 6



Implementation Model

• Cycle-accurate system description

• RTL description of hardware– Behavioral/structural FSMD view

• Object code for processors– Instruction-set co-simulation

• Clocked bus communication– Bus interface timing based on PE clock

Specification model

Architecture model

Communication model



Communication synthesis

Architecture exploration


Lecture 6: Outline

System specification

Specification modeling

System validation

System refinement

Computation

Communication

Implementation





Lecture 6



Specification model

Computation model

Communication model


Validation GUI

Test

Simulate

Compile

Test

Simulate

Test

Simulate

Simulate

Test

Design Environment (1): Modeling


Specification model

Computation model

Design decisions

Communication model

Comp. refinement

Comm. refinement

PE Allocation

Beh/Var Partitioning

Scheduling

Refinement GUI

Net Allocation

Channel partitioning

Spec. optimization

Prot. insertion

Design decisions

Design decisionsProc. refinement


Capture

RTL/SWHW alloc/sched/bind

SW Compilation

IF generation

Browsing

Alg. selection

Comp. / IP

Protocols

Validation GUI

Test

Verify

Simulate

Compile

Test

Simulate

Test

Verify

Simulate

Simulate

Verify

Test

Design Environment (2): Refinement


Lecture 6



Specification model

Computation modelEvaluation

Profiling

Profiling data

Design decisions

Communication model

Comp. refinement

Comm. refinement

PE Allocation


Scheduling

Refinement GUI

Net Allocation


Evaluation results

Spec. optimization

Prot. insertion

Design decisions

Evaluation

Evaluation results



Capture


SW Compilation

IF generation

Browsing

Alg. selection

Comp. / IP

Protocols

Validation GUI

Test

Verify

Simulate

Compile

Test

Simulate

Profile

Test

Verify

Simulate

Simulate

Verify

Test

Design Environment (3): Exploration

Estimate

Estimate


Specification model

Computation modelEvaluation

Profiling

Profiling data

Design decisions

Communication model

Comp. synthesis

Comp. refinement

Comm. synthesis

Comm. refinement

PE Allocation


Scheduling

Refinement GUI

Net Allocation


Evaluation results

Spec. optimization

Prot. insertion

Design decisions

Evaluation

HW/SW synthesis

Evaluation results



Capture


SW Compilation

IF generation

Browsing

Alg. selection

Comp. / IP

Protocols

Validation GUI

Test

Verify

Simulate

Compile

Test

Simulate

Profile

Test

Verify

Simulate

Simulate

Verify

Test

Design Environment (4): Synthesis

Estimate

Estimate


Lecture 6



System-on-Chip Environment (SCE)

• Server and accounts

• ECE LRC Linux servers– Labs (ENS 507) or remote access (ssh)

• SpecC software (© by CECS, UCI)– /home/project/gerstl/sce-20080601

– source /home/…/sce-20080601/bin/setup.{c}sh

• SCE tool set

• GUI– sce

• Scripting– sce_allocate / sce_map / sce_schedule / …

• Documentation ($SPECC/doc)– SCE Manual (online via Help->Manual)

– SCE Tutorial (PDF or html)– SCE Specification Reference Manual (SpecRM.pdf)


SCE Main Window


Lecture 6



SCE Source Editor


SCE Hierarchy Displays


Lecture 6



SCE Compiler and Simulator


SCE Profiling and Analysis


Lecture 6



GSM Vocoder

• Enhanced Full Rate (EFR) standard (GSM 06.10, ETSI)• Lossy voice encoding/decoding for mobile telephony

– Speech synthesis model

– Input: speech samples @ 104 kbit/s

– Frames of 4 x 40 = 160 samples (4 x 5ms = 20ms of speech)

– Output: encoded bit stream @ 12.2 kbit/s (244 bits / frame)

• Timing constraint– 20ms per frame (total of 3.26s for sample speech file)

SpecC specification model

• 73 leaf, 29 hierarchical behaviors (9 par, 10 seq, 10 fsm)

• 9139 lines of SpecC code (~13000 lines of original C)

Short-termsynthesis filter

+Delay/ Adaptive codebook

10th-order LP filter

Speech

Fixed codebook

Long-termpitch filter

Residual pulses


Vocoder Specification Model

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Lecture 6



Vocoder Computation Model

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Vocoder Communication Model

nWR

Data[23:0]

intC

Addr[15:0]

MCS

nRD

Bus InterfaceBus Driver

Bus InterfaceBus Interface Bus Interface Bus Interface

HWCodebook

Speech_In Bits2Prm Prm2Bits Speech_Out

DSP


Lecture 6



Vocoder Implementation Model

Cycle-accurate co-simulation

• DSP instruction-set simulator (ISS)• 70,500 lines of assembly code (running @ 60MHz)

• RTL SpecC for hardware• 45,000 lines of VHDL RTL code (running @ 100MHz)

nWR

Data[23:0]

intC

Addr[15:0]

MCS

nRD

CodebookFSMD

MotorolaDSP56600

ISSOBJ

DSP HW


Vocoder Results

• Productivity gain: 12 months vs. 1 hour = 2000x

Comm Impl

AutomatedUser / Refine

ManualModified

lines

Spec Arch

Arch Comm

3,275

914

30 min / < 2 min5~6 month

5 min / < 0.5 min

3~4 month

6,146

15 min / < 1 min

1~2 month

Refinement Effort

Total 50 min / < 4 min9~12 month10,355

Simulation Speed

1

10

100

1000

10000

100000

Spec Arch Comm Impl

No

rmal

ized

Tim

e

Code Size

0

5000

10000

15000

20000

Spec Arch Comm Impl

Nu

mb

er o

f L

ines


Lecture 6



Lecture 6: Summary

• Design methodology• Four levels of abstraction

– Specification model: untimed, functional– Computation model: estimated, structural– Communication model: timed, bus-functional– Implementation model: cycle-accurate, RTL/IS

• Three refinement steps– Computation refinement– Communication refinement– Processor refinement

» HW / SW / interface synthesis

• Well-defined, formal models & transformations– Automatic, gradual refinement– Executable models, test bench re-use– Simple verification

Documents

EE382V: Embedded System Design and Modelingusers.ece.utexas.edu/~gerstl/ee382v_f09/notes/lecture6.pdf · EE382V: Embedded Sys Dsgn and Modeling Lecture 6 © 2009 A. Gerstlauer 3 EE382V: