EE247 Lecture 22 ADC Converters Pipelined ADCsee247/fa05/lectures/L22_f05.pdfEECS 247 Lecture 22: Data Converters © 2005 H.K. Page 11 Two Stage Example • Fine ADC is re-used 22

EECS 247 Lecture 22: Data Converters © 2005 H.K. Page 1

EE247Lecture 22

ADC ConvertersPipelined ADCs


Pipelined A/D Converters

• Ideal operation• Errors and correction

– Redundancy– Digital calibration

• Implementation – Practical circuits– Stage scaling


Block Diagram

• Idea: Cascade several low resolution stages to obtain high overall resolution

• Each stage performs coarse A/D conversion and computes its quantization error, or "residue"

Align and Combine Data

Stage 1B1 Bits

Stage 2B2 Bits

Digital output(B1 + B2 + ... + Bk) Bits

Vin

MSB... ...LSB

Stage k Bk Bits

Vres1 Vres2


Characteristics

• Number of components (stages) grows linearly with resolution

• Pipelining– Trading latency for conversion speed– Latency may be an issue in e.g. control systems– Throughput limited by speed of one stage → Fast

• Versatile: 8...16bits, 1...200MS/s• Many analog circuit non-idealities can

be corrected digitally


Concurrent Stage Operation

• Stages operate on the input signal like a shift register• New output data every clock cycle, but each stage

introduces at least ½ clock cycle latency

Align and Combine Data

Stage 1B1 Bits

Stage 2B2 Bits

Digital output(B1 + B2 + ... + Bk) Bits

VinStage kBk Bits

φ1φ2

acquireconvert

convertacquire

...

...

CLKφ1

φ2


Data Alignment

• Digital shift register aligns sub-conversion results in time

Stage 2B2 Bits

VinStage kBk Bits

φ1φ2

acquireconvert

convertacquire

...

...

+ +Dout

CLK CLK CLK

Stage 1B1 Bits

CLKφ1

φ2


Latency

[Analog Devices, AD 9226 Data Sheet]


Pipelined ADC Analysis

• Ignore timing and use simple static model

• Let's first look at "two-stage pipeline"– E.g.: Two cascaded 2-bit ADCs to get 4 bits of

total resolution

Stage 2B2 Bits

Vin Stage k Bk Bits

+Dout

Stage 1B1 Bits

+

Vres1 Vres2


Two Stage Example

• Using only one ADC: output contains large quantization error

• "Missing voltage" or "residue" ( -εq1)

• Idea: Use second ADC to quantize and add -εq1

0 1 2 300

01

10

11

0 1 2 3-1

-0.5

0

0.5

1

[LS

B]

ADC Input [LSB]

Vin

+Dout = Vin + εq1

2-bit ADC 2-bit ADC

???

ε q1

D out

Vin


Two Stage Example

• Use DAC to compute missing voltage• Add quantized representation of missing voltage• Why does this help? How about εq2 ?

Vin “Coarse“

+

Dout= Vin + εq1

2-bit ADC 2-bit ADC

“Fine“+-

2-bit DAC-εq1

-εq1+εq2

-εq1+εq2


Two Stage Example

• Fine ADC is re-used 22 times• Fine ADC's full scale range needs to span only 1 LSB of coarse

quantizer

221

22

2 222 ⋅== refref

q

VVε

00 01 10 11

Vref1/22

−εq1

00

01

10

11

First ADC“Coarse“

Second ADC“Fine“VinVref1

Vref2


Two Stage Pipelined ADC Transfer Function

Dout

VinVref1

0000000100100011010001010110011110001001101010111100110111101111

CoarseBits(MSB)

FineBits(LSB)


Two Stage (2+2) Pipelined ADC

Vin Vin Vin

4-bit Flash ADC Ideal 2+2 pipelined ADC(2-step flash)


Cascading More Stages

• LSB of last stage becomes very small • Impractical to generate several Vref

VinADC

+-DACADC

B3 bitsB2 bitsB1 bits

Vref Vref /2B1 Vref /2(B1+B2) Vref /2(B1+B2+B3)


Inter-Stage Gain Elements

• Practical pipelines use single Vref• Precision requirements decrease down the pipe

– Advantageous for noise, matching (later)

Vin ADCB3 bitsB2 bitsB1 bits

Vref

2B1

+-DACADC

Vref Vref Vref

2B22B3


Complete Pipeline StageVin +

-B-bitDAC

B-bitADC

D

-G Vres

Vin0

0

Vref

−εq1

“ResiduePlot“

E.g.:B=2

G=22 =4

Vres

Vref


Errors

• We cannot build perfect ADCs, DACs and gain elements

• How can we tolerate/correct errors?• Let's first look at sub-ADC errors• Assumptions:

– Ideal DAC, ideal gain elements


ADC Model

1 q2 2out in,ADC q1

d1 d1 d 2

q( n 1) ( n 1) qnn 2 n 1

d( n 1)dj djj 1 j 1

G GD V 1 1

G G GG

.. . 1GG G

εε

ε ε− −− −

−

= =

⎛ ⎞ ⎛ ⎞= + − + − +⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠⎛ ⎞⎜ ⎟+ − +⎜ ⎟⎝ ⎠∏ ∏

ΣΣ

εq1

- G1

Σ

ΣΣ

εq2

- G2

Σ

ΣΣ

εq(n-1)

- Gn-1

Σ

Vin,ADC

Dout 1/Gd1 1/Gd2

Vres1 Vres2 Vres(n-1)

Σ

1/Gd(n-1)

εqnD1 D2 D(n-1)Dn


ADC Model• If the "Analog" and "Digital" gain/loss match

exactly, we get:

∏−

=

+= 1

1

, n

jj

qnADCinout

GVD

ε

j

n

jnADC GBB ∑

−

=

+=1

12log


Observations

• The aggregate ADC resolution is independent of sub-ADC resolution

• Effective stage resolution Bj=log2(Gj)

• Conversion error does not (directly) depend on sub-ADC errors!

• Only error term in Dout contains quantization error of last stage

• So why do we care about sub-ADC errors?Go back to two stage example


Sub-ADC Errors

∏−

=

+= 1

1

, n

jj

qnADCinout

GVD

ε

1

2, G

VD qADCinout

ε+=

Grows outside ½ LSB bounds

Vin,ADCADCB1 bits

Vref Vref

Vres1

V εq2Vin0

0

Vref

Vres1

ref


Sub-ADC Errors

Ideal 2-Stage Pipelined ADC 2-Stage Pipelined ADC with Coarse ADC Comp. Offset

Vin VinVinVin


1st-Stage Comparator Offset

First stage ADC Levels:(Levels normalized to LSB)Ideal comparator threshold: -1, 0, +1Comparator threshold including offset:-1, 0.3, +1

Problem: Vres1 exceeds 2nd pipeline stage overload range

Missing Code!

Overall ADC Transfer Curve

Vres1

Vres2


Three Ways to Deal with Errors...

• All involve "sub-ADC redundancy"• Redundancy in stage that produces

errors– Choose gain for 2nd stage < 2B1

– Higher resolution sub-ADC• Redundancy in succeeding stage(s)


(1) Inter-Stage Gain Following 1st stage < 2B1

• Choose G1 slightly less than 2B1

• Effective stage resolution becomes non-integer B1eff=log2G1

Ref: A. Karanicolas et. al., JSSC 12/1993

VinVref0

0

Vref

Vres1

Vin,ADCADCB1 bits

Vref Vref

εq2

Vres1


Correction Through Redundancy

“enlarged” residuum still within input range of next stage

If G1=2 only 1 Bit resolution from first stage (3 Bit total)

Overall ADC Transfer Curve

Vres1

Vres2


(2) Higher Resolution Sub-ADC

• Keep G1 precise power of two (e.g. keep G1=4)

• Add extra decision levels in sub-ADC (e.g. add 1 extra bit to 1st

stage)

• E.g. B1=B1eff+1

Ref: Singer et. al., VSLI1996

Vin

Vref00

Vref

Vres1

Vin,ADCADCB1 bits

Vref Vref

εq2

Vres1


(3) Over-Range AccommodationThrough Increase in Following Stage Resolution

• No redundancy in stage with errors

• Add extra decision levels in succeeding stage

Ref: Opris et. al., JSSC 12/1998

Vin

Vref00

Vref

Vres1

Vin,ADCADCB1 bits

Vref Vref

εq2

Vres1


Redundancy• The preceding analysis applies to any stage

in an an n-stage pipeline• Can always perceive a multi-stage pipelined

ADC as a single stage + backend ADCVin

B4 bitsB3 bitsB2 bitsB1 bits

VinB2+B3+B4 bitsB1 bits


Redundancy• In literature, sub-ADC redundancy schemes

are often called "digital correction" – a misnomer!

• No error correction takes place• We can tolerate sub-ADC errors as long as:

– The residues stay "within the box", or– Another stage downstream "returns the residue to

within the box" before it reaches last quantizer• Let's calculate tolerable errors for popular

"1.5 bits/stage" topology


1.5 Bits/Stage Example

• Comparators placed strategically to minimize overhead

• G=2

• Beff=log2G=log22=1

• B=log2(2+1)=1.589...

Ref: Lewis et. al., JSSC 3/1992

Vin

Vref00

Vref

Vres1

Vref/8


3-Stage 1.5-bps Pipelined ADC

• All three stagesComparator with

offset

• Overall transfer curve

No missing codesSome DNL error

Ref: S. Lewis et al, “A 10-b 20-MS/s Analog-to-Digital Converter,” J. Solid-State Circ., pp. 351-8, March 1992

Overall Transfer Curve

Vres1

Vres2

Vres3


Inter-Stage Amplifier Offset

• Input referred converter offset – usually no problem• Equivalent sub-ADC offset - accommodated through

adequate redundancy

+

ADC DAC-

D

VresVin G+

Vos +

-Vos

+

Vos


Gain Errors

1, 1

1

2 ( 1) ( 1)22 1

1 2 ( 1)

1 1

1

1 ... 1

out in ADC qd

q q n n qnn n

d d d ndj dj

j j

GD VG

GGG G G

G G

δεδ

ε ε ε− −− −

−

= =

⎛ ⎞+= + −⎜ ⎟+⎝ ⎠⎛ ⎞⎛ ⎞

+ − + + − +⎜ ⎟⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠∏ ∏

ΣΣ

εq1

- G1+δ

Σ

ΣΣ

εq2

- G2

Σ

ΣΣ

εq(n-1)

- Gn-1

Σ

Vin,ADC

Dout 1/(Gd1+δ ) 1/Gd2


Σ

1/Gd(n-1)

εqnD1 D2 D(n-1)Dn

Small amount of gain error can be tolerated


Interstage Gain Error

1 0.5 0 0.5 11

0

1First Stage Residue (Gain Error)

Vin

Vre

s

1 0.5 0 0.5 11

0

1Converter Transfer Function (Gain Error)

Vin

Dou

t1 0.5 0 0.5 1

0.2

0

0.2Transfer Function Error(Gain Error)

Vin

Dou

t(ide

al) -

Dou

t


Gain Errors

• Gain error can be compensated in digital domain – "Digital Calibration"

• Problem: Need to measure/calibrate digital correction coefficient

• Example: Calibrate 1-bit first stage

• Objective: Measure G in digital domain


ADC Model

( )DACinres VVGV −⋅=1

2/)1(0)0(

refDAC

DAC

VDVDV

====

2

VrefG Vin⎛ ⎞⎜ ⎟⋅ −⎝ ⎠

inG V⋅


Calibration – Step 1

Vin= const.+

-1-bitDAC

1-bitADC

D

GVres1

(1)

BackendDback

(1)

MUX

“1“

Vref

( )( )

storeVVV

GD

VVGV

ref

refinback

refinres

→−

⋅=

−⋅=

2/

2/

)1(

)1(1


Calibration – Step 2

Vin= const.+

-1-bitDAC

1-bitADC

D

GVres1

(2)

BackendDback

(2)

MUX

“0“

Vref

( )( ) storeVVGD

VGV

ref

inback

inres

→−⋅=

−⋅=0

0)2(

)2(1


Calibration – Evaluate

( )

( )

GDD

VVGD

VVV

GD

backback

ref

inback

ref

refinback

⋅=−

−−−−−−−−−−−−−−−−−

−⋅=−

−⋅=

21

0

2/

)2()1(

)2(

)1(


Accuracy Bootstrapping

• Highest sensitivity to gain errors in front-end stages

∏∏−

=

−

−−

=

− +⎟⎟⎠

⎞⎜⎜⎝

⎛−++⎟⎟

⎠

⎞⎜⎜⎝

⎛−+⎟⎟

⎠

⎞⎜⎜⎝

⎛−+= 1

1

)1(

)1(2

1

)1(

2

2

1

2

1

11, 1...11 n

jdj

qn

nd

nn

jdj

nq

dd

q

dqADCinout

GGG

GGG

GGGVD

εεεε

ΣΣ

εq1

- G1

Σ

ΣΣ

εq2

- G2

Σ

ΣΣ

εq(n-1)

- Gn-1

Σ

Vin,ADC

Dout 1/Gd1 1/Gd2


Σ

1/Gd(n-1)

εqnD1 D2 D(n-1)Dn


"Accuracy Bootstrapping"

VinBn bitsStage 3Stage 2Stage 1 Stage k

“Sufficiently Accurate“Direction of Calibration

Ref:

A. N. Karanicolas et al. "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Of Solid-State Circuits, pp. 1207-15, Dec. 1993

E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs," TCAS II, pp. 143-153, March 1995

L. Singer et al., "A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz," ISSCC 2000, Digest of Tech. Papers., pp. 38-9

→ Calibration in opposite direction...


DAC Errors

• Can be corrected digitally as well• Same calibration concept as gain errors

Vin +-

B1-bitDAC

D

GVres1

Dback

B1-bitADC +

Dout+ 1/G

εDAC

-+

Backend


DAC Calibration – Step 1

• εDAC(0) equivalent to offset - ignore

+-

B1-bitDAC

D

GVres1

Dback

B1-bitADC +

Dout 1/G

εDAC(0)

BackendVin= const.

MUX

“0“

+


DAC Calibration – Step 2...2B1

• Stepping through DAC codes 1...2B1-1 yields all incremental correction values

+-

B1-bitDAC

D

GVres1

Dback

B1-bitADC +

Dout+ 1/G

εDAC(1...2B1-1)

-

BackendVin= const.

MUX

1...2B1-1

+

Cal. Register


Calibration Hardware

• Digital is "free" and easier to build than precise analog circuits...Ref: E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of

monolithic pipelined ADCs," TCAS II, pp. 143-153, March 1995


Amplifier Nonlinearity

VIN1 VRES1

DAC

D1

-

a3V3

+23

ADC

+

VOS

+

+εADC

+εDAC

εgain


Amplifier Nonlinearity

Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue Amplification," ISSCC Dig. Techn. Papers, pp. 328-329, 2003

VRES1

a3VX3

+ BackendDB DB,corr

(...)

+-

...D12pD3pDp)p,(D 7B

32

5B

22

3B22B +−+−=ε

VX

ε(DB, p2)33

32

εgain )(2ap+

=

23

εgain


Measurement Results12bit ADC w Extra 2bits for Calibration

0 1000 2000 3000 4000-1

-0.5

0

0.5

1(b) with calibration

C d

0 1000 2000 3000 4000

-10

0

10

(a) without calibration

Code

INL

[LS

B]

RNG=0RNG=1

0 1000 2000 3000 4000

-10

0

10

(b) with calibration

Code

INL

[LSB

]

Documents

EE247 Lecture 22 ADC Converters Pipelined ADCsee247/fa05/lectures/L22_f05.pdfEECS 247 Lecture 22: Data Converters © 2005 H.K. Page 11 Two Stage Example • Fine ADC is re-used 22