EE 421 Final Project The Boost Switching Power Supplycmosedu.com/jbaker/students/david/myStuff/The Boost Switching P… · Enable, that will be used in Part III of the Boost Switching

EE 421 – Final Project

1

The Boost Switching Power Supply: By David Santiago

[email protected]

EE 421 – Digital Integrated Circuit Design

Project Due Date: 11/29/19 at 5:00pm, via email

Table of Contents: Page # Part I – The Band Gap Circuit…………………………………………………. 5

Part I Layouts………………………………………………………………….. 9

Part II – The Feedback Sensor…………………………………………………. 10

Part II Layout of the Feedback Sensor…………………………………………. 16

Transient Simulations of the Feedback Sensor………………………………… 22

Part III – The Ring Oscillator, Buffer, and NMOS devices…………………… 25

Part III Layouts and Conclusions……………………………………………… 33

Part IV – The Boost Power Supply…………………………………………….. 37

The Boost Power Supply Simulations………………………………………….. 41

Conclusions for the Boost Power Supply, Design, and Tradeoffs…………….. 49

Pad Frame Layout………………………………………………………………. 50


2

Summary of Report: Tables: DC Sweep of the Feedback Sensor, Varying Temperature

Temperature °C (at VDD = 5V) Enable goes LOW at Vout =

0° 7.512 V

25° 7.508 V

50° 7.497 V

75° 7.483 V

100° 7.467 V

DC Sweep of the Feedback Sensor, Varying VDD

DC Sweep of the Feedback Sensor, Varying both VDD and Temperature

VDD (at Temp = 27°C) Enable Goes LOW at Vout =

3.75 V 7.487 V

4.25 V 7.497 V

4.75 V 7.504 V

5.25 V 7.511 V


3

Transient of the Feedback Sensor, Varying Temperature

Temperature °C (at VDD = 5V,) Duty of Enable

0° 76%

25° 65%

50° 45%

75° 16%

100° 2%

Transient of the Feedback Sensor, Varying VDD

VDD Duty of Enable

3.75V 25%

4.25V 43%

4.75V 57%

5.25V 71%

NMOS Triode Effective Resistance:

VDD Triode Resistance

3.75 V 3.53Ω

4.25 V 3.23Ω

4.75 V 2.96Ω

5.25 V 2.74Ω

Boost Switching Power Supply, Varying VDD, Temp = 27°C

VDD VoutMIN VoutMAX VAVE VRipple IL,MAX IVDD,AVE ILoad Efficiency

3.75 V 7.485 V 7.489 V 7.487V 4.3mV 108.3

mA

46.8 mA 20mA 85.3%

4.75 V 7.502 V 7.506 V 7.504 3.97mV 95.7mA 37.9mA 20mA 83.3%

5.25 V 7.509 7.514 V 7.512mV 5.24mV 100.8mA 34.87mA 20mA 82.1%

Boost Switching Power Supply, Varying Temperature, VDD = 4.5V

Temp VoutMIN VoutMAX VAVE VRipple IL,MAX IVDD,AVE ILoad Efficiency

0°C 7.504V 7.509V 7.5065V 5.2mV 109.1mA 39.95mA 20mA 83.5%

25°C 7.499V 7.502V 7.5055V 4.05mV 92.7mA 39.66mA 20mA 84.1%

50°C 7.489V 7.493V 7.491V 5.24mV 104.7mA 39.52mA 20mA 84.2%

75°C 7.475V 7.481V 7.4785V 6.12mV 115.5mA 39.41mA 20mA 84.3%

100°C 7.460V 7.462V 7.461V 2mV 83.5mA 38.8mA 20mA 85.4%


4

Efficiency Curve, Varying the Inductor and Capacitor, VDD = 4.5V

Average Efficiency 84%

NMOS Switch 75/0.6, m = 24

Long L Inverters for Ring Oscillator 18μ

Frequency (Slowest) (VDD = 3.75V) 568kHz

Frequency (Nominal)(VDD = 4.5V) 700kHz

Inductor 75μH

Capacitor 15μF

Diode 1N5711


5

Part I: The Band Gap Circuit

In this part, we will investigate how the Band Gap Voltage Reference circuit works.

Below is the circuit used for the bandgap:

Figure 1 - The BandGap Reference (BRG) Circuit Schematic

The circuit above is a Parasitic Diode-Based BandGap Reference (BGR) Circuit. This circuit will

try to keep a constant reference voltage with changes in VDD and temperature. The diodes exhibit

a Complementary To Absolute Temperature (CTAT) behavior, where Vref decreases with rising

temperature, while the resistors exhibit a Proportional To Absolute Temperature (PTAT) behavior,

where Vref increases with rising temperature. Also with this topology, we will have cascaded

NMOS and PMOS devices in the diode branches, which will try to keep the reference voltages at a

constant value with changes to VDD.


6

Simulation of the BandGap Reference Circuit: Suppose we have the following test circuit:

Figure 2 - BGR: Simulation Circuit

The first half of simulations will be with changes to VDD and the temperature.

The second half will be the same simulations but on the parasitic diode in the BGR.

Bandgap: Change of VDD:

Figure 3 - BGR: Changes in VDD, Simulation Above, we can see that the voltage reference, VREF, is roughly constant when VDD sweeps from

3.75V ≤ VDD ≤ 5.5V. The current will go up exponentially when VDD ≤ 4.5V, however, this

current is in the microamps (μA) range, which will be small relative to the current that will be

driven in bigger devices such as an inductor or load.


7

Bandgap: Change of Temperature:

Figure 4 - BGR: Changes in Temperature, Simulation

From above, with a change of temperature of about 100°C, we will get a maximum of about 7.5mV

change in the reference voltage.

This is around 7.5 Parts Per Million (PPM) per degree Celsius.

The average PTAT value for an N-Well Resistor is 2,000 PPM/°C. Comparing these two, we can

conclude that the BGR does not vary much with changes in VDD and Temperature.

Simulation of the Parasitic Diode: Suppose we have the following diode:

We will do the same tests on the diode as we did with the BGR.

The diode will exhibit CTAT behavior. A great example of where the

effect of the diode’s CTAT properties overcomes the resistor’s PTAT

properties are shown in Figure 4.

Below is how VREF can be affected by both the diode and the resistor.

Figure 6 - CTAT/PTAT Characteristic Equation for VREF

From Figure 4, we can predict that the CTAT property of VREF is due to

the CTAT property of the diode.

Figure 5 - Parasitic Diode, Schematic


8

Parasitic Diode: Changes in VDD:

Figure 7 - Parasitic Diode: Changes in VDD, Simulation

This curve corresponds to the typical behavior of diodes, where there is no current flow in the diode

until the voltage between the diode is greater than a threshold voltage. In this case, the diode

threshold voltage, VTHD, is around 700mV.

Parasitic Diode: Changes in Temperature:

Figure 8 - Parasitic Diode: Changes in Temperature, Simulation

In this simulation, we can see that there is a huge negative linear change in the reference voltage.

For 100°C, we can estimate about a -190mV change in voltage, or -1,900 PPM/°C.

However, for the bandgap, the circuit tries taking care of making the reference voltage not a

function of temperature.


9

Part I Layouts: The Bandgap Reference Circuit. Note the resistors are high

res poly resistors. The

high-res resistance is

1.192kΩ/sq, where for a

52kΩ resistor, W = 1.8μm,

L = 78.6μm.

For a 34kΩ resistor, W =

1.8μm, L = 51.3μm.

Figure 9 - The Bandgap Reference Circuit, Layout


10

Conclusions for the Bandgap Reference Circuit: The BGR is helpful for keeping the output voltage, VREF, constant with changes in VDD and

temperature. There is a drawback however, since the lowest voltage we can get to be 3.6V, but we

will assume that our circuit will not operate that low. The BGR is CTAT, but not as much that will

affect the reference voltage. The power that the BGR uses is around 3μA, which compared to the

current in an inverter or ring oscillator, is small, so it can be neglected.

In short, the BGR will be a helpful voltage reference to help with Part II of the Boost Switching

Power Supply.

---------------------------------------------------------------------

Part II: The Feedback Sensor For this part, we will design a sensor that will sense a high voltage, and using the Bandgap

Reference Circuit, compare both the BGR reference voltage and sensed voltage and output a signal,

Enable, that will be used in Part III of the Boost Switching Power Supply.

The sensed voltage will be around 7.5V, and with a 1/6th voltage divider we can compare this

voltage with the BGR. When the sensed voltage goes higher than 7.5V, the output of the sensor is

LOW, and vice versa.

We will have the following circuit:

Figure 10 - The Feedback Sensor, Schematic

The input to the non-inverting input of the comparator is the BGR.

The input to the inverting input of the comparator is a 1/6th Voltage Divider.

The output of the Comparator is Enable. The Comparator will contain several chains of

comparators to add a little bit of hysteresis so that when Vout goes high, Vout can dip below the

comparator value for a reasonable amount before it needs to come back up. This is the hysteresis

effect, where the sensed output will be below the comparator value while the enable is LOW, but

the delay will be long enough before the enable goes HIGH again. Below is a quick diagram of

how the hysteresis works with our sensed voltage.


11

Figure 11 - Showing How Hysteresis works with our Sensed Voltage, Vout

The analogy to hysteresis is cooling down a house with an air conditioner, where when we hit a

high temperature, we would want to cool the house down, turn off at a certain cold temperature,

and then let the house heat up so that the average temperature will be the average time at all

temperatures.

Figure 12 - Hysteresis Analogy: AC Conditioning

Here is the schematic of the voltage divider:

Figure 14 - The 1/6th Voltage Divider, R = 40kΩ

The current should be less than 50uA. Vout will be around 7.5V, therefore, the minimum resistance

will be 150kΩ, or six 25kΩ resistors. For our design, we chose R = 40kΩ so that we can use a

current that is 31.25μA. We will have a longer RC delay however, we can disregard this effect.

Figure 13 - The 1/6th

Voltage Divider, Symbol


12

Comparator with Hysteresis:

Figure 15 - The Comparator with Hysteresis, Symbol

Figure 16 - The Comparator with Hysteresis Devices, Schematic

Each smaller comparator is a self-biased comparator, in which the current mirror NMOS device’s

gate is not connected to any other external voltage source other than itself.

The Inverter after the output of the 3rd comparator is there to “tune” or control the voltage

switching point. In this case, making the PMOS weaker with shorter W (or NMOS stronger with

higher W) will drag the switching point down. The theory behind this is that if our sensed voltage

Vout is not around 7.5V (or at the voltage that we want it to be), then we can tune the widths of one

inverter until we get the voltage that we will ripple around.

The Self-Biased Differential Amplifier:

Figure 17 - Self-Biased Diff Amp, Symbol

Figure 18 - Self-Biased Diff Amp, Schematic


13

Seen in Figure 16, the NMOS N2’s gate is connected to the current mirror PMOS devices. The gain

from the Minus pin on N0 (center right) is much higher than the Plus pin on N1 (center left) since

the PMOS P1 is gate-drain connected and will have a much lower effective resistance than P0 (top

right). Therefore, our reference voltage from the BGR will be the input to the Plus terminal.

Note, the circuit will need to be laid out, and this might be a pain. Suppose we look at how a diff-

pair is laid out:

Figure 19 - Example of a Diff-Pair Common-Centroid Layout

This type of layout is a Common-Centroid layout. This is where we would want to see equal

geometries and differences in gradient changes of substrate resistance.

For a current mirror layout:

Everything will revolve on trying to keep the

matching the same throughout the entire

devices. Yes we might introduce some

additional parasitic impedances, however, the

geometries will keep mismatching at a

minimal.

We will change the original schematic to have

multiple fingers so that we can do this kind of

layout.

Figure 20 - Example of a Current Mirror Common-

Centroid Layout


14

New Schematic:

Figure 21 - Using a Multiplier for our CMOS Devices

From this, all the devices have widths of 3μm, with

the PMOS devices having a multiplier of 4 and the

NMOS devices having a multiplier of 2.

Layout: Self-Biased Diff Amp:

Figure 22 - The Differential Amplifier, Layout

From this, we have combined two common-centroid techniques to minimize mismatching. We will

do one large LVS nearing the end of the report.


15

Layout of the Comparator with Hysteresis:

Since we designed the diff-amps to go from left to right, connecting all the layout pieces together

was simple. The inverters at the end are there to help drive the signal, Enable, out of the

Comparator.

Layout of the 1/6th Voltage Divider:

We have designed our voltage

divider to have a common-

centroid, so that there is better

matching of resistances, but at the

cost of some uneven fringe

parasitic impedances. Also, the

use of unit resistors keeps the

process shifts, temperature

coefficients, and power dissipation

constant.

We used a hi-res poly layer, W =

1.2μm, L = 40.2μm, for a unit

resistor of 39.93kΩ.

Figure 23 - The Comparator with Hysteresis, Layout

Figure 24 - The 1/6th Voltage Divider, Layout

Figure 25 - Resistance of the Unit Resistor = 39.93kΩ


16

Layout of the Feedback Loop:

Figure 26 - The Feedback Sensor, Layout


17

Figure 28 - Parametric Analysis on Temperature

Simulations of the Feedback Sensor:

Temperature Simulation: Suppose we have the following simulation:

Figure 27 - The Feedback Sensor, Simulation

Lets perform a DC Sweep on Vout (the sensed voltage) from 7V to 8V and look at how the Enable

responds to a DC sweep. We will also look at the temperature changes using a parametric analysis

toolkit in the Analog Design Environment (ADE).

Setting up the ADE:

Figure 29 - DC Sweep in ADE

Note, we will have VDD = 5V for the following Simulations.


18

Figure 30 - Vout vs Enable, Parametric Analysis Simulation, Pink = 0°C, Green = 25°C, Blue = 50°C,

Magenta = 75°C, Orange = 100°C

Table 1 - Enable Going LOW, Sweeping Vout, Temperature Simulation

Temperature °C (At VDD = 5V) Enable goes LOW at Vout =

0° 7.541 V

25° 7.535 V

50° 7.525 V

75° 7.510 V

100° 7.494 V

As temperature goes up, the point where the Enable goes LOW begins at a lower sensed Vout.

This is due to the Bandgap Temperature Simulation in Figure 4, where the BGR voltage goes down

a bit. Therefore, the comparator will have a lower reference voltage for Vout, and consequently,

Enable goes LOW earlier at higher temperatures when Vout approaches 7.5V.

The problem here is that 50°C (around the heat that will be dissipated in a phone or circuit), the

switching point is too high! We will need to change the switching point of the inverters so that we

can get around 7.5V.


19

Tuning the inverters of the comparator:

Figure 31 - Changing the Comparator Switching Points

We make the PMOS stronger so that when the input dips from VDD to VDD-VTHP, it doesn’t take

much of a change in VSG to switch the PMOS on. In an ideal world, the switching point is VDD/2

for the inverter. If we want it to be higher, the PMOS will need to turn ON sooner when we sweep

from VDD to GND. Therefore, by changing VSG to be smaller (the PMOS can turn on at lower gate

to source voltages), we can change the switching point to be at higher voltages.

The governing equation (under saturation conditions) for the gate-source voltage is:

When the width of the PMOS goes up, VSG will go down, therefore, the

PMOS has an easier time turning ON (pulling the output to VDD).

Resimulation:

From this, the switching points are

now closer to 7.5V with varying

temperature.

Equation 1 - Equation to

change VGS of a device

Figure 32 - Vout vs Enable, Parametric Analysis Simulation, Pink =

0°C, Green = 25°C, Blue = 50°C, Magenta = 75°C, Orange = 100°C,

Resimulation.


20

Table 2 - Enable Going LOW, Sweeping Vout, Temperature Resimulation

Temperature °C (at VDD = 5V) Enable goes LOW at Vout =

0° 7.512 V

25° 7.508 V

50° 7.497 V

75° 7.483 V

100° 7.467 V

The design choice was we assume that the user will be working at around nominal room

temperature, 27°C. We will assume that our test engineer will have a cooling solution if the

temperature of the device were to go more than 50°C (122°F).

VDD Simulation: Suppose we have the following: Figure 33 - Vin vs Enable, VDD Simulation

For this, we are going to do a parametric analysis

on VDD. Note that we will keep Temp = 27°C.

From Figure 34, we can see that

with higher VDD supply voltage,

the switching point goes up!

However, looking at the sim, we

are around 7.5V when VDD is

between 3.5V and 5.25V (we are

designing around the center of

these two voltages).

Figure 34 - Vout vs. Enable, VDD Simulation, Blue = 3.75V, Pink =

4.25V, Green = 4.75V, Light Blue = 5.25V


21

Table 3 - Enable going LOW, Sweeping Vout, Changing VDD

Enable goes LOW much sooner at lower VDD. This is due to the Bandgap again, where when

VDD is near 3.6V, VREF is not at 1.25 V and is lower by a few millivolts.

Grand Simulation: Changing Temperature and VDD We will be using MATLAB to plot a 3D plot of when the Enable goes LOW.

We will run many simulations on the ADE and plotting their values in MATLAB, with the X axis

as VDD, Y axis as Temperature, and Z axis as the switching point of the Enable going LOW.

Figure 35 - Enable Switching Point, Varying VDD and Temperature

From this, when VDD and Temperature are both at lower values, the switching point is much

higher than 7.5V. However, as Temperature increases, the switching point will go as low as

7.451V. So, the optimal conditions for running a simulation is most likely at 20°C when VDD is

around 4.25V.

VDD (at Temp = 27°C) Enable Goes LOW at Vout =

3.75 V 7.487 V

4.25 V 7.497 V

4.75 V 7.504 V

5.25 V 7.511 V


22

Transient Simulations of The Feedback Sensor: Changes of Temperature, VDD = 5V, frequency @ 1MHz Using the same simulation circuit, we will do a transient analysis with changes to temp, VDD, and

both changes in temperature and VDD. The sensing voltage, Vout, will go at about

Figure 36 – Transient Simulation: Hysteresis of Enable at VDD=5V, Pink = 0°C, Green = 25°C, Blue = 50°C,

Magenta = 75°C, Orange = 100°C

Table 4 - Hysteresis of Feedback Sensor, Transient Simulation

Temperature °C (at VDD = 5V,) Duty of Enable

0° 76%

25° 65%

50° 45%

75° 16%

100° 2%

As the temperature goes up, we recall that the switching point of the Enable goes down, therefore,

for our triangle ripple Vout, if the ripple is not big enough, we will not have a good hysteresis

feedback.

In practice, our ripple will be huge since Vout will continue to go down, way below 7.5V, and this

will cause an unstable ripple that will need to take in a big capacitor, at the cost of storing more

energy from an inductor load.


23

Changes of VDD, Temp = 27°C, frequency @ 1MHz:

Figure 37 - Transient: Hysteresis of Feedback Sensor, Varying VDD, Blue = 3.75V, Pink = 4.25V, Green =

4.75V, Light Blue = 5.25V

Recalling from the DC sweeping simulation in figure 34, the switching point goes up with higher

VDD supply voltages, therefore, the duty cycle of the feedback sensor will be higher at higher

VDD.

Table 5 – Hysteresis of Feedback Sensor: Changing VDD, Transient

VDD Duty of Enable

3.75V 25%

4.25V 43%

4.75V 57%

5.25V 71%


24

Conclusions for the Feedback Sensor: For the Feedback sensor, we needed to implement a hysteresis effect so that when the sensed

voltage goes above a certain value, the sensor will output LOW (in other words, disable) to the next

stage of The Boost Switching Power Supply, The Ring Oscillator.

For the sensor to work, the sensed voltage will be stepped down using a voltage divider, and this

voltage will be compared to a reference voltage. The comparison in the chain of self-biasing

differential amplifiers will cause a delay, which will be our hysteresis effect that will make sure

that when the sensed voltage goes lower than the compared voltage, the Enable (Ring Oscillator)

will be LOW, thus saving power, until we need more voltage at Vout.

Figure 38 - The Feedback Sensor, Symbol


25

Figure 39 - Ring Oscillator Hand Calcs

Part III: The Ring Oscillator, Buffer, and NMOS Switch

Using the Feedback Sensor that was created in Part II, we will now create a ring oscillator and

buffer system that will be able to drive/enable an NMOS switch that is connected from GND to the

output of a chip, which will go into an off-chip inductor and Schottky Diode.

The first part will be designing a Ring oscillator. For this, we will choose a frequency of around

1MHz. We will use a combination of long length inverters, regular 12/6 inverters, and two NAND

gates that will help with the Duty Cycle. The design duty cycle will be over 50%, since the parasitic

resistance in the inductor, the diode voltage drop, and the NMOS resistance will all affect the

response of Vout.

For the ring oscillator, we have chosen to use 26 Long Length inverters of L = 18μm, 6 normal

inverters, and 1 NAND gate in the Ring Oscillator Loop.


26

The Ring Oscillator:

Figure 40 - The Ring Oscillator, Schematic

Simulation of the Ring Oscillator:

Figure 41 - The Ring Oscillator, Simulation

From the Hand Calcs to the actual simulation, we are close to our simulation results. The

frequency is around 500-600kHz, Duty = 69%. We should also recall that since we are using

faster switching, the effective resistance will not be the same throughout the entire ring oscillator,

where we could be working partially in the triode region (the resistance can be lower than

expected).

We have chosen to design with the Long L inverters so that we will consume less power and we

will have a lower frequency. This also means that our efficiency will go up as we will use less

current. Consequently, we will need to use a larger NMOS switch, and therefore, a stronger buffer.

The other drawback is that in using a larger inductor, the response time will go up, and we will see

a larger ripple at Vout.


27

The engineering decision is to have higher efficiency and use less current, at the cost of a longer

response time and a larger ripple voltage at Vout. In order to reduce the ripple, we will use a larger

capacitor, but that will demand more energy to keep Vout steady.

Layout of the Ring Oscillator:

The ring oscillator has one common VDD line,

where half of the other long L inverters are upside

down, returning to the beginning of the circuit.

Figure 42 - The Ring Oscillator, Layout

Figure 43 - The beginning of the Ring

Oscillator, NAND gate at bottom right

Figure 44 - The end of the Ring Oscillator, output at

bottom Right


28

The NMOS Switch: For the switch, the approach is that we will want to keep VDS as small as possible (close to GND).

So, for this design, the NMOS switch’s sizes will be minimum L (for high speed current), and large

W so that the resistance of the NMOS switch from the Drain to GND is small.

Since there will be at the bare minimum 20mA (assuming all current goes into the resistive load),

the effective resistance (which will be a small number, around 20Ω) times 20mA = 200mV.

The power dissipated would then be 200mV x 20mA = 1μW.

Note however, this assumes that the gate of the NMOS will be switched to VDD, which can also

vary. If the gate does not have a high potential, the Electric field between the plate and the body

substrate will be small, meaning less electrons are in the channel region. Consequently, at lower

gate voltages (different VDDs), the effective resistance will be higher at lower VDD.

We will select a W = 75μm, L = 600nm, multiplier of 24, NMOS switch, and run a simple

characteristic simulation of sweeping VDS at different VGS levels that are equal to VDD.

The equation for the resistance of an NMOS is: Equation 2 - Effective Resistance Equation

Creating a sim to see the resistance at the triode region at different VDDs:

Figure 45 - Sweeping VDS, Changing VGS/VDD, Red = 3.75V, Yellow = 4.25V, Green = 4.75V, Light Blue =

5.25V


29

Table 6 - Triode Resistance for the NMOS Switch

VDD Triode Resistance

3.75 V 3.53Ω

4.25 V 3.23Ω

4.75 V 2.96Ω

5.25 V 2.74Ω

Figure 46 - Digital Model of the NMOS Switch

Since we have a huge NMOS, we will have a drain voltage that is low.

However, one thing will arise: we first have a huge gate capacitance on the NMOS, consequently, a

regular inverter will not be able to pull or charge this capacitance up.

In this next section, we will design a buffer system that will be able to drive this gate.

Layout of the NMOS Switch: We will have a simple schematic, shown below:

Figure 48 - The Switching NMOS, Schematic

Figure 47 - The Switching NMOS, Symbol


30

The reason for a large multiplier and

not one super wide NMOS is so that

our device will fit in a layout, and

plus the area that it will take will be

much smaller. In the figure to the

right, we can see that this a nice

square, where on the top left side

(the m1_poly via) is the input to the

gate of the NMOS, and the top of the

NMOS is where we will connect to a

pad that will go off-chip.

The Buffer System: For our Boost Switching Power Supply Design, we will want to drive a W = 75μm, L = 600nm,

multiplier of 24, NMOS switch.

Figure 50 - Hand calculation of the Input Capacitance of the Switching NMOS

Therefore, we will design a buffer that will be able to drive this load. For safety, we will design a

buffer that is able to drive more than just 4pF, so the buffer will drive at least 10pF.

Figure 49 - The Switching NMOS, Layout


31

Figure 51 - Hand Calculation of the Buffer System

From these hand calculations, we can use N = 5 inverters, where the next inverter’s CMOS widths

are multiplied by A = 3.

This will be a large buffer, and for layout sizing, we will choose a 3-stage inverter, with a

multiplier of 7. This will not give us the ideal delay through the buffer, however, for layout sizing

and power consumption of using 3 inverters instead of 5, we will have a low-power inverter at the

cost of a small delay, which for now we can consider as negligible.

Figure 52 - The Buffer System, Schematic, 3 Stages, A = 7


32

From this simulation, we have around

a 1ns delay. Comparing this to our ring

oscillator which has a delay that is 3

orders of magnitude larger than the

buffer delay (tRingOsc is in μs range).

Layout of the Buffer System:

Figure 54 - The Buffer System, Layout

We use an inverting symbol for the buffer system, since we

have 3 stages of Inverters. If we wanted to make this a

normal non-inverting buffer, we would add a minimum

length 12/6 inverter at the beginning of the chain. Adding

this small inverter will make no additional change to our

propagation delay through the buffer system.

Figure 53 - The Delay Through The Buffer System

Figure 55 - The Buffer System, Symbol


33

Conclusions for Part III: With all of these modules, one thing that was the focal point is the frequency and duty cycle of the

ring oscillator. This component is the “heart” of the entire Boost Switching Power Supply.

However, with this fast frequency, to drive a heavy load such as a capacitance of a wide NMOS, a

buffer system is made so that we can not only have a device that can drive a heavy load, but also

can use less layout and low current. These pieces will now be placed into one big module, The

Boost Switching Power Supply, and we are ready to test varying loads, conditions, and layouts.

Complete Schematic:

Figure 56 - The Boost Switching Power Supply, Schematic

Figure 57 - The Boost Switching Power Supply, Symbol


34

Figure 58 - The Boost Switching Power Supply, Layout


35

Figure 59 - The Boost Switching Power Supply, Extracted


36

Big Global DRC:

Figure 60 - DRC of The Boost Switching Power Supply

Big Global LVS:

Figure 61 - LVS of the Boost Switching Power Supply

Figure 62 - Output File of LVS


37

Part IV: The Boost Switching Power Supply Now, with all the components built, we are ready to simulate different loads, power supplies, and

changes in temperature.

Suppose we have the following:

Figure 63 - The Boost Switching Power Supply Simulation

From the ring oscillator, the frequency that comes out is about 600kHz, with the duty cycle at

around 70%, the average current in the inductor can be found with:

Equation 3 - Average current in an Inductor

From this, the load will be 20mA, and therefore, the average current is 66.7mA.

To vary with 10% of this average current, we will then have a change of 6.6mA current.


38

Inductance: The inductance can be found with the following:

Equation 4 - The Inductance Equation

Doing the hand calcs, the inductance will be

Figure 64 - Hand calcs for Inductance

Since we will have extra current running through the inductor due to parasitic impedances, and our

clock frequency will not be on all the time, we will choose a smaller inductor of 75μH so that our

circuit is fast, however we will have a bigger ripple voltage.

The price for this inductor can be found on Digikey for 97 cents.

Figure 65 - 75μH Inductor on Digikey

Capacitance: For the minimum capacitance to give us the least amount of current dissipation for a good ripple

voltage, we use the following:


39

Equation 5 - Capacitance Equation

Doing the hand calcs:

Since we are using a large inductor and NMOS switch, to keep the ripple low, we will then use a

15μF capacitor, at the cost of efficiency.

The price for this capacitor is 46 cents on digikey.

Figure 66 - 15μF Capacitor on Digikey

Lets do a simple simulation, where the Inductor = 75μH, Capacitor = 15μF, at VDD = 4.75V


40

Diode: For this, we chose a 1N5711 Diode. The diode zero bias capacitance for this diode is small, and this

will be good to keep the oscillations at VDS Small.


41

Simple Simulation:

Figure 67 - SPS Simple Simulation, VDD = 4.75V, Temp = 27°C, Clock = 720KHz, D = 69%

VDD VoutMIN VoutMAX VRipple IL,MAX IVDD,AVE ILoad Efficiency

4.75V 7.502 V 7.506 V 3.9mV 95.7 mA 37.9mA 20mA 83.3%

From this simple simulation, we have a low ripple voltage, however, our efficiency is near 80%.

We notice that the Enable is about a 50% duty cycle, therefore, we can calculate the sensed voltage

output.

A rough estimate of the voltage at Vout is:

Equation 6 - Vout, With Enable Duty Cycle


42

Figure 68 - Hand Calculating Vout

The hand calcs are a bit off but are close to the voltage that we want.

Simulations:

Changes in VDD: We will have the following:

Figure 69 - Simulation Circuit of the SPS, Changing VDD

We will simulate at the lowest voltage, and then the highest voltage.


43

Setting up the ADE:

Figure 70 – Setting up the ADE, VDD = 3.75V, Temp = 27°C

Figure 71 - VDD =3.75V, Temp = 27°C


44

Figure 72 - VDD = 5.25V, Temp = 27°C

Table 7 - SPS: Varying VDD Simulation Table

VDD VoutMIN VoutMAX VAVE VRipple IL,MAX IVDD,AVE ILoad Efficiency

3.75 V 7.485 V 7.489 V 7.487V 4.3mV 108.3

mA

46.8 mA 20mA 85.3%

4.75 V 7.502 V 7.506 V 7.504 3.97mV 95.7mA 37.9mA 20mA 83.3%

5.25 V 7.509 7.514 V 7.512mV 5.24mV 100.8mA 34.87mA 20mA 82.1%

The correlation is that we have designed this to where at lower voltages, the efficiency is high. As

VDD goes up, the frequency in the Ring Oscillator also goes up, which also means that the duty

cycle of the Enable goes down.

The way the efficiency is calculated is based on what Virtuoso Visualizer plots, and we can use the

calculator function to send our current at VDD and find the average current.


45

Using the Calculator by right-clicking on the VDD current plot:

Figure 73 - How to Setup the Calculator

Simulation: Changing Temperature For this simulation, we will use the Parametric Analysis Tool, so that we can sweep at different

temperatures. For this simulation, we will have VDD = 4.5V.

Setting up the ADE:

Figure 74 - Setting Up ADE for Temperature Parametric Analysis


46

Figure 75 - Vout with Changing Temperature

Figure 76 - Inductor Current with Changing Temperature


47

Table 8 - Varying Temperature, VDD = 4.5V

Temp VoutMIN VoutMAX VAVE VRipple IL,MAX IVDD,AVE ILoad Efficiency

0°C 7.504V 7.509V 7.5065V 5.2mV 109.1mA 39.95mA 20mA 83.5%

25°C 7.499V 7.502V 7.5055V 4.05mV 92.7mA 39.66mA 20mA 84.1%

50°C 7.489V 7.493V 7.491V 5.24mV 104.7mA 39.52mA 20mA 84.2%

75°C 7.475V 7.481V 7.4785V 6.12mV 115.5mA 39.41mA 20mA 84.3%

100°C 7.460V 7.462V 7.461V 2mV 83.5mA 38.8mA 20mA 85.4%

Simulation: Varying the Resistive Load: Suppose we placed a current pulse at the load:

Figure 77 - Current Pulsed Load

Keeping the supply at VDD = 4.5V, Temp = 27°C:

Figure 78 - The Current Pulsed Load, Simulation


48

From this simulation, we can see that the sensed voltage, Vout, drops a bit, but it is remaining

relatively constant near 7.5V.

Simulation: Different Inductor/Capacitive Loads: Suppose we do not have the right inductor with us. For this simulation, we will look at 9 different

types of loads, and plot the efficiency in MATLAB.

Figure 79 - Efficiency, Varying Impedances, Ir = 20mA, VDD=4.5V

Figure 80 – Ripple Voltage, Varying Impedance, Ir = 20mA, VDD = 4.5V


49

From the graphs above, as we increase the inductance, the Efficiency will go up, however, the

ripple voltage will increase a lot. However, as we increase capacitance, ripple voltage will go

down, but the efficiency will drop by a small margin.

In practice, we will not have perfect inductors or capacitors, and with this graph, we can say that

we are at a rough 84% Efficiency throughout all impedances, and we might have a better benefit

using a higher capacitance, since the efficiency differences are small, that they can be negligible in

practical testing.

Conclusions for The Boost Switching Power Supply: Designs and tradeoffs: For our design, we chose to go with a slower clock cycle so that we are able to have an overall

good efficiency and drive our Resistive load. The tradeoff would then be speed, as we will need to

use a large inductor, which will consequently increase the impedance of the LC circuit when the

NMOS is turned OFF.

For a better efficiency, we chose to do a large NMOS W/L of 75/.6, multiplier of 24, since the

effective triode switching resistance (VDS < VGS – VTHN) is around 2Ω. The consequence of that is

that we will have a large capacitor (around 5pF) at the input gate of the NMOS, and we will need a

strong buffer to turn on the NMOS.

For the Buffer, we have designed a buffer that can drive up to 10pF capacitances. We chose a 3-

stage buffer so that we can use less switching power. The consequence of using less inverter stages

is that we will have a longer delay, however, comparing the delay to the delays of the ring

oscillator, it is minimal and can be negligible.

For the inductor, we went for a 75μH inductor, so that in conjunction with the low frequency

oscillation of around 500-600kHz, we can have better efficiency into our resistive load, but at the

cost of a slower response from the feedback loop and an output ripple of around 4mV.

For the capacitor, we went for a 15μF capacitor with the goal that we want higher efficiency.

However, looking at the Varying load MATLAB plot, if we use a higher capacitance, the efficiency

will go down but the effect is small that it can be neglected.


50

Pad frame of our circuit:

Documents

EE 421 Final Project The Boost Switching Power Supplycmosedu.com/jbaker/students/david/myStuff/The Boost Switching P… · Enable, that will be used in Part III of the Boost Switching