EE 3610: Digital Systems 1 - Weber State University · 2018. 11. 18. · EE 3610 Digital Systems Suketu Naik Functions: declaration 3 VHDL Functions (put in the declaration of architecture)

EE 3610 Digital Systems Suketu Naik

1

VHDL Functions

and Procedures,

Attributes,

Multivalued Logic

EE 3610: Digital Systems


2

VHDL Functions



3Functions: declaration

VHDL Functions (put in the declaration of architecture)

function (formal-parameter list) return

is

--variables, constants, not

signal)

begin

sequential statements --must have a return

end


4Functions: example 1

function Parity (a: std_logic_vector) return

std_logic is

variable b:std_logic:='0';

begin

for i in a'low(1) to a'high(1) loop

b:= b xor a(i);

end loop;

return b; --b is set to 1 if number of bits is

odd otherwise 0 if even

end parity;

VHDL Predefined Attributes:

http://www.csee.umbc.edu/portal/help/VHDL/attribute.html


5Functions: guidelines

▪ Formal parameters are of type "in" and can not be altered

▪ Expressions may be passed to functions (unlike signals)

▪ Parameters & return value can be vectors of arbitrary

length

▪ Function executes a squential algorithm & returns a value

▪ Return must always be a variable



function bit_count (a: std_logic_vector(3 downto 0))

return integer is

variable count:std_logic:='0';

begin

for i in 0 to 3 loop

if a(i)='1'then

count:= count+1;

end if;

end loop;

return count;

end bit_count;



Functions can only return

one variable (bit vector or bit)


9Functions: predefined functions

to_integer (A)

to_unsigned (B,N)

to_stdlogicvector (C)

shift_left (A,B)

rotate_right (A, B)

resize (A,B)


10

VHDL Procedures



11Procedures: declaration

VHDL Procedures (put in the declaration of architecture)

procedure (parameter list) is

begin

sequential statements

end

Parameter in in/out or out

Constant any expression N/A

Variable Variable Variable

Signal Signal Signal

'in' parameters are constant by default

'out' parameters are variable by default


12Procedures: example 1

procedure parity2

(a:in std_logic_vector;signal p:out std_logic) is

variable b:std_logic:='0';

begin

for i in a'range loop

b:= b xor a(i);

end loop;

p



procedure can return multiple

signals



library ieee;

use ieee.std_logic_1164.all;

package my_reg8 is

subtype byte8 is std_logic_vector(7 downto 0);

type iarr is array(integer range 0 to 3) of integer;

constant CLEAR8: byte8 := (others=>'0');

procedure dff8 (signal takt: in std_logic;

signal D: in byte8;

signal Q: out byte8);

end my_reg8;

package body my_reg8 is

procedure dff8 (signal takt: in std_logic;

signal D: in byte8; signal Q: out byte8)is

begin

if rising_edge(takt) then

Q


15Procedures: example 3 (continued...)library ieee;

use ieee.std_logic_1164.all;

use work.my_reg8.all;

entity myDFF is

port

(clk : in STD_LOGIC; datain: in std_logic_vector(7 downto 0);

dataout : out std_logic_vector(7 downto 0));

end myDFF;

architecture behav of mydff is

signal fromdip: byte8; signal toled: std_logic_vector(7 downto

0); signal arrtest: iarr;

begin

reg: process(clk)

begin

if(clk='1' and clk'event) then

fromdip



procedure READ(L:inout LINE; VALUE:out STD LOGIC VECTOR);

procedure READ(L:inout LINE; VALUE:out STD LOGIC VECTOR;

GOOD:out BOOLEAN);

procedure WRITE(L:inout LINE; VALUE:in STD LOGIC VECTOR;

JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);

For the last procedure, we may write:

WRITE(Lin, invec); the final two parameters assume values of

RIGHT and 0 respectively.


17VHDL Functions and Procedures

Functions and Procedures are called Subprograms

1) Functions and procedures in VHDL provide a

mechanism for representing commonly used logic

functions, and especially overloaded functions and

procedures for supporting types such as std_logic

2) Subprograms (functions and procedures) may be

declared in the declarations section of an architecture

body and within the declarations section of a process

3)The most common location to declare functions is

within packages which can be accessed with use


18VHDL Functions and Procedures

4) In functions, the formal parameters may be input to the

function and used as part of the computation of the return

value

5) Functions do not change the values of the parameters passed

to them; procedures can change the values of the parameters

passed to them

6) A procedure does not return a value, but formal

parameters that are replaced by the values of the actual

parameters


19Writing your own package

Packages allow flexibility and an overloaded operator to be defined

easily

Example:package EE3610pkg is

constant maxint: integer := 16#ffff#;

type arith_mode_type is (signed, unsigned);

function minimum(constant a,b: in integer) return integer;

end EE3610;

package body EE3610pkg is

function minimum (constant a,b: integer) return integer is

variable c: integer; -- local variable

begin

if a < b then

c := a; -- a is min

else

c := b; -- b is min

end if;

return c; -- return min value

end;

end EE3610pkg;

Package declaration

Package body


20

Attributes



21Attributes: Exampletype example is array (0 to 255, 7 downto 0) of

integer;

Useful for for loops

example'left(1)would be 0 (here 1=dimension 1= ‘rows’)

example'left(2)would be 7 (here 2=dimension 2= ‘columns’)

example'right(1)would be 255

example'right(2)would be 0

example'range(1) would be 0 to 255

example'range(2) would be 7 downto 0

example'length(1) would be 256


22Attributes: Simulation Only

T'LEFT is the leftmost value of type T. (Largest if downto)

T'RIGHT is the rightmost value of type T. (Smallest if downto)

A'LEFT(N) is the leftmost subscript of dimension N of array A.

A'RIGHT(N) is the rightmost subscript of dimension N of array A.

A'HIGH is the highest subscript of array A or constrained array

type.

A'HIGH(N) is the highest subscript of dimension N of array A.

A'LOW is the lowest subscript of array A or constrained array

type.

A'LOW(N) is the lowest subscript of dimension N of array A.

A'RANGE is the range A'LEFT to A'RIGHT or A'LEFT downto A'RIGHT

.

A'RANGE(N) is the range of dimension N of A.

A'LENGTH is the integer value of the number of elements in array A.

A'LENGTH(N) is the number of elements of dimension N of array A.

S'EVENT is true if signal S has had an event this simulation cycle.

S'ACTIVE is true if signal S is active during current simulation

cycle.

S'LAST_VALUE is the previous value of signal S.

VHDL Predefined Attributes:

http://www.csee.umbc.edu/portal/help/VHDL/attribute.html


23

Multivalued Logic



24Multivalued Logic Systems

4-valued logic system

'X' = Unknown

'0' = 0

'1' = 1

'Z' = High Impedance

▪ Used for tri-state buffers and buses

▪ If the initial value of signal is unknown or if a signal

is simultaneously driven to both '0' and '1'


254-Valued Logic System: Example

a b c d Output f

a 1 x 0 a

x 0 c 1 c

x 0 x 0 Z

x 1 x 1 Conflict

Note:

x in this table

represents

'don't care'


26Multivalued Logic Systems

IEEE 1164 9-valued logic system

'U' = Uninitialized (e.g. what you see first in simulation)

'X' = Forcing unknown

'0' = Strong or Forcing 0 (e.g. setting 0 with ground)

'1' = Strong or Forcing 1 (e.g. setting 1 with power supply voltage)

'Z' = High Impedance (e.g. open circuit or driven together with ‘0’

and ‘1’)

'W' = Weak Unknown

'L' = Weak 0 (e.g. setting 0 with pull-down resistor)**

'H' = Weak 1 (e.g. setting 1 with pull-up resistor)**

'-' = Don't care (e.g. you often see this in simulation)

**Weak 0 and Weak 1 examples:

https://learn.sparkfun.com/tutorials/pull-up-resistors

https://learn.sparkfun.com/tutorials/pull-up-resistors


27Application of Multivalued Logic System

1) IEEE 1164 9-valued logic system is used to model

signals and resolve conflicts

e.g. fourpack package shown on slide 25

Question: Suppose you happen to drive a signal such that

it has both ‘0’ and ‘H’, what should be the result?

Answer: ‘0’, Because ‘0’ takes precedence over ‘H’

2) IEEE 1164 9-valued logic system defines a standard for

AND, OR, NOT, XOR and other functions

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EE 3610: Digital Systems 1 - Weber State University · 2018. 11. 18. · EE 3610 Digital Systems Suketu Naik Functions: declaration 3 VHDL Functions (put in the declaration of architecture)