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EE 3610 Digital Systems Suketu Naik
1
MIPS:
Microprocessor
without
Interlocked
Pipeline
Stages
EE 3610: Digital Systems
EE 3610 Digital Systems Suketu Naik
2MIPS: Application
The MIPS is used in
Embedded systems,
Cisco routers
Nintendo 64
Sony PlayStation , Sony PlayStation 2
and Sony PlayStation Portable
Small computing devices
Small consumer electronics and
appliances
Google's Honeycomb (Android 3)
tablet
EE 3610 Digital Systems Suketu Naik
3Why MIPS?
The MIPS is an example of RISC (Reduced Instruction Set
Computing)
RISC uses simplified instruction set (as opposed to a
complex set which is used in CISC)
Provides higher performance architecture capable of
executing those instructions using fewer microprocessor
cycles per instruction
RISC Processors include,
DEC Alpha, AMD 29k, ARC, ARM (used in tablets, smart
phones), Atmel AVR, Blackfin, Intel i860 and i960, MIPS,
Motorola 88000, PA-RISC, PowerPC, SuperH, and SPARC (open
source)
EE 3610 Digital Systems Suketu Naik
4CISC vs. RISC
Save
Memory
Through
Microcoding
Save
Time
through
simple
instructions
EE 3610 Digital Systems Suketu Naik
5Realm of Microprocessors
Babbage: Difference and Analytical Machines
Automatic calculation based on finite differences
Wheels on shaft: data memory
Cards in deck: instructions
EE 3610 Digital Systems Suketu Naik
6Realm of Microprocessors
Harvard Architecture
Electromechanical computer: separation of data and
instructions
punched paper tape: instructions
loops: join the end of the paper tape containing the
program back to the beginning of the tape
EE 3610 Digital Systems Suketu Naik
7Realm of Microprocessors
Harvard Architecture
Physically separate signals and storage for code and data
memory
Program memory is read-only and data memory is read-
write
Impossible for program contents to be modified by the
program itself
CPUInstruction
Memory
Data
Memory
EE 3610 Digital Systems Suketu Naik
8Realm of Microprocessors
Von Neumann Architecture
Shared signals and memory for code and data
The program can be easily modified by itself since it is
stored in read-write memory
CPUInstruction
Cache
Data
Cache
RAM
EE 3610 Digital Systems Suketu Naik
9Caches
Cache is fast memory used to reduce
the time required to fetch an instruction or
data
When a piece of data or instruction is
fetched, the same data or instruction will
be accessed in the near future or data and
instructions nearby will be accessed.
Instead of the CPU spending time
accessing program or data memory for
every piece of data or instruction, it can
check cache first and then main memory
if the desired data or instruction is not
available in cache
Registers
Cache
RAM
S
T
o
R
A
G
E
S
I
Z
E
S
P
E
E
D
&
C
O
A
S
T
EE 3610 Digital Systems Suketu Naik
10Register: Set of D Flipflops
D Q
Q’
D Q
Q’
D Q
Q’
D Q
Q’CLK
D3
D2
D1
D0
Q3
Q2
Q1
Q0
EE 3610 Digital Systems Suketu Naik
11CPU DESIGN
Heart of CPUs:
Register File and ALU (Arithmetic and Logic Unit)
A
L
UA3
A1
A2
D3
D1
D2
op
1) At each clock cycle, the register will load the data
present at its inputs
2) This data is used by ALU to carry out operations
EE 3610 Digital Systems Suketu Naik
12ALU
A
L
U
op
A
B
Cin
opcode
EE 3610 Digital Systems Suketu Naik
13ALU: An Example
Functions
(selected by F):
ADD SUBTRACT
LEFT SHIFT
RIGHT SHIFT
EE 3610 Digital Systems Suketu Naik
14CPU DESIGN
Problem: Where to start?
No way to get the data into the register file initially
Solution: Add a path for 'immediate' values
A
L
UA3
A1
A2
D3
D1
D2
op
M
U
XImmediate
values1
0
Imm or offset
EE 3610 Digital Systems Suketu Naik
15R Instructions
R-Format (32-bits): ALU (core) Instructions
0 RS RT Shift F_CodeRd
Source
Registers
Destination
Register
Shift
Amount
How does CPU know what function to perform? A: Opcodehttp://alumni.cs.ucr.edu/~vladimir/cs161/mips.html
opcode=0
(indicates type
of instruction)
ADD, SUB,
AND, OR, etc
EE 3610 Digital Systems Suketu Naik
16MIPS Instruction Encoding (Data)
R-Format (32-bits)
opcode RS RT Shift Function
A
L
UA3
A1
A2
D3
D1
D2
function
M
U
X
X
(Immediate value)
1
0
O (offset)
RS
RT
Rd
Rd
EE 3610 Digital Systems Suketu Naik
17R Instructions
R-Format (32-bits)
0 RS RT Shift F_CodeRd
Function (F_Code)(same op-code, different
arithmetic operation)
add (add)
addi (add immediate)
addu (add unsigned)
addiu (add imm unsigned)
sub (subtract)
subu (subtract unsigned)
and (and)
andi (and immediate)
or (or)
ori (or immediate)
sll (shift left logical)
srl (shift right logical)
EE 3610 Digital Systems Suketu Naik
18R Instructions: Examples
EE 3610 Digital Systems Suketu Naik
19R Instructions: Examples
EE 3610 Digital Systems Suketu Naik
20I Instructions
I-Format (32-bits): Load/Store, Immediate ALU, Branch
Source
Registers
offset/immediate
op code RS RT C (sign extended)
opcode
EE 3610 Digital Systems Suketu Naik
21I Instructions
I-Format (32-bits): Load/Store, Immediate ALU, Branch
A
L
UA2
A1
D3
D1
D2
op code
M
U
X
C 1
0
O
RS
op code RS RT C (sign extended)
RT
EE 3610 Digital Systems Suketu Naik
22I: Load/Store
Load/Store Register file is limited (32 registers)
We must get data to and from memory
A
L
UA2
A1
D3
D1
D2
add
C
1
RS
RT
1
0
load
1
0
DIn Dout
Addr
Data Memory
EE 3610 Digital Systems Suketu Naik
23I Instructions: Examples
word: 32 bits
byte: 8-bits
EE 3610 Digital Systems Suketu Naik
24JUMP Instructions
J-Format (32-bits)
word: 32 bits
byte: 8-bits
Offset (26-bits)
op code Jump Address
opcode
EE 3610 Digital Systems Suketu Naik
25JUMP Instructions
J-Format (32-bits) Jump offset (target address) is specified as a word address (32-bits)
MIPS uses byte (8-bits) address: multiply the offset by 4, then concatenated
with the highest 4 bits of the program counter (PC) to get the target address
Program counter: register that contains the address of the next instruction,
is always incremented by 4 (so that 4 bytes or a word is incremented)
pc_sel
1
0DOAddrPC
+4
clk Instruction
to decode
Offset is 26 bits long
bits 25:0 (shifted by 2 =
multiply by 410: 1002 )
word: 32 bits
byte: 8-bits
EE 3610 Digital Systems Suketu Naik
26JUMP Instructions
ExampleThe 26-bit field in a jump instruction is 0x0100080. What is the
actual address the jump instruction refers to if the top four bits
of the Program Counter are 0000?
EE 3610 Digital Systems Suketu Naik
27JUMP Instructions
Special Cases Sometimes we compute jump address or need a jump address > 228
pc_sel
to pcData 1 (from reg file)
I25:0 x 4
PC + 4
pc_sel
to pcData 1
I25:0 x 4
PC + 4
A
L
U
add
PC + 4
C
EE 3610 Digital Systems Suketu Naik
28J Instructions: Examples
EE 3610 Digital Systems Suketu Naik
29A Subset of MIPS Instructions
EE 3610 Digital Systems Suketu Naik
30Instructions Encoding
EE 3610 Digital Systems Suketu Naik
31MIPS: example program
Write MIPS Assembly Language Program for the following task:
for i= 1, 100, i++ ; repeat 100 times
y(i) = x(i) + y(i) ; add each element of the arrays and store it in y
Assume that x and y start at locations 400010 and 800010
Answer:
andi $3 ,$3, 0 ;initialize loop counter $3 to 0
andi $2, $2, 0 ; clear register for loop end
addi $2, $2, 100 ; loop end
$label: lw $15, 4000($3) ;load x(i) to Register#15
lw $14, 8000($3) ;load y(i) to Register#14
add $24, $15, $14 ;x(i) + y(i)
sw $24, 8000 ($3) ;save new y(i)
addi $3, $3, 4 ;update address reg, addr=addr+4
bne $3,$2,$label ;check if the loop counter=loop end
i
100
x(i)
y(i)
x(i)+y(i)
y(i)=x(i)+y(i)
i++
EE 3610 Digital Systems Suketu Naik
32MIPS: example program Write MIPS Machine Code given the following assembly program:
andi $3,$3, 0 ;initialize loop counter $3 to 0
andi $2, $2, 0 ; clear register for loop end
addi $2, $2, 100 ; loop end
$label: lw $15, 4000($3) ;load x(i) to R15
lw $14, 8000($3) ;load y(i) to R14
add $24, $15, $14 ;x(i) + y(i)
sw $24, 8000 ($3) ;save new y(i)
addi $3, $3, 4 ;update address reg, addr=addr+4
bne $3,$2,$label ;check if the loop counter=loop end
Final
Answer
EE 3610 Digital Systems Suketu Naik
33
MIPS using VHDL
EE 3610 Digital Systems Suketu Naik
34MIPS Controller: Sequential
Fetch
Decode
Execute
Writeback
Memory
__/load_pc and
write reg_file
opcode=beq
or opcode
bne/load_pc
opcode=jr or j
/load_pc opcode≠jr /_
opcode=jw
or sw /_
opcode=sw/mem_
write and load_pc
Fetch:
PC outputs to memory
Instruction is loaded at the end of the state
Decode: Registers accessed
Execute: ALU computes the result
opcode≠sw/_
EE 3610 Digital Systems Suketu Naik
35Simplified MIPS Microprocessor in VHDLFetch Stageinst_address <= std_logic_vector(F_PC);
process (clk, reset)
begin
if reset = '1' then
F_PC <= X"00000000"; -- start executing instr at address 0
D_PC <= X"00000004"; -- normally P_PC + 4
D_IR <= X"00000000"; -- instruction register
elsif rising_edge(clk) and not D_stall then
D_IR <= X"00000000"; -- no-op instruction in case of jump/branch
D_PC <= F_PC + 4; -- pc transferred to decode stage for branch &
jump
case D_pc_select is
when pc_next => F_PC <= F_PC+4; D_IR <= unsigned(inst_in);
when pc_jump => F_PC <= D_PC(31 downto 28) & D_IR(25 downto 0)
& "00"; -JUMP by contactenating w 1st 4 bits of PC and sll by 2
when pc_branch => F_PC <= D_PC + (D_imm(29 downto 0) & "00");
when pc_jreg => F_PC <= D_T;
end case;
end if;
end process;
EE 3610 Digital Systems Suketu Naik
36Simplified MIPS Microprocessor in VHDLExecute StageE_result <= E_Op1 + E_Op2 when E_alu_op = alu_add else -- add
E_Op1 - E_Op2 when E_alu_op = alu_sub else -- subtract
E_Op1 and E_Op2 when E_alu_op = alu_and else -- and
E_Op1 or E_Op2; -- or
process (clk, reset)
begin
if reset = '1' then
M_read_mem <= false;
M_write_mem <= false;
M_write_reg <= false;
elsif rising_edge(clk) then
M_read_mem <= E_read_mem;
M_write_mem <= E_write_mem;
M_write_reg <= E_write_reg;
M_T <= E_T; -- for store instruction
M_result <= E_result;
M_Rd <= E_Rd;
end if;
end process;
EE 3610 Digital Systems Suketu Naik
37
More Simplified VHDL on the class page