EE 348: Lecture #03 EE 348: Lecture #03 Circuit Level Models Of CMOS Technology Transistors Prof. John Choma, Jr. University of Southern California Department

EE 348: Lecture #03 EE 348: Lecture #03

Circuit Level Models Of CMOS Circuit Level Models Of CMOS Technology TransistorsTechnology Transistors

Prof. John Choma, Jr.

University of Southern CaliforniaDepartment of Electrical Engineering-Electrophysics

University Park: MC: 0271Los Angeles, California 90089-0271

213-740-4692 (USC )626-915-0944 (FAX )

818-384-1552 (CELL )[email protected]

[email protected]

Spring 2003 Semester

Circuit Level Models Of CMOS Circuit Level Models Of CMOS Technology TransistorsTechnology Transistors

Prof. John Choma, Jr.

University of Southern CaliforniaDepartment of Electrical Engineering-Electrophysics

University Park: MC: 0271Los Angeles, California 90089-0271

213-740-4692 (USC )626-915-0944 (FAX )

818-384-1552 (CELL )[email protected]

[email protected]

Spring 2003 Semester

University of Southern California/Choma

EE 348, Spring 2003: Lecture #03 2

Lecture OverviewLecture OverviewLecture OverviewLecture Overview

Static MOS Model Cutoff Region Ohmic (Triode) Region Saturation Region Subthreshold Region

Short Channel Effects In Saturation Channel Length Modulation Substrate (Bulk) Phenomena Mobility Degradation Carrier Velocity Saturation

Small Signal Model In Saturation Low Frequency Equivalent Circuit High Frequency Equivalent Circuit

Example: Inverter Analysis

Static MOS Model Cutoff Region Ohmic (Triode) Region Saturation Region Subthreshold Region

Short Channel Effects In Saturation Channel Length Modulation Substrate (Bulk) Phenomena Mobility Degradation Carrier Velocity Saturation

Small Signal Model In Saturation Low Frequency Equivalent Circuit High Frequency Equivalent Circuit

Example: Inverter Analysis



N—Channel MOSFETN—Channel MOSFETN—Channel MOSFETN—Channel MOSFET

N+

Sou

rce N

+D

rainP Ty p e

S u b stra te[C o n c en tra tio n = N c m ]

A

-3

S G D

B

S ilic o n D io x id e

T o x

X d

L d L d

W

L

Gat

e

Sour

ce

Drain

B u lk orS u b stra te

M eta l o rP o lysilico n

s d g b

g b bs

s d

ds gs gd

I I I I

I 0; I 0 for V 0

I I

V V V

S

G

D

B

I d

I b

I s

I g

V d s

V b s

V g s

S

V g d

D

For Low SignalFrequencies



P—Channel MOSFETP—Channel MOSFETP—Channel MOSFETP—Channel MOSFET

P+

Sou

rce P

+D

rain

N Typ eS u b stra te

[C o n c en tra tio n = N cm ]

D

-3

S G D

B


T o x

X d

L d L d

W

L

Gat

e

Sour

ce

Drain

B u lk orS u b stra te

M eta l o rP o lysilico n

s d g b

g b sb

s d

sd sg dg

I I I I

I 0; I 0 for V 0

I I

V V V

D

G

S

B

I s

I b

I d

I g

V s d

V s b

V d g

S

V s g

D

For Low SignalFrequencies



Static Cutoff ModelStatic Cutoff ModelStatic Cutoff ModelStatic Cutoff Model

Cutoff Regime Is Vgs < Vhn For N-Channel Vhn Is Threshold Voltage, Which Is Functionally Dependent On

Bulk-Source Voltage, Vbs

Model Is Simply Id = 0 (Open Circuited Drain)

Cutoff Regime Is Vsg < Vhn For P-Channel Vhn Is Threshold Voltage, Which Is Functionally Dependent On

Source-Bulk Voltage, Vsb


Cutoff Operation Commonly Encountered In Digital Applications Rarely Encountered In Analog Configurations

Cutoff Regime Is Vgs < Vhn For N-Channel Vhn Is Threshold Voltage, Which Is Functionally Dependent On

Bulk-Source Voltage, Vbs


Cutoff Regime Is Vsg < Vhn For P-Channel Vhn Is Threshold Voltage, Which Is Functionally Dependent On

Source-Bulk Voltage, Vsb


Cutoff Operation Commonly Encountered In Digital Applications Rarely Encountered In Analog Configurations



Static Triode ModelStatic Triode ModelStatic Triode ModelStatic Triode Model

Triode Regime Is Vgs Vhn & Vds < Vgs – Vhn

Parameters Kn Is Transconductance Coefficient (Hundreds Of mhos/volt) εox Is Silicon Dioxide Dielectric Constant (345 fF/cm) μn Is Electron Mobility Of Source -To- Drain Electrons

Typically In Mid-Hundreds Of cm2/volt-secTemperature DependentInverse Temperature Dependence Of Mobility Makes MOS A Negative Temperature Coefficient Transistor. To Is Arbitrary Reference Absolute Temperature

Triode Regime Is Vgs Vhn & Vds < Vgs – Vhn

Parameters Kn Is Transconductance Coefficient (Hundreds Of mhos/volt) εox Is Silicon Dioxide Dielectric Constant (345 fF/cm) μn Is Electron Mobility Of Source -To- Drain Electrons

Typically In Mid-Hundreds Of cm2/volt-secTemperature DependentInverse Temperature Dependence Of Mobility Makes MOS A Negative Temperature Coefficient Transistor. To Is Arbitrary Reference Absolute Temperature

S

G

D

B

I d

I b

I s

I g

V d s

V b s

V g s

S

V g d

Dds

d n ds gs hn

oxn n ox ox

ox

VWI K V V V

L 2

εK μ C ; C

T

3 2

on n o

Tμ (T ) μ T

T



Triode Model For P—ChannelTriode Model For P—ChannelTriode Model For P—ChannelTriode Model For P—Channel

Triode Regime Is Vsg Vhn & Vsd < Vsg – Vhn

Parameters Kp Is Transconductance Coefficient (Hundreds Of mhos/volt) εox Is Silicon Dioxide Dielectric Constant (345 fF/cm) μp Is Electron Mobility Of Source –To- Drain Electrons

Typically In Low-Hundreds Of cm2/volt-secTemperature DependentInverse Temperature Dependence Of Mobility Makes MOS A Negative Temperature Coefficient Transistor. To Is Arbitrary Reference Absolute Temperature

Triode Regime Is Vsg Vhn & Vsd < Vsg – Vhn

Parameters Kp Is Transconductance Coefficient (Hundreds Of mhos/volt) εox Is Silicon Dioxide Dielectric Constant (345 fF/cm) μp Is Electron Mobility Of Source –To- Drain Electrons

Typically In Low-Hundreds Of cm2/volt-secTemperature DependentInverse Temperature Dependence Of Mobility Makes MOS A Negative Temperature Coefficient Transistor. To Is Arbitrary Reference Absolute Temperature

D

G

S

B

I s

I b

I d

I g

V s d

V s b

V d g

S

V s g

D

sdd p sd sg hn

oxp p ox ox

ox

VWI K V V V

L 2

εK μ C ; C

T

3 2

op p o

Tμ (T ) μ T

T



gs hn dsd dds n gs hn ds

ds ds gs hn ds

V V VI IWG K V V V

V L V V V V 2

@

Triode Regime CharacteristicsTriode Regime CharacteristicsTriode Regime CharacteristicsTriode Regime Characteristics

Triode Regime Also Known As Ohmic Regime Or Ohmic Region Often Used As Active Two Terminal Resistance Note Vds = Vgs – Vgd < Vgs – Vhn Implies Vgd > Vhn; That Is, Both The

Gate-Source AND The Gate-Drain Biases Must Exceed Threshold

Drain-Source Resistance Small Signal Conductance

For Vds << (Vgs – Vhn)

For Small Drain-Source Voltages, Transistor Behaves As A Linear Resistance In Its Ohmic Regime

Triode Regime Also Known As Ohmic Regime Or Ohmic Region Often Used As Active Two Terminal Resistance Note Vds = Vgs – Vgd < Vgs – Vhn Implies Vgd > Vhn; That Is, Both The

Gate-Source AND The Gate-Drain Biases Must Exceed Threshold

Drain-Source Resistance Small Signal Conductance

For Vds << (Vgs – Vhn)

For Small Drain-Source Voltages, Transistor Behaves As A Linear Resistance In Its Ohmic Regime

d d

ds ds

I I

V V



Saturation Regime ModelSaturation Regime ModelSaturation Regime ModelSaturation Regime Model

Saturation Requires Vgs Vhn & Vds Vgs – Vhn

ParametersDrain Saturation Voltage, Vdss

Drain Saturation Current, Idss

I-V Characteristic

Comments On Saturation Regime Saturation Regime Is The Region Where Transistors Are

Commonly Biased For Linear Signal Processing Applications Current Is Constant, Independent Of Drain-Source Voltage For All

Vds Vdss

Transistor Behaves As A Current Source At Its Drain-Source PortCurrent Is Actually Voltage Controlled Current Source

Controlled By Gate-Source Voltage, Vgs

Control Is Nominally Square Law Relationship

Saturation Requires Vgs Vhn & Vds Vgs – Vhn

ParametersDrain Saturation Voltage, Vdss

Drain Saturation Current, Idss

I-V Characteristic

Comments On Saturation Regime Saturation Regime Is The Region Where Transistors Are

Commonly Biased For Linear Signal Processing Applications Current Is Constant, Independent Of Drain-Source Voltage For All

Vds Vdss

Transistor Behaves As A Current Source At Its Drain-Source PortCurrent Is Actually Voltage Controlled Current Source

Controlled By Gate-Source Voltage, Vgs

Control Is Nominally Square Law Relationship

2nd gs hn

K WI V V

2 L

dss gs hn

2nd dss dss

V V V 0

K WI V I

2 L

@



Linearity In SaturationLinearity In SaturationLinearity In SaturationLinearity In Saturation

Differential Amplifier

Differential Response

Differential Amplifier

Differential Response

DMgs1 CM

DMgs2 CM

VV V

2V

V V2

o D1 D2V R I I

2 2n n

D1 D2 gs1 hn gs2 hn

ngs1 gs2 hn gs1 gs2

n CM hn DM o n CM hn DM

K KW WI I V V V V

2 L 2 LK W

V V 2V V V2 L

W WK V V V V K R V V V

L L

V /2D M

V /2D M

V C M

R R

V o

V D D

ID 1 I D 2

M 1 M 2



Comments: Differential AmplifierComments: Differential AmplifierComments: Differential AmplifierComments: Differential Amplifier

Fundamental Results Output Voltage

Gain

Linearity Output Voltage Is Proportional To Differential Input Voltage Gain Is Independent Of Differential Input Voltage Gain Is Controllable By Common Mode Input Voltage Note That No Small Signal Modeling Approximation Is Invoked

Fundamental Results Output Voltage

Gain

Linearity Output Voltage Is Proportional To Differential Input Voltage Gain Is Independent Of Differential Input Voltage Gain Is Controllable By Common Mode Input Voltage Note That No Small Signal Modeling Approximation Is Invoked

V /2D M

V /2D M

V C M

R R

V o

V D D

ID 1 I D 2

M 1 M 2

o n CM hn DMW

V K R V V VL

on CM hn

DM

V WK R V V

V L



Subthreshold Regime ModelSubthreshold Regime ModelSubthreshold Regime ModelSubthreshold Regime Model

Subthreshold Requires 0 < Vgs < Vhn – 2nVT & Vds 2nVT

VT = kT/q = 26 mV @ 27 °C Factor n Is Empirical And Satisfies 1.1 < n < 2.0

Drain Current:

Comments Gate-Source Voltage Is Barely Above Threshold Level, While

Drain-Source Voltage Is Restricted To Nominally Less Than 100 mV

Operation In Subthreshold Is Useful Only For Low Frequency, Low Power Analog Signal Processing Applications

Static Volt-Ampere Characteristic Emulates That Of Bipolar Transistor Action

Subthreshold Requires 0 < Vgs < Vhn – 2nVT & Vds 2nVT

VT = kT/q = 26 mV @ 27 °C Factor n Is Empirical And Satisfies 1.1 < n < 2.0

Drain Current:

Comments Gate-Source Voltage Is Barely Above Threshold Level, While

Drain-Source Voltage Is Restricted To Nominally Less Than 100 mV

Operation In Subthreshold Is Useful Only For Low Frequency, Low Power Analog Signal Processing Applications

Static Volt-Ampere Characteristic Emulates That Of Bipolar Transistor Action

gs hn TV V nV2n

d T2

2K WI nV

Le

e



Review: Simple MOSFET ModelReview: Simple MOSFET ModelReview: Simple MOSFET ModelReview: Simple MOSFET Model

Low Signal Frequencies

Comments Above Relationships Written For N-Channel; Analogous Expressions

For P-Channel Known As “Schichman-Hodges” Model Or “Long Channel Model

Approximation” Valid Only For Low Signal Frequencies

Low Signal Frequencies

Comments Above Relationships Written For N-Channel; Analogous Expressions

For P-Channel Known As “Schichman-Hodges” Model Or “Long Channel Model

Approximation” Valid Only For Low Signal Frequencies

gs hn

d n ds gs hn ds gs hn ds gs hn

2n

gs hn gs hn ds gs hn

0 for V V

WI K V V V V 2 for V V & V V V

LK W

V V for V V & V V V2 L

S

G

D

B

I d

I b

I s

I g

V d s

V b s

V g s

S

V g d

D



Sample MOSFET Static CurvesSample MOSFET Static CurvesSample MOSFET Static CurvesSample MOSFET Static Curves

0

150

300

450

600

750

900

0.0 1.0 2.0 3.0 4.0 5.0

Drain-Source Voltage, Vds (volts)

Dra

in C

urre

nt, I

d (

a)

Vgs = 2 volts

3 volts

4 volts

5 voltsOhmic

Regime

Saturation

Regime

DrainSaturationCurrent

Kn(W/L) = 100 mmho/voltVhn = 900 mvolt

Nom

inal

lyLi

near

Res

ista

nce



MOSFET In CutoffMOSFET In CutoffMOSFET In CutoffMOSFET In Cutoff

Voltages Vds 0 Vbs 0

Gate-Source Vgs = Vox + Vy

Vox Is VoltageAcross Oxide

Vy Is VoltageBetween Oxide-SemiconductorInterface AndSource

Ionic ChargesIn ChannelAre Immobile

Voltages Vds 0 Vbs 0

Gate-Source Vgs = Vox + Vy

Vox Is VoltageAcross Oxide

Vy Is VoltageBetween Oxide-SemiconductorInterface AndSource

Ionic ChargesIn ChannelAre Immobile

N+

Sou

rce N

+D

rain

P -Type S u bstra te

S G D

B


V g s

V d s

V b s

D ep le tio nL a yer, V > 0d s

D ep le tio nL a yer, V = 0d s

I d



Comments: Cutoff RegimeComments: Cutoff RegimeComments: Cutoff RegimeComments: Cutoff Regime

Channel Depleted Of Free Carriers No Current Conduction Path

Between Source And Drain Only Current Is Leakage

Holes From Drain & SourceElectrons From Bulk

Depletion Regions At Source-Bulk And At

Drain-Bulk Because Vbs 0 Wider In Drain Region

Because Vds > 0

Channel Depleted Of Free Carriers No Current Conduction Path

Between Source And Drain Only Current Is Leakage

Holes From Drain & SourceElectrons From Bulk

Depletion Regions At Source-Bulk And At

Drain-Bulk Because Vbs 0 Wider In Drain Region

Because Vds > 0 N

+So

urc

e N+

Drain

P -Type S u bstra te

S G D

B


V g s

V d s

V b s



I d



Channel Inversion In Ohmic RegimeChannel Inversion In Ohmic RegimeChannel Inversion In Ohmic RegimeChannel Inversion In Ohmic Regime

Gate Voltage

Inversion Weak: n = Ni @

V = VF

Strong: n = NA @Vy = 2VF

VF: Fermi Potential

Gate Voltage

Inversion Weak: n = Ni @

V = VF

Strong: n = NA @Vy = 2VF

VF: Fermi Potential

gs ox y

Ay T T 2

o i

V V V

nNnV V V

n Nln ln

Ni Is Intrinsic Carrier Concentration Of Silicon (about 1010 atoms/cm3 at 27 °C)

n Is Concentration Of Free Electrons In Channel

N+

Sour

ce N+

Drain

P -Type S u bstra te (con c . = N cm )A

-3

S G D

B


V > Vg s h n

V = 0d s


I d

C h a n n el O fF ree E lec tro n s

V 0b s

Ay F T

i

hn ox F

NV V V

N

V V 2V

ln

@



Channel Inversion: Ohmic, VChannel Inversion: Ohmic, Vdsds > 0 > 0Channel Inversion: Ohmic, VChannel Inversion: Ohmic, Vdsds > 0 > 0

Channel Narrows At Drain Vgd = Vgs – Vds

Decreases Resistance Becomes

Dependent On Vds

Resistance IsResultantly Nonlinear

Current Electrons Transported

From Source –To-Drain Principally InChannel Via Conventional Diffusion Mechanisms

But Some Electrons Are Transported By Drift Through Depletion Region Between Drain Site And Electron Channel “Wedge”

Channel Narrows At Drain Vgd = Vgs – Vds

Decreases Resistance Becomes

Dependent On Vds

Resistance IsResultantly Nonlinear

Current Electrons Transported

From Source –To-Drain Principally InChannel Via Conventional Diffusion Mechanisms

But Some Electrons Are Transported By Drift Through Depletion Region Between Drain Site And Electron Channel “Wedge”

N+

Sour

ce N+

Drain


-3

S G D

B


V > Vg s h n

0 < V < V - Vd s g s h n

V 0b s


I d

C h an n e l O fF ree E lec tron s



N+

Sour

ce N+

Drain


-3

S G D

B


V > Vg s h n

V = 0d s


I d

C h a n n el O fF ree E lec tro n s

V 0b s

Comments: Ohmic RegimeComments: Ohmic RegimeComments: Ohmic RegimeComments: Ohmic Regime

Uniform Channel Resistance Behaves As Implanted Resistor Contacts Are Source & Drain Conductance

Uniform Channel Resistance Behaves As Implanted Resistor Contacts Are Source & Drain Conductance

N+

Sour

ce N+

Drain


-3

S G D

B


V > Vg s h n

0 < V < V - Vd s g s h n

V 0b s


I d


ds n gs hnW

G K V VL

With Drain-Source Bias Behaves As Tapered Resistor Contacts Are Source & Drain Conductance

ds n gs hn dsW

G K V V VL



Channel Inversion: PinchoffChannel Inversion: PinchoffChannel Inversion: PinchoffChannel Inversion: Pinchoff

At Pinchoff Vgd = Vhn

Vds = Vgs – Vhn = Vdss

Gate-Drain VoltageBarely SupportsStrong Inversion

Channel ThicknessNarrows To ZeroAt Drain Site

Resistance Dynamic

Conductance(Slope Of Id vs. Vds

Curve) Is Zero Electron Transport Mechanism From Source -To- Drain Now Shifts

From Diffusion To Drift

At Pinchoff Vgd = Vhn

Vds = Vgs – Vhn = Vdss

Gate-Drain VoltageBarely SupportsStrong Inversion

Channel ThicknessNarrows To ZeroAt Drain Site

Resistance Dynamic

Conductance(Slope Of Id vs. Vds

Curve) Is Zero Electron Transport Mechanism From Source -To- Drain Now Shifts

From Diffusion To Drift

N+

Sour

ce N+

Drain


-3

S G D

B


V > Vg s h n

0 < V = V - Vd s g s h n

V 0b s


I d




Channel In Saturation RegimeChannel In Saturation RegimeChannel In Saturation RegimeChannel In Saturation Regime

Channel Channel

Thickness ReducesTo Zero WhenVoltage AcrossChannel Is Vdss

For Vds > Vdss Vdss Must BeDropped WithRespect To SourceWithin Channel

Voltage (Vds – Vdss)Dropped AcrossDepletion ZoneBetween Channel And Drain

Phenomenon Is Channel Length Modulation

Channel Channel

Thickness ReducesTo Zero WhenVoltage AcrossChannel Is Vdss

For Vds > Vdss Vdss Must BeDropped WithRespect To SourceWithin Channel

Voltage (Vds – Vdss)Dropped AcrossDepletion ZoneBetween Channel And Drain

Phenomenon Is Channel Length Modulation

N+

Sour

ce N+

Drain


-3

S G D

B


V > Vg s h n

0 < V > V - Vd s g s h n

V 0b s


I d


L

L

In te rfa ceP o ten tia l

H ere Is V d s s



Channel Length ModulationChannel Length ModulationChannel Length ModulationChannel Length Modulation

Modified I/V Characteristic In Saturation

Idss Is Current Flowing When Channel Is Of Length L Modified Current Is Effectively Idss Corrected For A Channel Length Of

(L – L)

Channel Length Modulation Voltage

Substrate-Drain/Source Junction Potential:

Intrinsic Carrier Concentration:(Ni In cm-3 When T In °K)

Modified I/V Characteristic In Saturation

Idss Is Current Flowing When Channel Is Of Length L Modified Current Is Effectively Idss Corrected For A Channel Length Of

(L – L)

Channel Length Modulation Voltage

Substrate-Drain/Source Junction Potential:

Intrinsic Carrier Concentration:(Ni In cm-3 When T In °K)

V Vds dss

2n ds dss

dss gs hnd

K V VL WI I V V 1

L L 2 L V

Ads dss j

s

2qNV L V V V

D Aj T 2

i

N NV V

Nln

T 300.2 11 10i

N 2 10



Channel Length ParametersChannel Length ParametersChannel Length ParametersChannel Length Parameters

Channel Length Modulation Voltage Ideally, Vλ Infinitely Large V Implies MOSFET Behaves As An Ideal Current

Source (Independent Of Vds) Controlled By Vgs

Progressively Shorter Channels Diminish Vλ Large Substrate Doping Concentration Encourages Large Vλ

Intrinsic Carrier Concentration Empirical Relationship Nominally Valid Only For Silicon Ni = 1010 cm-3 At Temperature T = 27 °C = 300.2 °K Ni Nominally Doubles For Each 11 °C Rise In Silicon

Temperature

Miscellaneous Parameters s Is Silicon Dielectric Constant (1.05 pF/cm) q Is Magnitude Of Electron Charge (1.6 x 10-19 Coulomb)

Channel Length Modulation Voltage Ideally, Vλ Infinitely Large V Implies MOSFET Behaves As An Ideal Current

Source (Independent Of Vds) Controlled By Vgs

Progressively Shorter Channels Diminish Vλ Large Substrate Doping Concentration Encourages Large Vλ

Intrinsic Carrier Concentration Empirical Relationship Nominally Valid Only For Silicon Ni = 1010 cm-3 At Temperature T = 27 °C = 300.2 °K Ni Nominally Doubles For Each 11 °C Rise In Silicon

Temperature

Miscellaneous Parameters s Is Silicon Dielectric Constant (1.05 pF/cm) q Is Magnitude Of Electron Charge (1.6 x 10-19 Coulomb)



Threshold Voltage ModulationThreshold Voltage ModulationThreshold Voltage ModulationThreshold Voltage Modulation

Modified Saturation Region Drain Current

Bulk Voltage-Dependent Threshold Voltage

Threshold Voltage Increases With Substrate-Source Reverse Bias Ideally, Threshold Voltage Is Constant, Independent Of Vbs

Constant Threshold Voltage Requires Thin Oxide And/Or Low Substrate Dopant Level

Modified Saturation Region Drain Current

Bulk Voltage-Dependent Threshold Voltage

Threshold Voltage Increases With Substrate-Source Reverse Bias Ideally, Threshold Voltage Is Constant, Independent Of Vbs

Constant Threshold Voltage Requires Thin Oxide And/Or Low Substrate Dopant Level

AF T

i

NV V

Nln

2n ds dssd gs hnc

λ

K V VWI V V 1

2 L V

bs

hnc hn θ F TF T

VV V 2 V V V 1 1

2 V V

2

A s oxθ A s2

oxox

qN ε TV qN ε

εC



Threshold Voltage CharacteristicThreshold Voltage CharacteristicThreshold Voltage CharacteristicThreshold Voltage CharacteristicN

A =

5 x

10

14

cm-3;

T =

27

°C

0

150

300

450

600

750

900

0-1-2-3-4-5-6

Bulk-Source Voltage, Vbs (volts)

Th

resh

old

Volt

age

Ch

an

ge

(mV

)

Oxide Thickness = 1200 AngOxide Thickness = 1200 Ang

600 Ang

100 Ang



Mobility DegradationMobility DegradationMobility DegradationMobility Degradation

Electric Field Problems Short Channels And/Or Thin Oxides Conduce Large Lateral And

Vertical Channel Fields For Even Moderate Drain-Source Voltages Large Fields Impart Increasing Energy To Free Channel Charges,

Thereby Causing More Carrier Collisions And A Mobility That Degrades From A Value Of μn –to- A Value, Say μne

At Low Fields, Carrier Velocity Is Proportional To Lateral FieldsAt Large Lateral Fields, The Carrier Velocity, v, Saturates To A Value, vsat,

Which In Silicon Is Around 0.1 m/pSecSaturation Occurs When Lateral Field, Eh, Exceeds A Critical Value, Ec,

Which In Silicon Is About 5 volts/ m

Mobility And Field

Electric Field Problems Short Channels And/Or Thin Oxides Conduce Large Lateral And

Vertical Channel Fields For Even Moderate Drain-Source Voltages Large Fields Impart Increasing Energy To Free Channel Charges,

Thereby Causing More Carrier Collisions And A Mobility That Degrades From A Value Of μn –to- A Value, Say μne

At Low Fields, Carrier Velocity Is Proportional To Lateral FieldsAt Large Lateral Fields, The Carrier Velocity, v, Saturates To A Value, vsat,

Which In Silicon Is Around 0.1 m/pSecSaturation Occurs When Lateral Field, Eh, Exceeds A Critical Value, Ec,

Which In Silicon Is About 5 volts/ m

Mobility And Field

gs hncdssh

V VVE

L L

n sat

neh ch c

μ vμ

E E1 E E

sat h cn hne h

h c h c

v E Eμ Ev μ E

1 E E 1 E E



Carrier Velocity And MobilityCarrier Velocity And MobilityCarrier Velocity And MobilityCarrier Velocity And Mobility

0.0

0.2

0.4

0.6

0.8

1.0

0 1 2 3 4 5 6 7 8 9 10

Normalized Electric Field

Nor

mal

ized

Car

rier

Veloc

ity

0.0

0.2

0.4

0.6

0.8

1.0

Nor

mal

ized

Car

rier

Mob

ility

Carrier Mobility

Carrier Velocity



Alternative Mobility RelationshipsAlternative Mobility RelationshipsAlternative Mobility RelationshipsAlternative Mobility Relationships

Critical Voltage Parameter

Comments Crude Approximation For Lateral Field, Eh

Channel Length In Field Expression Should Be (L – L), But Channel Modulation Is Accounted For By Channel Modulation Voltage, V

Critical Voltage For L = 0.25 μm Is Vc = 1.25 volts

TransconductanceDensity:

Critical Voltage Parameter

Comments Crude Approximation For Lateral Field, Eh

Channel Length In Field Expression Should Be (L – L), But Channel Modulation Is Accounted For By Channel Modulation Voltage, V

Critical Voltage For L = 0.25 μm Is Vc = 1.25 volts

TransconductanceDensity:

gs hncdssh

V VVE

L L

c cV LE@

nne

h c

μμ

1 E E

n n n

negs hnc gs hnch c

c c

μ μ μμ

V V V V1 E E1 1

LE V

n ox nne ne ox

gs hnc gs hnc

c c

μ C KK μ C

V V V V1 1

V V



Volt-Ampere Impact Of MobilityVolt-Ampere Impact Of MobilityVolt-Ampere Impact Of MobilityVolt-Ampere Impact Of Mobility

Static DrainCurrent InSaturation

High Fields Vgs - Vhnc >> Vc

Vc = LEc

vsat = μnEc

Comments Drain Current Now Scales With W, As Opposed To (W/L) Drain Current Almost Linear W/R To Gate-Source Voltage

Static DrainCurrent InSaturation

High Fields Vgs - Vhnc >> Vc

Vc = LEc

vsat = μnEc

Comments Drain Current Now Scales With W, As Opposed To (W/L) Drain Current Almost Linear W/R To Gate-Source Voltage

2ne ds dss

d gs hnc

ds dss

2n

d gs hncgs hnc

c

K V VWI V V 1

2 L V

V V1

K VWI V V

V V2 L1

V

ox sat ds dssd gs hnc

WC v V VI V V 1

2 V



Comments: Velocity SaturationComments: Velocity SaturationComments: Velocity SaturationComments: Velocity Saturation

Most Of The Channel Is Depleted Common For Deep Submicron Geometries (L < 0.2 m) Free Electrons Concentrated Near Source

Characteristics

Drain Current Nominally Linear With Gate-Source Voltage Limited Overdrive (Vds – Vdss) Capability Effective Transconductance Is Low (Generally Of Order Of Low

Tens of Millimhos ForRoutine Geometries)

Most Of The Channel Is Depleted Common For Deep Submicron Geometries (L < 0.2 m) Free Electrons Concentrated Near Source

Characteristics

Drain Current Nominally Linear With Gate-Source Voltage Limited Overdrive (Vds – Vdss) Capability Effective Transconductance Is Low (Generally Of Order Of Low

Tens of Millimhos ForRoutine Geometries)

ox sat ds dss ox satd gs hnc gs hnc

ox satd gs hnc M gs hnc

WC v V V WC vI V V 1 V V

2 V 2

WC vI V V G V V

2

ox satM

ox

WC v WG 3.45 S

2 2T



MOS Large Signal ModelMOS Large Signal ModelMOS Large Signal ModelMOS Large Signal Model

Cgd Gate-Drain Capacitance

Cgs Gate-Source Capacitance

Cdb Drain-Bulk Capacitance

Csb Source-Bulk Capacitance

Cold Drain Overlap Capacitance

Cols Source Overlap Capacitance

rg Gate-Source Resistance

rdd Drain Ohmic Resistance

rss Source Ohmic Resistance

rbb Bulk Ohmic Resistance

rdb Bulk/Drain Ohmic Resistance

rsb Bulk/Source Ohmic Resistance

DBD Bulk-Drain DiodeDBS Bulk-Source Diode

Cgd Gate-Drain Capacitance

Cgs Gate-Source Capacitance

Cdb Drain-Bulk Capacitance

Csb Source-Bulk Capacitance

Cold Drain Overlap Capacitance

Cols Source Overlap Capacitance

rg Gate-Source Resistance

rdd Drain Ohmic Resistance

rss Source Ohmic Resistance

rbb Bulk Ohmic Resistance

rdb Bulk/Drain Ohmic Resistance

rsb Bulk/Source Ohmic Resistance

DBD Bulk-Drain DiodeDBS Bulk-Source Diode

I d

C s b

G

r s sC g s

C o ls

S

B

r s b

r d d

id

C g d

D

C o ld

r d bD B D

r b b

C d b

D B S

r g



MOS Capacitances In SaturationMOS Capacitances In SaturationMOS Capacitances In SaturationMOS Capacitances In Saturation

Ad Drain-Bulk Junction Area

As Drain-Source Junction Area

Cjo Zero Bias Density Of Junction Depletion Capacitance

Ad Drain-Bulk Junction Area

As Drain-Source Junction Area

Cjo Zero Bias Density Of Junction Depletion Capacitance

gd old old d oxC C C WL C

dgs ols ox

L2C C WLC

3 L

d jo

db

bd j

A CC

1 V V

s josb

bs j

A WL CC

1 V V

Cdb, Csb High Tens of fF

Cgs Tens of fF

Cgd, Cold, Cols Few fF(Representative Submicron Device)

Cdb, Csb High Tens of fF

Cgs Tens of fF

Cgd, Cold, Cols Few fF(Representative Submicron Device)

I d

C s b

G

r s sC g s

C o ls

S

B

r s b

r d d

id

C g d

D

C o ld

r d bD B D

r b b

C d b

D B S

r g



Comments On ModelComments On ModelComments On ModelComments On Model

Overlap Capacitances Generally Negligible In Self-Aligning Processes Possible Exception Is Cgd For Deep Submicron

Proportional To Device Depth, WW Necessarily Large For Reasonable Transconductance

Diodes Are Routinely Non-Conductive

Resistances rdd, rss, rbb, rsb, rdb Normally Have Negligible Electrical Effects rg Is Gate-Source Resistance

Allows Accurate Modeling Of Transconductance Phase ResponseNegligible Effect For Frequencies Well Below Unity Gain FrequencySemi-Empirical Expression

Overlap Capacitances Generally Negligible In Self-Aligning Processes Possible Exception Is Cgd For Deep Submicron

Proportional To Device Depth, WW Necessarily Large For Reasonable Transconductance

Diodes Are Routinely Non-Conductive

Resistances rdd, rss, rbb, rsb, rdb Normally Have Negligible Electrical Effects rg Is Gate-Source Resistance

Allows Accurate Modeling Of Transconductance Phase ResponseNegligible Effect For Frequencies Well Below Unity Gain FrequencySemi-Empirical Expression

do

g 2

gs

5Gr

C

dsdo n gs hn ds V 0

WG K V V G

L



First Order Small Signal ModelFirst Order Small Signal ModelFirst Order Small Signal ModelFirst Order Small Signal Model

Transconductances

Channel Resistance

Transconductances

Channel Resistance

Csb

G

r ssC

gs

Col

s

S

r sb

r dd

i d

Cgd

D

Col

d

r dbC

db

gv

mf

gag

vm

bba

v ga

v ba

r bb

B

r o

dsQ dssQo

dQ

V V Vr

I

d dQ

d dQ

dmf n dQ

Q pointgsI I

dmb b mf

Q pointbs I I

bF T bsQ

Ig 2K W L I

V

Ig g

V

V 2

2 V V V

@

@



Comments: First Order ModelComments: First Order ModelComments: First Order ModelComments: First Order Model

Model Is For “Long Channels” Where Square Law I-V Characteristic Is Valid

All Ohmic Resistances Are Generally Ignored

Gate Resistance IgnoredBecause Of PresumptionOf Signal FrequenciesMuch Smaller Than UnityGain Device Frequency

Model Is For “Long Channels” Where Square Law I-V Characteristic Is Valid

All Ohmic Resistances Are Generally Ignored

Gate Resistance IgnoredBecause Of PresumptionOf Signal FrequenciesMuch Smaller Than UnityGain Device Frequency

mf n dQ

mb b mf

bF T bsQ

g 2K W L I

g g

V 2

2 V V V

dsQ dssQo

dQ

V V Vr

I

C s b

G

C g s

C o ls

S

i d

C g d

D

C o ld

C d b

g vm f g a g vm b b a

v g a

v b a

B

r o



Short Channel Small Signal EffectsShort Channel Small Signal EffectsShort Channel Small Signal EffectsShort Channel Small Signal Effects

Static (Low Frequency) Drain Current

Intermediate Parameters:

Resistance:

Transconductances:

Static (Low Frequency) Drain Current

Intermediate Parameters:

Resistance:

Transconductances:

mbs b mfsg g

ds dss

2n

d gs hnc dssgs hnc c

c

V V1

K V 1 fWI V V I

V V2 L 1 f1

V

ds dss

c gs hnc c

f V V V

f V V V

ds dss

od

V V Vr

I

mf n dss

bF T bs

2n

dss gs hnc

dss gs hnc

g 2K W L I

V 2

2 V V V

K WI V V

2 LV V V

dss cmfs mf

c c

1 f V 2V f 2g g 1

1 f 1 f 1 f



Hypothetical TransistorHypothetical TransistorHypothetical TransistorHypothetical Transistor

Physical Parameters

NA = 5.5(10)14 cm-3

ND = 5(10)21 cm-3

Ni(To) = (10)10 cm-3

s = 1.05 pF/cm

ox = 345 fF/cm

n = 420 cm2/volt-sec

Ec = 5 volts/m

Comments Internal Temperature, T, Is

Always Larger Than Ambient Reference Temperature, To

Compare Long And Short Channel Characteristics

Physical Parameters

NA = 5.5(10)14 cm-3

ND = 5(10)21 cm-3

Ni(To) = (10)10 cm-3

s = 1.05 pF/cm

ox = 345 fF/cm

n = 420 cm2/volt-sec

Ec = 5 volts/m

Comments Internal Temperature, T, Is

Always Larger Than Ambient Reference Temperature, To

Compare Long And Short Channel Characteristics

Device Parameters

Tox = 18 Å (Angstroms)

L = 0.18 mVhn = 650 mV

T = 50 °C = 323.2 °KTo = 27 °C = 273.2 °K

W = 1.8 m

Circuit Operation

Vds = 1.8 volts

Vgs = 0.95 volts

Vbs = -1 volts

Saturation Region Bias Bulk Is Back Biased

Device Parameters

Tox = 18 Å (Angstroms)

L = 0.18 mVhn = 650 mV

T = 50 °C = 323.2 °KTo = 27 °C = 273.2 °K

W = 1.8 m

Circuit Operation

Vds = 1.8 volts

Vgs = 0.95 volts

Vbs = -1 volts

Saturation Region Bias Bulk Is Back Biased



Transistor CharacteristicsTransistor CharacteristicsTransistor CharacteristicsTransistor Characteristics

Peripheral Calculations VF = 263.8 mV (Fermi Potential) Vj = 974.3 mV (Substrate-Drain/Source Junction Potential) V = 25.15 V (Threshold Body Effect Voltage) V = 366.8 mV (Channel Length Modulation Voltage) Vc = 900 mV (Mobility Degradation Voltage) Vdss = 296.3 mV (Drain Saturation Voltage) Vhnc = 653.7 mV (Compensated Threshold Voltage) Kn = 721 mho/V (Transconductance Parameter) Cox = 1.92 F/cm2 (Oxide Capacitance Density)

Device Performance Idss = 316.25 A (Long Channel Static Drain Current) IdQ = 1.213 mA (Actual Static Drain Current) gmf = 2.135 mmho (Long Channel Forward Transconductance) gmfs = 6.527 mmho (Actual Forward Transconductance) b = 0.00292 (Bulk Transconductivity Factor) gmb = 19.079 mho (Substrate/Bulk Transconductance) ro = 1.54 K (Drain-Source Channel Resistance)

Peripheral Calculations VF = 263.8 mV (Fermi Potential) Vj = 974.3 mV (Substrate-Drain/Source Junction Potential) V = 25.15 V (Threshold Body Effect Voltage) V = 366.8 mV (Channel Length Modulation Voltage) Vc = 900 mV (Mobility Degradation Voltage) Vdss = 296.3 mV (Drain Saturation Voltage) Vhnc = 653.7 mV (Compensated Threshold Voltage) Kn = 721 mho/V (Transconductance Parameter) Cox = 1.92 F/cm2 (Oxide Capacitance Density)

Device Performance Idss = 316.25 A (Long Channel Static Drain Current) IdQ = 1.213 mA (Actual Static Drain Current) gmf = 2.135 mmho (Long Channel Forward Transconductance) gmfs = 6.527 mmho (Actual Forward Transconductance) b = 0.00292 (Bulk Transconductivity Factor) gmb = 19.079 mho (Substrate/Bulk Transconductance) ro = 1.54 K (Drain-Source Channel Resistance)



Device Unity Gain FrequencyDevice Unity Gain FrequencyDevice Unity Gain FrequencyDevice Unity Gain Frequency

Short CircuitCurrent Gain:

Unity GainFrequency:

Comments T << gmf /(Cgd+Cold) Shichman-Hodges

Model For gmf

Short CircuitCurrent Gain:

Unity GainFrequency:

Comments T << gmf /(Cgd+Cold) Shichman-Hodges

Model For gmf

I b ia s C b ig

io u ti in

V d d

g vm f 1 g vm b 2 r o

C + Cg s o l s

C + Cg d o ld

i in v 1

S

D

G

B v 2

io u t

mf gd oldout

in gs ols gd old

g s C Ci

i s C C C C

n gs hncmfT

2 dgs ols gd old

3 V Vg

3LC C C C2L 1

L



satTs

d

3vf

3L8 L 1

L

High Frequency ObservationsHigh Frequency ObservationsHigh Frequency ObservationsHigh Frequency Observations

Long Channel Approximation: Inversely Proportional To Nominally The

Square Of Channel Length Degradation Incurred By Gate Overlaps Decreases With Temperature Because Of Mobility Dependence

Short Channel Approximation: Assume Small Overdrive And Large fc

Total Capacitance, CT, Is Net (Cgd + Cgs) Unity Gain Frequency Is gmfs/CT

Note Nominal Inverse Proportion To L,Not L2

Actual Unity Gain Frequency Smaller Of Long And Short Channel Results For Preceding Example With Ld /L = 0.1

fTl = 63.13 GHz

fTs = 51.01 GHz

Long Channel Approximation: Inversely Proportional To Nominally The

Square Of Channel Length Degradation Incurred By Gate Overlaps Decreases With Temperature Because Of Mobility Dependence

Short Channel Approximation: Assume Small Overdrive And Large fc

Total Capacitance, CT, Is Net (Cgd + Cgs) Unity Gain Frequency Is gmfs/CT

Note Nominal Inverse Proportion To L,Not L2

Actual Unity Gain Frequency Smaller Of Long And Short Channel Results For Preceding Example With Ld /L = 0.1

fTl = 63.13 GHz

fTs = 51.01 GHz

n dssTl

2 d

3 Vf

3L4 L 1

L

dT

3L2C WLCox 1

3 L

mf ox satmfs

c

g WC vg

f 2

T Tl Tsf f , fmin

fT = 51 GHz



Small Signal ModelsSmall Signal ModelsSmall Signal ModelsSmall Signal Models

Traditional Model Assumes Saturation Regime Cgs And Cgd Include Overlap

Alternate Model Current Control

Assumes Saturation Gate Capacitances

Include Overlap Effects Useful When Source

Degeneration Is Used

Traditional Model Assumes Saturation Regime Cgs And Cgd Include Overlap

Alternate Model Current Control

Assumes Saturation Gate Capacitances

Include Overlap Effects Useful When Source

Degeneration Is Used

C s b

G

C g s

S

i d

i g a

C g d

D

C d b

g vm f g a g vm b b a

v g a

B

r o

v b a

C s b

G

C g s

S

i d

i g a

C g d

D

C d b

g vm b b a

v g a

B

r o

v b a

T gks( ) i g a

ga T g gdmf ga mf ga g

gs gs

i k Cg v g i ; k 1

sC s C

@



Common Source InverterCommon Source InverterCommon Source InverterCommon Source Inverter

PROBLEM:Determine The Low Frequency, Small-Signal Voltage Gain, Av(0) = Vos/Vs, And, Assuming CL Is The Dominant Circuit Capacitance, Find The 3-dB Bandwidth And The Unity Gain Frequency Of The Amplifier.

PROBLEM:Determine The Low Frequency, Small-Signal Voltage Gain, Av(0) = Vos/Vs, And, Assuming CL Is The Dominant Circuit Capacitance, Find The 3-dB Bandwidth And The Unity Gain Frequency Of The Amplifier.

V g g

M D

M L

V o

C L

+ V d d

V s

R s

E ffec tiveL o a d

S ch em a tic D ia g ra m

M D

V o s

C L

V s

R s

E ffec tive L o a dR esista n ce

A C S ch em a tic D ia g ra m

R L e f f



Effective Load ResistanceEffective Load ResistanceEffective Load ResistanceEffective Load Resistance

Model Parameters Account For Short Channels

Analysis With All InternalOhmic ResistancesIgnored:

Resistance Is Roughly Inverse Forward Transconductance

Model Parameters Account For Short Channels

Analysis With All InternalOhmic ResistancesIgnored:

Resistance Is Roughly Inverse Forward Transconductance

1 2 x

x ol x ml 1 bl ml 2

v v V

V r I g v g v

x ol

Leffx bl ml ol bl ml

V r 1R

I 1 1 g r 1 g

@

M L E ffec tiveL o a d

I x I x

V

x

V

x

g vm l 1 b l m l 2g v r o l

v 1 v 2



Low Frequency Voltage GainLow Frequency Voltage GainLow Frequency Voltage GainLow Frequency Voltage Gain

Gain

Long Channel Approximation

Gain

Long Channel Approximation

M D

V o s

V o s

C L

V s

V s

R s

R s

E ffec tive L o a dR esis ta n ce

R L e f f

g vm d 1 b d m d 2g v r o d

v 1

v 2

R L e f f

1 s

2

NOTE:

v V

v 0

os md

v md od Leff md Leffs bl ml

V gA (0 ) g r R g R

V 1 g

os md D D

vs L Lbl ml bl

V g W L1A (0 )

V W L1 g 1



High Frequency ConsiderationsHigh Frequency ConsiderationsHigh Frequency ConsiderationsHigh Frequency Considerations

Substantial Capacitive Loading At Output Port Due To Substrate

Negligible Cf In Self-Aligning Gate Technology

Substantial Capacitive Loading At Output Port Due To Substrate

Negligible Cf In Self-Aligning Gate Technology

V g g

M D

M L

V o

C L

C i

+ V d d

V s

R s

C g sd C sb d

C d bdC g dd

C g sl C sb l

C d blC g dl

V o s

V s

R s

g vm d 1 r o d

v 1

R L ef fC f C o

Model Ignores Bulk TransconductanceBecause Source And Bulk Of Driver

Are Shorted To Ground

All Gate-Source AndGate-Drain CapacitancesInclude Overlap Effects

Gate-Drain And Drain-Bulk LoadCapacitances And Source-Bulk DriverCapacitances Are AC Short Circuited

i gsd f gdd

o L dbd gsl sbl

C C C C

C C C C C



High Frequency Gain & BandwidthHigh Frequency Gain & BandwidthHigh Frequency Gain & BandwidthHigh Frequency Gain & Bandwidth

Dominant Pole Likely p1

Rs Is Typically Small (50 Ohms Or Less) In High Frequency CircuitsLarge Capacitive Loading At Output Port

Bandwidth, B, (In Radians/Sec) Is Resultantly Roughly p1

Gain-Bandwidth Product:

Dominant Pole Likely p1

Rs Is Typically Small (50 Ohms Or Less) In High Frequency CircuitsLarge Capacitive Loading At Output Port

Bandwidth, B, (In Radians/Sec) Is Resultantly Roughly p1

Gain-Bandwidth Product:

C i

V o s

V s

R s

g vm d 1 r o d

v 1

R L e f fC f C o

vv

1 2

A (0 )A ( s )

s s1 1

p p

1 od Leff o

2 s i

p 1 r R C

p 1 R C

v md od LeffA (0 ) g r R

1 2 1B p , for p p

v md oGBP A (0 ) B g C@



Dominant Pole ResponseDominant Pole ResponseDominant Pole ResponseDominant Pole Response

For p2 >> P1:

Unity Gain Frequency Frequency At Which Gain Magnitude Degrades To One (0 dB)

True Dominant Pole Response Has p2 > u

Advantage Of This Requirement Is Principally Stability In Feedback Networks

Promotes Adequate Phase And Gain Margins (Discussed Later)Feedback, Although Not Necessarily Purposefully Imposed, Is

Unavoidable In High Frequency Networks

For p2 >> P1:

Unity Gain Frequency Frequency At Which Gain Magnitude Degrades To One (0 dB)

True Dominant Pole Response Has p2 > u

Advantage Of This Requirement Is Principally Stability In Feedback Networks

Promotes Adequate Phase And Gain Margins (Discussed Later)Feedback, Although Not Necessarily Purposefully Imposed, Is

Unavoidable In High Frequency Networks

v vv

11 2

A (0 ) A (0 )A ( j )

jj j 1

1 1 pp p

1

v 1v p

A (0 ) pA ( j )

u v 1A (0 ) p



Frequency ResponseFrequency ResponseFrequency ResponseFrequency Response

Zer

o F

requ

ency

Gai

n =

6 =

15.

6 dB

-15

-10

-5

0

5

10

15

20

0.1 0.3 0.6 1.6 4.0 10.0

Normalized Frequency, /p1

Gain

(in

dB

)

p 2 / u = 0.5 1.0

4.0

Ideal Single

Pole



Phase ResponsePhase ResponsePhase ResponsePhase Response

-360

-330

-300

-270

-240

-210

-180

0.1 0.3 0.6 1.6 4.0 10.0

Normalized Frequency, /p1

Ph

ase

An

gle

(deg

rees

)

p 2 / u = 0.51.0

4.0

Ideal Single

Pole

Documents

EE 348: Lecture #03 EE 348: Lecture #03 Circuit Level Models Of CMOS Technology Transistors Prof. John Choma, Jr. University of Southern California Department