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accuracy, and boundary condi-tions to investigate
nonlinearbehavior. Use the circuit in Figure1 to verify the dc gain
and inputbias current of an op amp.
Run a dc analysis on the circuit
in Figure 1, table the data, and havea data sheet handy. The
outer limitfor the calculations is 20% of thetypical numbers in the
data-sheetspecifications. (10% is much bet-ter.) If the calculated
values varyfrom the data-sheet specificationsby more than 20%, the
designermust evaluate each out-of-limitparameter to determine
whether it
can influence the design.The first measurement is the
noninverting input bias current,which is the current in R
3. It
should be approximately equal for
both inputs and approximatelyequal to the
input-bias-currentspecification in the data sheet. Theinput bias
current varies frompicoamperes to microamperesdepending on the IC
process andtype of transistor you use.I
R1I
R2I
BIAS; thus, the currents in
R1 and R2 are normally unequal,causing an output-voltage
error.Very low bias current is negligiblewhen compared with the
signalcurrent, so under low bias-currentconditions, it appears that
I
R1I
R2.
When the designer selects R3
equalto the parallel value of R
1and R
2,
the bias current creates a com-mon-mode offset voltage, and
theop amp rejects common-modevoltage.
The equation for the op-amp
gain, a, is aVOUT/(VV), whichreduces to aV
OUT/V
when the
signal current is much greater thanthe input bias current.
Again, thecalculated dc-op-amp-gain valueshould be within 20% of
the data-sheet value. Running a series ofsimulations with
closed-loop gain,power-supply voltage, load resist-ance, and other
parameters as vari-ables yields more data. A worst-case Bode
analysis demands thatthe Bode calculations use the high-
est possible loop gain, and thisdata establishes it. The dc
loop
gain is the intercept point for the
ac loop gain, so it is a requiredpoint for establishing the
overallloop gain.
It is necessary to verify the dcCMRR (common-mode
rejectionratio), which you can calculateusing the circuit in Figure
2.
Using this circuit for laboratorymeasurements requires
resistorsmatched to 0.0001% to measureCMRR greater than 100 dB.
Thismatching is extremely hard to
accomplish on an ongoing labbasis, thus CMRR measurementsuse
more complicated circuits.Spice uses perfect resistors so it
canmeasure the CMRR with the cir-cuit in Figure 2. For this
circuit,CMRR20log(2V
IN/V
OU T).
First, set the battery equal to 0V
and record the output voltage.Next, set the battery voltage to
1Vand record the output voltage. Theresulting data gives a
reasonablyaccurate dc CMRR that shouldcompare favorably with the
data-sheet CMRR. Now you can varythe input-voltage range,
power-supply range, and other parame-ters, to obtain CMRR data as
afunction of them.
Although these dc-measure-ment techniques are valid, they
contain approximations andassumptions that need
periodicexamination. For instance, thesecalculations neglect input
offsetvoltage, which could be importantin some applications. After
dc ver-ification of the model, you need anac verification of the
modelthetopic of my next column.
32 edn | April 14 , 2005 www.edn.com
Understanding Spice models
To ensure a complete and accurate Spice analy-
sis, you must verify your selected Spice model. Veri-
fication is a three-part exercise: Verify dc perform-
ance to ensure dc accuracy, ac performance to verify ac
VERIFY DC PERFORMANCE TO ENSURE DC ACCURACY, ACPERFORMANCE TO
VERIFY AC ACCURACY, AND BOUNDARY
CONDITIONS TO INVESTIGATE NONLINEAR BEHAVIOR.
analogangle By Ron Mancini
Ron Mancini is a staff scientistat Texas Instruments. You
can
reach him at 1-352-569-9401,[email protected].
VOUT
R31k
RL1kR2
1k
R1
100k
V
1
15V
V2
15V
V310 mV
The inverting op-amp con-
figuration yields bias current and dc-gain
analysis.
R125k
R225k
R325k
R425k
VOUT
V1
15V
V3
0V
V2
15V
This circuit requires
0.0001% matched resis-tors, so it is impractical for lab
use.
F igure 1
F igure 2
