EDLC_2

VidyalankarVidyalankarVidyalankarVidyalankar S.E. Sem. III [CMPN]

Electronic Devices and Linear Circuits Prelim Question Paper Solutions

1. (a) Construction of BJT

Consider a pure semiconductor made of silicon or germanium. We make a layout to develop the PNP or NPN structure.

Consider the construction of PNP transistor. After making the

layout, a photosensitive material is pasted over it to form a

photomask. The remaining region is lightly doped to get an

N−type semiconductor (base material). The photomask is then subjected to UV light, thereby opening the mask. Then the

respective regions are diffused with impurities to form heavily

doped P region (emitter) and medium doped P region (collector)

as shown. The terminals are taken from the respective regions to form E and C. Since the width

of the base region is very small, base terminal cannot be taken from the base. Hence the base

region is divided into two regions.

1) active base (b’) − the region supporting the carrier movement from emitter to collector.

2) passive base (b) − the region between actual base and external base lead.

The passive base offer a high resistance to the flow of current and hence most of the applied base

voltage drops across the passive base. Hence it cannot provide faithful amplification. To prevent

this, the passive base region is isolated and subject to heavy doping so that its conductivity

increases, the base spread resistance (rbb′) decreases. The process continues until rbb′ is within limits say (10 − 100 ohms).

rbb’ plays a dominant role in transistor operation at high frequencies and in power transistors.

1. (b) Transconductance (gm) : It is defined as the ratio of the change in drain current to the change in

the gate source voltage for a constant value of VDS.

gm = D

DSGS

IV

V

∆∆

constant

= slope of transfer characteristics

Expression for gm :

For JFET, DI =

2

GSDSS

p

VI 1

V

−

Differentiate DI with respect to GSV

D

GS

dI

dV = GS

DSSp p

V 1I . 2 1

V V

−−

∴ mg = DSS GS

P p

2I V1

V V

−−

If GSV = 0V, mg = DSSmo

p

2I.g

V

−

mog : is the maximum transconductance when GSV = 0V.

For BFW − 11, mog = 5 m

∴ mg = GSmo

p

Vg 1

V

−

= mog D

DSS

I

I

mg of JFET is very small.

P+ N P

E b′ C

E C

rbb′ B

N-type lightly doped

semiconductor

BJT structure

Passive

base

ID

(mA)

IDSS

VGS Vp 0

∆VGS

∆ID

(2) Vidyalankar : S.E. – EDC

1. (c) (i) Offset Currents and Voltages : While the op-amp output should be 0 V when the input is

0 V, in actual operation there is some offset voltage at the output. For example, if one connects 0 V to both op-amp inputs and then this measures 26 mV (dc) at the output, this

would represent 26 mV of unwanted voltage generated by the circuit and not by the input

signal. Since the user may connect the amplifier circuit for various gain and polarity

operations, the manufacturer specifies an input offset voltage for the op-amp. The output offset voltage is then determined by the input offset voltage and the gain of the amplifier.

(ii) CMRR: When same input voltages are applied to the two terminals, the op−amp is said to be working in common mode. Since op−amp amplifies only the difference, no common mode

signal appears at the output. But due to some imperfections in the op−amp, some common mode signal appears at the output and that voltage gain.

CA = oc cV / V dA = od dV / V

CMRR is defined as the ratio of differential gain to common mode gain and is usually

expressed in dB.

CMRR = 20 10log | d cA / A | dB

Usually high values of CMRR are preferred and it is a function of frequency. It decreases as frequency increases.

(iii) Slew Rate: Slew rate is the maximum rate of change of output voltage with respect to time.

It is expressed in volts/µsec. Ideally, an op−amp should have infinite slew rate. For 741, slew rate is 0.5 Volts/µsec. Let , oV = mV sin tω

odV

dt = mV . Cos tω ω

S = o

max

dV

dt = m max mV 2 f Vω= π

∴ S = max max2 f Vπ Volts/µseconds. Slew rate is a large signal phenomenon. A large signal is one whose amplitude is comparable

to the power supply voltages. Slew rate is caused by current limiting and saturation of

internal stages of the op−amp. When a high frequency large signal is applied, the resulting current is the maximum current available to charge the compensation capacitance network.

The capacitors require a finite amount of time to charge and discharge. The rate at which

voltage across the capacitor rises is cdV I

dt c= .

If slew rate is exceeded, distortion will happen. Thus slew rate limiting is caused by capacitor

charging rate in which voltage across the capacitor is the output voltage.

1. (d) (i) Overload Protection : If the current limit protection is not given, and if the load demands more current e.g. under short circuit conditions, the IC tries to provide it at a constant output

voltage getting hotter all the time. This may ultimately burn the IC.

The IC is therefore, provided with a current limiting facility. Current limiting refers to the

ability of a regulator to prevent the load current from increasing above a preset value. The

output voltage remains constant for load current below Ilimit. As current approaches the limit, the output voltage drops. The current limit Ilimit is set by connecting an external resistor RCL

between the terminals CL and CS as shown in fig. The CL terminal is also connected to Vo

and Cs terminal to the load.

Vin

o/p

C

Prelim Question Paper Solutions (3)

The load current produces a small voltage drop Vsense across RCL. This voltage Vsense is

applied directly across the base emitter junction of Q1. When this voltage is approximately

0.5 V, transistor Q1 begins to turn ON. A part of current from error amplifier goes to the collector of Q1, thereby decreasing the base current of Q2. This in turn, reduces the emitter

current of Q2. So any increase in load current will get nullified.

If the ILOAD decreases, VBL of Q1 drops, repeating the cycle in such a manner that the load

current is held constant to produce a voltage across RCL sufficient to turn ON Q1. This voltage

is typically 0.5 V or 0.65 V.

So, senselim it

CL CL

V 0.5VI

R R= =

This method of current limiting is also referred to as current sensing technique.

(ii) Current Foldback Protection : Current limiting reduces the load voltage when the current

becomes larger than the limiting value. The circuit of figure below provides foldback limiting, which reduces the output voltage and output current protecting the load from

overcurrent, as well as protecting the regulator.

Foldback limiting is provided by the additional voltage-divider network of R4 and R5 in the

circuit of above figure. The divider circuit senses the voltage at the output (emitter) of Q1.

When IL increases to its maximum value, the voltage across RSC becomes large enough to drive Q2, thereby providing current limiting. If the load resistance is made smaller, the

voltage driving on Q2 becomes less, so that IL drops when VL also drops in value. This action

being called foldback limiting. When the load resistance is returned to its rated voltage, the

circuit resumes its voltage regulation action.

2. (a) (i) Collector Feedback : The collector feedback network of Fig. (i) employs a feedback path from collector to base to

increase the stability of the system.

VO

(= VL) Vi

Q1

Q2

R1

R2 R5

R4

RSC

RL

R3

+

Vz

(a)

L O A D

VC ILOAD

Q2

Vo Vsense

+ –

RCL

CL

CS

Q1

Error

Amp

+

–

VBE

Vo

15V

VLOAD

RL = 15 Ω

ILOAD 2.5 A

(b) Characteristic curve

O

2 Ω

Io

6 Ω

Ilimit


Substituting the equivalent circuit and redrawing the network will result in the configuration

of Fig. (ii)

Av : At node C of Fig. (ii),

Io = βIb + I′ For typical values, βIb >> I′ and Io ≅ βIb. Vo = − Io RC = − (βIb) RC

Substituting Ib = Vi/βre gives us,

Vo = i

Ce

VR

r−β

β

and Av = o

i

V

V = C

e

R

r− … (1)

Ai = Applying Kirchhoff's voltage law around the outside network loop yields.

Vi + rRV − Vo = 0

and b e b i F o CI r (I I )R I R 0β + − + =

Using Io ≅ βIb, we have b e b F i F b CI r I R I R I R 0β + − +β =

and b e F C i FI ( r R R ) I Rβ + +β =

Substituting Ib = Io/β from Io ≅ βIb yields

oe F C i F

I( r R R ) I Rβ + + β =

β

and F io

e F C

R II

r R R

β=β + + β

Ignoring βre compared to RF and βRC gives us

Ai = o F

i F C

I R

I R R

β=

+β

For βRC >> RF,

Ai = o F

i C

I R

I R

β=β

and Ai = o

i

I

I≅ F

C

R

R

(ii) The DC equivalent circuit is as shown :

Fig.(ii) : Substituting the re equivalent circuit into

the ac equivalent network

of Fig.(i).

4.7 V

RE = 1 k

VCC = 10 V

RC = 2.2 k


Applying Kirchoff's voltage law to the input circuit yields

− VEE = IE RE + VBE = 0

∴ IE = EE BC

E

V V

R

−

= 4.7 0.7

1k

− =

4

1k

IE = 4 mA

Applying Kirchoff's voltage law to the output circuit yields

− VCB + ICRC − VCC = 0

VCB = VCC − IC RC with IC ≅ IE ∴ VCB = 10 − (4 mA) (2.2 kΩ) VCB = 1.2 V

IB = CI

β =

4mA

100 = 40 µA

∴ IB = 40 µA ∴ VCB = 1.2 V, IE = 4 mA, IB = 40 µA

2. (b) Comparison of BJT and JFET Amplifier

BJT Voltage Amplifier (CE) FET Voltage Amplifier (CS)

1 Current controlled current source. It is a

linear device.

1 It is the voltage controlled constant current

source. FET is square law device.

2 It is operated in active region with input

junction forward biased and output

junction reverse biased.

2 It is always operated in reverse bias mode

3 Input impedance is high and output

impedance is high. 3 As input junction is always reverse biased,

the input impedance is very high (of the

order of 1 MΩ) and high output

impedance.

4 Voltage gain is very high (100 − 500) 4 Voltage gain is low (10 − 20) 5 Current gain is finite (Ai = hfe) 5 Current gain is infinite. ∵ input current is

zero due to reverse bias.

6 The variation of Q point due to changes in temperature is very important. Changes in

Q point with device parameter variations

are less. Hence stability is important for

BJT.

6 Changes in Q point with device parameter variations are very large. Hence JFET

should be biased against device parameter

variations.

7 Small bandwidth due to capacitance effect 7 Large bandwidth since capacitance effect

is negligible.

8 Biasing is complex 8 Biasing is simple

9 Requires small supply voltage 9 Requires very high supply voltage

10 Noise is very high 10 Low noise

11 Current to current converter 11 Voltage to current converter

RS

VS Vi

b

Ib hie e

IC =

hfeIb V0 RL rd

Id =

gmVgs Vgs V0 RL


3. (a) Operational Amplifier Optimizing

Frequency compensation The necessity for frequency compensation is demonstrated by the gain versus frequency plot as

shown. At the first break frequency f01 corresponding to a pole in the amplifier transfer junction,

the gain rolls off at about 6 dB per octave. This continues till the second break frequency is

reached, when the roll of continues at about 12 dB per octave. These poles are caused by various

shunting capacitors within the amplifiers. They introduce a 90° phase shift into the amplifier response which is added to by all subsequent time constants in the amplifier, making the system

unstable.

The tailoring of the frequency response for stabilization of the system is known as frequency compensation. The basic requirement for frequency compensating a feedback amplifier is to keep

the frequency roll off to the loop gain from exceeding 6 dB per octave when it goes through unity

gain, allowing some margin for excess roll off in the actual external circuitry.

For any externally compensated amplifier, increasing the compensation increases the stability of

the system at the expense of slew rate and bandwidth. The type and amount of compensation determines the signal bandwidth for a given gain. The large signal behavior is primarily

determined by their slew rate rather than by bandwidth (for a sine wave signal Vm sinωt, the maximum slew rate is ωVm compared to its frequency ω/2π). Thus, the size of the compensating capacitor should be optimized for a particular operation.

The internally compensated op−amp is a practical choice in all DC and very low frequency applications till about 20 kHz. However the externally compensated op−amp offers greater flexibility where wider bandwidth and /or high slew rate are needed.

Correct frequency compensation of an op−amp will show the difference between a merely adequate amplifier design and one that performs at its best. Some specified standard frequency

compensation techniques for IC op−amps, they cannot possibly indicate optimized stabilization methods. Hence, very often, one turns up with either over compensated circuits with poor high frequency response, or under compensated circuits with tendency to oscillate very easily.

Single Capacitor (Single pole) Compensation

If single capacitor is added to some part of the circuit, which is usually a high impedance point, and a pole is introduced at a frequency f1, from which point the open loop gain rolls off at 6 dB

per octave as shown.

dB

f01 f02 f03 log frequency

Log AOL 6 dB octave

12 dB octave

log 1/β

18 dB octave

max. loop gain

for stability

min. stable closed

loop gain (ACL)

dB f1 f01

f02

f03 fc

12 dB octave

modified open

loop gain

closed loop gain

log frequency


The frequency f1 is chosen such that the frequency fc (at which the loop gain of the system is

unity), is lower than any of the break frequencies f01, f02 etc. This makes the amplifier stable

because of only 90° phase shift at fc.

The compensating capacitor may shunt an internal stray capacitance, shifting one of the poles to

f1. If f01 shifts, fc needs only be less than f02 rather than f01, so that an increase in bandwidth can

be obtained. For unconditionally stable op−amps such as 741, f1 << f02 so that the entire mid band gain of the amplifier is rolled off before the second pole is reached. This means that f1 must

be less than 10 Hz, but it does allow 100% feedback to be applied around the circuit. As an

example, consider the typical compensation scheme for the popular LM 308 op−amp.

Resistor −−−−Capacitor Compensation The single capacitor method of frequency compensation usually causes a reduction of the maximum

slew rate and increased gain bandwidth, obtainable from the amplifier. A resistor capacitor technique gives a higher slew rate and increased gain bandwidth, although it is more difficult to apply since it

relies on a knowledge of the poles in the open loop transfer function of the amplifier.

A resistor and capacitor in series are added to the compensating points so that a break frequency

f1 is produced at f1 = 1/2πRcCc where Cc is the compensating capacitor and Rc is the output resistance at the compensating point.

For the specific case as shown, f02 is shifted to f1 by the compensation time constant. Series

resistor R1 is chosen to remove effect of Cc at a frequency equal to f01 = 1/2πR1Cc, so that the

natural roll off of the amplifier is utilized from f01 to f03.

The unity loop gain frequency fc must be less than f03 and for a required value of closed loop gain, the total roll off is calculated. Once f1 has been calculated from fc and the 6 dB per octave line,

R1 and Cc can be calculated, assuming that Rc and f01 are known. An example of this type of

compensation is as shown for the common circuit for a µA 709 op−amp.

2−

3+

7

4 6 8

1 ei+

ei−

Cc

e0

R3

R1

R2

+ve −ve Cc ≥ 1

1 2

R30 p

R R+ f

dB f1 f01

f02

f03 12 dB octave

open loop gain

closed loop gain

log frequency

2

3

7 4

6

8 1 N.INV

C1

o/p

R1

+ve −ve

INV

C2

5 ΓA709


Two pole compensation

A two pole compensation network as shown provides more than a factor of 2 in improvement in power bandwidth and an order of magnitude reduced gain error at moderate frequencies from DC

to 5 kHz. The network consists of a capacitor C2, which sets the unity gain bandwidth at 1 MHz,

along with capacitor C1 and resistor R1.

C1 = 10 C2

32

3 4

RC 30 pf

R R≥

+

By dividing the ac output voltage by R1C1, there is less voltage across C2 and less current is needed for charging. Since the voltage division is frequency sensitive, the open loop gain rolls

off at 12 dB/octave till a gain of 20 is reached at 50 kHz as shown. From 50 kHz to 1 MHz, R1

offers a large impedance than C1 and thus the gain now rolls off at 6 dB per octave. To ensure sufficient drive to C1, it is connected to the output pin rather than the usual frequency

compensation pin.

This type of frequency compensation is useful in applications like differential amplifiers, audio

amplifier, oscillators and active filters.

The configurations shown above is a typical method

used for the popular LM 301 A op−amp.

Note : Any three compensation techniques are expected.

3. (b) Now RG = R1 || R2 = 2.1 M || 330 k

RG = 285 kΩ

VG = 2 DD

1 2

R V

(R R )+ =

330k 18

(330k 2.2M)

×+

VG = 2.44 V

VGS = VG − IDRS

and ID = 0 mA; VGS = + 2.35 V

VGS = 0 V, ID = 2.35

1.2k = 1.96 mA

2

3

7

4 6

1 ei+

ei−

C2

o/p

R2

R3

R2

+ve −ve

R4

LM 301A

C1

R1

1

0

40

80

120

100 10K 10M

dB

Two pole

log F

single

pole

−10 −9 −8 −7 −6 −5 −4 −3 −2 −1

1 2 3 4 5 6 7 8 9 10

10

9

8

7

6

5

4

3

2

1

VGS

IDSS

QDI = 4.2 mA

VGS = −2.8 V

+2.35DI 0mA

V =

0VD|I

Q point

1.2 k

VDD = 18 V

2.2 k 2.1 M

330 k

VG

R1

R2

RD

RS


The resulting biasline appears in figure with quiescent value,

IDQ = 4.2 mA, VGS = − 2.8 V The ac equivalent circuit is as shown

Now Ri = RG = 285 kΩ

Now level of rd is defined by :

rd = os

1 1

40 s= =

γ µ 25 kΩ

rd = 25 kΩ

QDSV = VDD − ID(RD + Rs)

= 18 − 1.96m(2.2k + 1.2k) = 11.336 V

gm0 = DSS

p

2I 2 10mS2.5mS

| V | 8

×= =

∴ gm = GS

m0p

Vg 1

V

−

= 2.5 mS ( 2.8)

1( 8)

− − −

gm = 1.625 mS

∴ | AV | = gm (RD || rd) RD || rd = 2.2k 25k

(2.2k 25k)

×+

= 2 k

∴ | AV | = 1.625 mS × 2 kΩ | AV | = 3.25

Now RO = Rd || rd

RO = 2 kΩ

∴ aGSV = − 2.8 V;

QDI = 4.2 mA, QDSV = 11.336 V, AV = 3.25, Ri = 285 kΩ,

RO = 2 kΩ

4. (a) Integrator : A circuit in which the output voltage waveform is the integral of the input voltage waveform is

the integrator or the integration amplifier.

Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor RF is replaced by a capacitor CF.

rd

RD

VO

+

− VGS

Vgs gm

+

− RG

+

−


Practical integrator circuit

Fig. (a) is used for practical integrator. In this figure resistor RF is used parallel with CF in basic integrator.

Analysis of practical integrator

0 F

i i

V (s) Z (s)

V (s) Z (s)

−=

where ZF(s) = RF // 1/SCF

= ZF(s) = F

F F

R

R C s 1+

= Zi(s) = Ri.

0 F F F

i 1

V (s) R / R C s 1

V (s) R

− +=

0 F 1

i F F

V (s) R / R

V (s) R C s 1

−=

+

Put s = Jω

A = 0 F 1

i F F

V (s) R / R

V (s) R C j 1

−=

ω+

|A| =

( )0 F 1

2i

F F

V (s) R / R

V (s) R C 1

=ω +

.

At low frequency, ω = 0 |A| = RF/R1.

This will avoid OP-AMP from going into saturation so that due to RF here capacitor has discharging

path. Hence capacitor will not act as open circuit. So using this we can avoid problem of basic integrator.

Vin ~

RF

RL R0M = R1

Fig. (a) : Practical Integrator

CF R1

V0 = ∫− dtVCR

1in

F1

Vcc

-VCC

Zii(s) Zii(s)

t (sec)

Vin

0

1V

−1V

t (sec)

0.5 1.5

0


The frequency response of a practical integrator circuit along with that of the basic integrator

circuit is as shown in figure:

4. (b) V0 = 5 V1 + 2V2 − 3V3 … (i) The following equation can be implemented using IC 741 adder-subtractor configuration.

The general adder-subtractor configuration

is as shown :

For the above configuration :

V0 = f 2 1 f

1 2 33 1 2 1 2 3

R R R R1 V V V

R R R R R R

+ + − + +

Comparing with eq. (i), f

3

R3

R=

Let Rf = 30 kΩ

∴ R3 = 10 kΩ

∴ V0 = (4) 2 1

1 2 31 1 2

R RV V 3V

R R R

+ − +

2

1 2

4R5

R R=

+ and 1

1 2

R 1

R R 2=

+

∴ 2

1 2

R 5

R R 4=

+ and 1

1 2

R 1

R R 2=

+

∴ 2

1

R (5 / 4) 5

R (1/ 2) 2= =

Let R1 = 20 kΩ

∴ R2 = 50 kΩ

VO

RL

+VCC

−VCC

Rf R3

R2

R1

V3

V2

V1

10 f f

0

20

40

60

80

100

102 f 10

3 f 10

4 f 10

5 f

Fig. (b) Frequency response of basic and practical integrator

fc

Basic integrator response

Ideal response of practical integrator

−

dB3dB

R

R

i

F

Actual response of

practical integrator

Relative frequency

Gain (dB)

dBR

R

1

f


∴ The final configuration is as shown

∴

4. (c) (i) The two basic modes in which (5) operates are : (1) Monostable (2) Astable.

(1) Monostable : The monostable multivibrator has only one stable state and one quasi

stable state and it requires triggering. It is often called as one−shot multivibrator. It is a pulse generating circuit in which the duration of the pulse is determined by the RC

network connected externally to the timer circuit. The following figure shows the arrangement for monostable multivibrator.

• Operation : Monostable multivibrator has one quasi-stable (unstable) state and one

stable state. In the stable state output is at ground potential (0V). This is because the

Flip Flop output holds the transistor Q1 ON [Because SET(s) is low] and thus capacitor C is shorted out to ground.

• Circuit diagram

(2) Astable : • Circuit Diagram :

+VCC

−VCC

20 kΩ

V3

50 kΩ

10 kΩ 30 kΩ

IC 741 V2

V1

VO = 5V1 + 2V2 − 3V3

8 4

6

3

7

2

1 5

IC 555

CC31 V

VCC

0

Trigger input

Output

0.01 µF (C1)

VCC

RA

C

Fig. (a) Pin diagram monostable multivibrator

8 4

7

6 3

2

1 5

o/p

+ VCC = +5V

RA

C

555 RB

0.01 µF


An astable multivibrator is often called a free running multivibrator or rectangular

wave generating circuit. Unlike the monostable multivibrator, this circuit does not require an external trigger to change the state of the output. Hence the name free

running. However, the time during which the output is either high or low is

determined by the two resistors and a capacitor, which are externally connected to the

555 timer.

(ii) Duty cycle = A B

A B

R R

R 2R

+

+ × 100 = 60

∴ A B

A B

R R

R 2R

+

+ = 0.6

∴ 0.4 RA − 0.2 RB = 0

∴ 4 RA = 2 RB Now output frequency is given :

f0 = A B

1.44

(R 2R )C+

2 kHz = A A

1.44

(R 4R )C+

∴ 5 RAC = 1.44

2kHz

∴ 5 RAC = 7.2 × 10−4

Assume C = 0.1 µF

∴ 5 RA = 4

8

7.2 10

10 10

−

−

×

×

RA = 7200

5

RA = 1440 Ω

∴ RB = 2 RA = 2880 Ω

∴ The resultant circuit diagram is as shown in figure (i).

5. (a) Introduction to IC Voltage Regulators

A voltage regulator is an electronic circuit which provides a constant output voltage regardless of

changes in the load current, input voltage and the ambient temperature. It provides the constant voltage to a selected range of load from a selected range of input.

Voltage regulators are commonly used for on–card regulation and laboratory–type power supplies. The switching type regulators are especially used as control circuits in pulse–width

modulation (PWM), push–pull bridges, and series–type switch mode power supplies.

723 General Purpose Regulator The three terminal regulators have the following limitations :

(1) No short circuit protection. (2) Output voltage is fixed.

These limitations have been overcome in the 723 general purpose regulator, which can be

adjusted over a wide range of both positive or negative regulated voltage.

This IC is inherently low current device but can be beasted to provide 5 amps or more current by

connecting external components. The limitation of 723 is that it has no in–built thermal

protection. It also has no short circuit current limits.

7

6

2 1 5

3

8 4

0.01 µF

Output

555

RA = 1440 Ω

RB = 2880 Ω

C = 0.1 µF

+VCC = 5 V

Fig.(i)


Functional Block Diagram

Fig. shows the functional block diagram of a 723 regulator IC. It has two separate sections. The zener diode has a constant current source and reference amplifier produce a fixed voltage of about

7V at the terminal Vref. The constant current source forces the zener to operate at a fixed point so

that the zener outputs a fixed voltage. The other section of the IC consists of an error amplifier, a series pass transistor Q2 and a current

limit transistor Q1. The error amplifier compares a sample of the output voltage applied at the

INV input terminal to the reference voltage Vref applied at the NON INV input terminal. The

error signal controls the conduction of Q2.

5. (b) Data : V0 = 5V, ISC = 150 mA, IO = 100 mA, Vsense = 0.7 V, Vin = 15 V

The circuit diagram for the low voltage regulator using IC 722 is as shown:

Now for maximum temperature stability

R3 = 1 2

1 2

R R

R R+ where 966 Ω ≤ R3 ≤ 3.52 kΩ

for ID ≈ 1 mA

Now R1 = R O

D

V V

I

− VR = 7.15 V for LM 723 C

∴ R1 = 7.15 5

1mA

−

R1 = 2150 Ω

Similarly, R2 = O

O

V 5

I 1mA= = 5 kΩ

Ref. Amp

Error Amp.

INV

N. INV

Vref

REF. AMP V

– Current

Limit CL CS

Q1

Freq. compen.

Current Sense

Q2

VC

Booster Terminal

V0

Vg D3

V+

VO

VR

N.Inv

723

V+

VC

Vin

R2

Cre

= 0.1 µF

Inv

C1 = 100 ρF

R1

RCL

V−

CS

CL

E3

F comp


∴ R2 = 5 kΩ

∴ R3 = 1.5 kΩ

∴ the circuit is stable.

Select Cref = 1 µF to reduce reference noise voltage and C1 = 100 ρF for frequency stability.

The value of RCL = sense

m

V

I

Now Vsense = 0.65 V at 25 °C; Im = Ilimit = 65 mA

∴ RCL = 0.65

65m

RCL = 10 Ω

∴ The final circuit diagram is as shown :

5. (c) Voltage divider bias network

i) Circuit diagram

The circuit diagram of voltage divider bias network is as shown.

R1, R2 forms the potential divider network connected across VCC. The voltage across R2 is applied to the base of the

transistor. Taking into consideration, the loading at the base of

transistor.

ii) DC analysis

Thevenizing the base circuit,

thV = BV = 2CC

1 2

RV

R R+ = fixed dc value

thR = BR = R1 || R2

Replacing the base circuit by Thevenin’s equivalent.

Apply KVL to base loop

B BEV V− = B B C B EI R (I I )R+ +

= C CB C E

I IR I R

+ + β β

= CB B E

IR (R ( 1)R )+ + β +

β

∴ CI = B BE

B e

(V V )

R (1 )R

− β

+ + β

If (1 + β) ER >> BR and β >> 1, then

CI ≅ B BE

E

(V V )

(1 )R

− β

+β ≅ B BE

E

V V

R

−

∵ BV >> BEV

CI = B

E

V

R = CC 2

1 2 e

V R

(R R ) R+ = constant.

Hence in voltage divider bias, CI is independent of β.

RC

RE

Q

+VCC

VB

IB

RB

IC

IC + IB

VCE

VBE

VO = 5 V

V+

VC

Vin

V−

5 kΩ

1 µF

lnv

C1 = 100 ρF

R3 = 1.5 kΩ

2.15 kΩ

RCL = 10 Ω VO

CL

CS

F comp.

VR

N.Inv

RC R1

RE

Q

+VCC

R2

VB IB

IC

IE


iii) To find SI

By definition, IS = C

CO

I

I

∆

∆ β, BEV constant.

= B

C

1

dI1

dI

+β

−β

Apply KVL to the base loop

B BEV V− = B B C B EI R (I I )R+ +

= B B E C EI (R R ) I R+ +

Differentiate with respect to CI

0 = BB E E

C

I(R R ) R

I

∂+ +

∂

∴ B

C

dI

dI = E

B E

R

R R−

+

Negative sign indicates that when CI increases, BI decreases and vice versa.

∴ IS = e

B e

1

R1

R R

+β

+β+

IS = B E

B E

(1 )(R R )

R R (1 )

+ β +

+ +β

If (1 + β) ER >> BR , then IS = B E

E

R R

R

+

i.e. IS = B

E

R1

R+

Lower the value of IS , better the perfomance of the circuit. If IS ≤ 10, then the circuit has better Q point stability.

iv) Advantages

• Simple in construction

• Better stability of Q point against

variations in temperature and device parameters.

v) Drawback

Gain decreases due to ac degeneration through ER

This draw back can be rectified by the circuit shown.

6. (a) Analog to Digital Converter

An Analog to Digital converter is a very important building block which has numerous applications. It forms an essential interface when it comes to analyzing analog data with a digital

computer. It is an indispensable part of any digital communication system where the analog

signal to be transmitted is digitized at the sending end with the help of an analog to digital

converter; it is invariably used in all digital read−out test and measuring equipment whether it is a

digital voltmeter or a laser power meter or for that matter a pH meter. An analog to digital converter is the heart of all of them.

RC R1

RE

Q

+VCC

R2

VB

CE


fig. (b)

Analog to Digital converter types

Analog to digital converters are often classified according to the conversion process or the conversion technique adopted to digitize the signal. We have the flash or simultaneous analog to

digital converter, the counter type analog to digital converters, tracking analog to digital

converters, successive approximation type analog to digital converters, single slope and dual

slope integrating type analog to digital converter converters. Nowadays, we are talking about quad slope integrating type analog to digital converter where the converter goes through two

cycles of dual slope conversion, one with zero input and the other with the analog input being

measured. The errors determined in the first cycle are subtracted digitally from result in the second cycle. A brief description of each one of the above mentioned types follows :

A. Simultaneous or flash analog to digital converter : Simultaneous or flash analog to digital converters are the fastest available on the scene. Their

extremely high speed stems from the very nature of their conversion process. The conversion

is done with parallely connected comparators followed by a digital encoding circuit. Fig.(a)

shows the schematic of a 3−bit simultaneous converter. The output status of different comparators depends upon the analog input. The comparator outputs are then encoded into a digital output of desired data format.

Simultaneous (also known as parallel type) analog to digital converters have the disadvantage

of becoming quite unweildy for more than 8 bit resolution converters (even an 8 bit converter would require as many as 255 comparators). A conversion speed of however 150 MHz

(conversion time of approximately 6 ns) in AD9002 from analog devices would have been

possible only with the simultaneous conversion approach. Conversion time in this case is equal to the propagation time of the comparators and the encoding circuit.

B. Counter type analog to digital converter :

DIGITAL OUTPUT

Fig. (a)

R R R R R R R R R

2° 21 2

2

ENCODER

VREF

VA


fig.(d)

fig.(e)

Fig.(b) shows the schematic of a conversional counter type analog to digital converter. The

counter is initially reset to 0. A high comparator output allows the clock pulses to the counter. The counter starts counting upwards with each count increasing the DAC output by

a step. The counter stops counting even when the DAC output equals the analog input. The

counter output at that time instant represents the digital equivalent of the analog input. This converter has the disadvantage that the counter has to reset and start counting from count ‘0’

every time a new analog input is to be digitized. In the worst case, the conversion process

may take as many as 2n cycles. It implies a worst case conversion time of 256 µs in an 8 bit

converter with a 1 MHz clock.

In a modified counter type analog to digital converter known as the tracking type analog to

digital converter (fig.(c)), the counter is not reset every time a new analog input is to be

digitized. An up/down counter is used in place of an up only counter and the control circuitry allows the clock either to the up count input or to the down count input depending upon the

status of the comparator output. This improves the conversion time particularly when the

analog signals are varying slowly like the audio signals.

C. Successive approximation analog to digital converter: Fig.(d) shows the schematic and the conversion chain for

4 bit converter of this type. Successive approximation

register (SAR) is the heart of this converter. The SAR sets the MSB to the DAC input on the first clock cycle, the

second MSB on the second clock input and so on. Every

time a particular bit is set, the bit set prior to this is either kept set or reset depending upon whether the DAC output

obtained by setting the present bit is less than or greater

than the analog input. The SAR proceeds to the LSB in this manner to get the desired output. Each conversion in

an n−bit converter of this type takes n clock cycles. It is the most widely used technique for constructing high speed,

high resolution analog to digital converter.

D. Single slope and dual slope integrating analog to digital converters :

fig.(c)


In the single slope analog to digital converter (fig.(e)) one of the inputs to the comparator is a

ramp of a fixed slope. The counter and the ramp generator are initially reset to 0. The counter starts counting with the first clock cycle input. It stops when the ramp amplitude

equals the analog input. In this case, count is directly proportional to the analog signal. It is

a low cost, reasonably high accuracy converter but is suffers from the disadvantage of loss of

accuracy due to changes in the characteristics of the ramp generator. This problem is overcome in dual slope integrating converter where the unknown voltage is applied to the

integrator input and the counter counts up to a fixed count and then resets. The integrator

input is then switched to a known reference. The number of counts required by the integrator to get back to ‘0’ is directly proportional to the analog input. The advantages of this type of

converter are its accuracy coupled with low cost and its immunity to temperature caused by

variations in integrator components. The disadvantage of this converter is its slow speed.

6. (b) Comparison linear regulators with switch regulators.

Linear Regulators Switch Regulators

Function : Only steps down; input voltage must

be greater than output voltage.

Steps up, steps down or inverse.

Efficiency : Low to medium, but actual battery life depends on load current and

battery voltage over time; high if

Vin − Vout difference is small.

High except at very low load currents

(µA), where switch mode quiescent

current is usually higher.

Waste Heat : High, if average load and or input /

output voltage difference are high.

Low, as components usually run cool

for power levels below low.

Complexity : Low, which usually requires only the

regulator and low value bypass

capacitors.

Medium to high, which usually

requires inductor, diode and filter

caps in addition to the IC; for high power circuits, external FETs are

needed.

Size : Small to medium in portable designs,

but may be larger if heat sinking is

needed.

Larger than linear as low power but

smaller at power levels for which

linear requires a heat suit.

Total Cost : Low Medium to low, largely due to

external components.

Ripple / Noise : Low, no ripple, low noise, better

noise rejection.

Medium to high, due to ripple at

switching rate.

6. (c) Zero Temperature Drift (Effect of Temperature on JFET characteristics)

i) Mutual Characteristics of JFET The operation of JFET is temperature dependent. Hence, when we plot the transfer

characteristics of JFET for different operating temperatures, it can be seen that the drain

current DI decreases with increase in temperature. The transfer characteristics of JFET for

different operating temperatures is as shown.

Assume T3 > T2 > T1. One of the important characteristics of JFET is that all the transfer

characteristics cross a particular point on the transfer

curve. If this point is selected as the operating point of

JFET, it can be seen that the drain current DQI is

independent of temperature. This phenomenon by

which DQI is made independent of temperature is

called Zero Temperature Drift. The condition for Zero

Temperature Drift is | pV | − | GSV | = 0.63 volts.

ID

VGS

DC bias line

0

Q

VGSQ

IDQ

T3

T1

T2


ii) Effect of temperature on mutual characteristics

There are two factors associated with zero temperature drift. 1. When temperature increases, the lattice atoms gain energy, they vibrate faster, hence

collisions between the lattice atom and the carrier increases. Due to increased number of

collisions, the mobility of the carrier decreases. Hence DI decreases with increase in

temperature. Experimentally it is seen that DI decreases by 0.7 % of DI .

∴ ∆ DI = 0.007 DI … (1)

2. When temperature increases, the junction barrier decreases. The decrease in junction barrier increases the width of the channel, hence the resistance offered by the channel

decreases, hence DI increases. Experimentally it is seen that the increase in DI is

proportional to 2.2 mV change in GSV per °C.

∴ ∆ DI = mg ∆ GSV = 3m2.2 10 g−× … (2)

At one point on the transfer curve, the decrease in DI due to decrease in mobility and

increase in DI due to decrease in junction barrier will oppose each other, making the

drain current independent of temperature. This is the principle behind zero thermal drift.

iii) Condition for zero temperature drift

Equating eq. (1) and (2)

0.007 DI = 3m2.2 10 g−×

Substitute for DI and mg

0.007

2

GSDSS

p

VI 1

V

−

= 32.2 10−× × DSS GS

p p

2I V1

V V

−−

∴ 0.007 GS

p

V1

V

−

=

3

p

4.4 10

V

−− ×

∴ p GSV V− = 34.4 10 / 0.007−− ×

= −0.63 volts Hence p GS| V | | V |− = 0.63 volts

6. (d) Biasing is defined as the process by which IC is made independent of β and temperature by allowing IB to vary within its tolerable limits. Different types of biasing circuits are :

i) fixed bias ii) collector to base bias

iii) self bias

iv) voltage divider bias

7. (a) Instrumentation Amplifier In a number of industrial and consumer application, one is required to measure and control

physical quantity. Some examples are measurement and control of temperature, humidity, water flow, light intensity etc. These physical quantities are usually measured with the help of

transducer and the transducer is frequently located some distance away from the measurement

system. The signal levels at the transducer side are often low and their source impedance is high. So the output of transducer has to be amplified so that it can drive the indicator or display system.

This function is performed by instrumentation amplifier. The instrumentation amplifier should

have following characteristics.


Differential amplifier with three OP-AMPs used in instrumentation amplifier.

1. It should have differential inputs.

2. It should have high input impedance and common mode rejection ratio.

3. The amplifier should be provided with simple gain adjustment.

4. It should have low output impedance.

In this circuit OP-AMP 1 and OP-AMP 2 are basically connected in non-inverting configuration.

The only change is that instead of grounding inverting terminal of both OP-AMP [as in non-

inverting OP-AMP] they are connected to resistor R2.

Effectively the inverting terminal of OP-AMP 1 is fed by a voltage V1 through R2 and the

inverting terminal of OP-AMP 2 is fed by a voltage V2 through R2. This is obvious by virtual

ground concept.

Analysis of above circuit :

V0 = 4

0 03

RV V

R

″ ′ −

………(1)

But V0′ = 1 11 2

2 2

R R1 V V

R R

+ −

1 10 2 1

2 2

R RV 1 V V

R R

″ = + −

………(2)

Substitute (2) in (1),

V0 = 4 1 1

2 13 2 2

R 2R 2R1 V 1 V

R R R

+ − +

[ ]4 10 2 1

3 2

R 2RV 1 V V

R R

= + −

A = 0 4 1

2 1 3 2

V R 2R1

V V R R

= + −

.

The gain may be easily adjusted without disturbing circuit’s symmetry by varying the resistance R2.

7. (b) V−−−−I Characteristics of JFET Let GSV = 0V, and when DSV increases gradually, for low values of DSV , the drain current

magnitude is very small, hence DI can’t cause potential gradient, the channel geometry remains

the same, the resistance offered by the channel remains constant, the drain current increases

linearly with applied DSV .

+

−

−

+

−

+

A1

A2

V0

R3

R3

v2

v1

v2

v1

R1

R2

R1

v2

R4

R4

v1

V0′

V0′′


When DSV increases further, the drain current magnitude becomes sufficiently high enough to

cause potential gradient across the length of the channel. The increase in DI causes the depletion

region to widen, causing narrowing of the channel. Since the channel area decreases, there is an

increase in channel resistance, hence the rate of increase of current per unit increase in DSV

decreases. The decrease in DI is as shown in figure (a).

When DSV = | Vp |, the depletion region on each side of the channel join together. The voltage Vp

is called the Pinch−off voltage, since it pinches off the channel connection between drain and source. When DSV > Vp, the depletion region area thickens, hence drop across the depletion

region increases. The electric field produced by the voltage drop across the depletion region

draws the electrons emitted by the source across the depletion region. The voltage drop between

the point ‘A’ and source is constant and is equal to pinch−off voltage. Since the conductivity and geometry between point A and source remain approximately the same, the drain current

DI remains constant as DSV increases above Vp. This is called saturation of the JFET. The

constant value of DI for GSV = 0V is called as drain saturation current DSS[I ] .

When GSV varies, the channel width varies, and hence the channel resistance increases. This

inturn varies the current from drain to source. When GSV becomes more negative, the drain

current DI decreases. At a particular value of GSV , DI becomes zero since the channel gets

completely pinched off. This value of GSV is called GSV off.

For a given JFET, DSSI and GSV off is a constant. The V−I characteristic of JFET is as shown.

7. (c) Differentiator

Fig. (a) shows the basic differentiator or differentiation amplifier. As its name implies, the circuit

performs the mathematical operation of differentiation i.e. the output waveform is the derivative

of the input waveform.

td

dVCRV in1F0 −=

RF C1 V2

+Vcc

-VEE

RL

V1

Ic

Vin

Vc

IB2 = 0

IB1 = 0

R0M = RF

Fig. (a) : Basic Differentiator

IF

| Vp |

IDSS

ID

(mA)

VDS

(V) 0

(a) (b)

(c)

VGS = −2V

VGS = −1V

VGS = 0V

fig. (a)


The differentiator is constructed from a basic inverting amplifier if an input resistor R1 is replaced

by capacitor C1.

Expression for output voltage of basic differentiator

Apply KCL at node V2.

Ic = IB2 + IF ∵ IB2 = 0

Ic = IF

c 2 01

F

d V V VC

dt R

−=

But Vc = Vin − V2

( )in 2 2 0

1F

d V V V VC

dt R

− −=

But V1 = V2 = 0, because A is very large (virtual ground).

0in1

F

VdVC

dt R= − .

in0 F 1

dVV R C

dt= − ………(A)

10 f f −20

0

20

40

60

80

100

102 f 10

3 f 10

4 f 10

5 f

Relative frequency (Hz)

(Fig. b) Frequency Response of differentiator

fb

fa

fc

Closed loop response of practical differentiator :

−20 dB/decade

Closed loop response of

basic differentiator :

20 dB/decade

Open loop

Gain (dB) →

td

dVCRV in1F0 −=

RF C1

+Vcc

-VCC

RL

Vin

R0M

Fig. (c) : Practical Differentiator

CF

~

R1

Z f(s)

if RFC1 > R1C1 or RFCF

Z i(s)


Thus the output voltage is equal to the RFC1 times, the negative instantaneous rate of change of

input voltage Vin with time. Thus minus sign indicates that a 180° phase shift of the output waveform V0 with respect to the input signal.

Drawback of basic differentiator

Phase equivalent of equation (A)

V0(t) = −RFC1in(t)dV

dt

Take L. T. of this equation

V0(s) = −RFC1S Vi(S) where V0(s) and Vi(s) phasor equivalent of V0(t) and Vi(t).

In steady state put s = Jω, then we may write gain A.

A = 0F 1

i

V (s)R C J

V (s)= − ω

|A| = 0F 1

0

V (s)R C

V (s)= ω ………(B)

From equation (B), we can draw frequency response of differential amplifier.

|A| = f/fa, where fa = F 1

1

2 R Cπ.

At f = fa, |A| = 1. i.e. gain will be 0 dB and gain increase with 20dB/decade. Thus at high

frequency differentiator may become unstable.

Similarly second problem is that the impedance (i.e. 1/wc1) decreases with increase in frequency thereby making the circuit sensitive to high frequency noise. So we have to use practical

differentiator to avoid above problems or drawback.

7. (d) Hybrid ππππ Model of Transistor (high frequency model) In normal mode, emitter base junction is forward biased and collector base junction is reverse

biased. When the transistor is operated at high frequencies, the internal capacitance plays a

dominant role. Across the forward biased emitter base junction a diffusion capacitance CD/CS

exists. Across the reverse biased collector base junction a transition capacitance CT/CJ exists. A transistor model that takes into account the internal charge distributions of transistor is called as

hybrid π model of transistor. This model is valid for low as well as high frequency analysis of

transistor. The hybrid π model of CE transistor is as shown.

1) bbr ' : Base spread resistor − the resistance offered by the passive base region; the

voltage drop across this region is represented by bbr ' . bbr ' represent a dominant

role in switching and power transistors. The value of bbr ' should be kept as small

as possible. Typical value of bbr ' in the range (10 − 100 Ω) for ordinary

transistors, and is kept less than 5 Ω in power transistors.

2) b er ' : The ac dynamic resistance of actual base emitter diode. It indicates how much the

base current changes, when base voltage changes. Its typical value is the range 1K to

2K.

b Ib b′ c Ic

e

rbb’

cb’c

rce

rb’c

cb’e rb’e gmVb’e Vbe Vce Vb’e


3) b cr ' : The early resistance, indicates early effect, shows that the transistor is a bilateral

device.

Its typical value > 10 MΩ

Note : By definition, reh = be

ce

V

V

∆

∆ = b e

b e b c

r '

r ' r '+

4) cer : Output resistance of transistor indicates that transistor is not an ideal current

source.

cer = 1/slope of output characteristic of CE transistor.

It’s typical value ≥ 50 K 5) m b eg V ' : Indicates that transistor at high frequencies will work as a charge controlled

current source.

By definition, mg = c

BE

I

V

∆

∆ the transconductance of transistor

= e

1

r = c

T

I

V = cI

26mV

6) b eC ' : The capacitance across the forward biased emitter base junction, due to storage of

charge carriers in the base of transistor at high frequencies. Its typical value iS of

the order of 0.01 µF. 7) b cC ' : The capacitance across the reverse biased emitter base junction, it is the junction

capacitance, its typical value is the order of 1 pF to 10 pF.

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