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ECE 546ECE 546 -- VLSI Systems DesignVLSI Systems Design

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FlipFlip--Flops, & PipeliningFlops, & PipeliningFallFall 20112011

W. Rhett DavisW. Rhett Davis

NC State UniversityNC State University

Slide 1W. Rhett Davis NC State University ECE 546 Fall 2011

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Announcements

HW#6 Due Tuesday

Start forming project groups

3-person groups

e-mail me your names and Unity IDs

I will assign you a group number and post it to the class web-a e

Slide 2W. Rhett Davis NC State University ECE 546 Fall 2011

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Summary of Last Lecture

Is this a positive or anegative latch? Does is

CLK

wor y oop- rea ngor loop-forcing? How shouldyou size the transistors? CLK

How do you calculate the minimum clock-period for a

design?

What are the types of timing constraints? Which one isthe most critical to satisfy?

Using the skew definition from the last lecture, if theclock edge at the source register arrives BEFORE the

Slide 3W. Rhett Davis NC State University ECE 546 Fall 2011

clock edge at the destination register, is the skew

positive or negative?

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Todays Lecture

.

pe n ng .

Slide 4W. Rhett Davis NC State University ECE 546 Fall 2011

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Static vs. Dynamic Latches

Dynamic (charge-based)Static

D Q

CLK

CLKCLK

Q

CLK

Slide 5W. Rhett Davis NC State University ECE 546 Fall 2011

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Dynamic Flip-Flop

1 21 2

What are the dynamic nodes?

Rising-Edge or Falling Edge Triggered?

Estimate tsu, thold, and tc-q based on the delays of

the transmission gates and inverters.

Slide 6W. Rhett Davis NC State University ECE 546 Fall 2011

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Clock-Overlap

Problem: Both latches are

Assume tsu and thold arerelative to CLK

What timing constraints are

needed to ensure proper

Falling-edge (ensure input

doesnt propagate to slave)

Rising-edge (ensure input

doesnt propagate to master)

Slide 7W. Rhett Davis NC State University ECE 546 Fall 2011

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Clock-Overlap

Consider CLK later thanCLK: Both latches are

still transparent Assume tsu and thold are

What timing constraints

are needed to ensure

Falling-edge (ensure inputdoesnt propagate to slave)

Rising-edge (ensure inputdoesnt propagate to

Slide 8W. Rhett Davis NC State University ECE 546 Fall 2011

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C2MOS (Clocked CMOS) Register

Insensitive to CLK and CLK overlap

reven s a c ange on rom a ec ng ur ng over ap

VDD VDD

M4

M2

CLK CLK M8

M6

D Q

M3CLKCL1

X

CL2M7CLK

M1 M5

Slide 9W. Rhett Davis NC State University ECE 546 Fall 2011

Master Stage Slave Stage

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Insensitive to Clock-Overlap

VDD VDD VDD VDD

M4

M2

0 0 M8

M6 M2 M6

D QX

M3

D Q

1

X

M71

M1 M5 M1 M5

D 01: doesnt chan e X

(a) (0-0) overlap (b) (1-1) overlap

D 01: chan es X but not Q

Slide 10W. Rhett Davis NC State University ECE 546 Fall 2011

D 10: changes X, but not Q D 10: doesnt change X

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Disadvantage to C2MOS

M2

VDD

M6

VDD

D Q

M4CLK

X

CLK M8

M1

M3CLKCL1 CL2

M5

M7CLK

Master Stage Slave Stage

Short-Circuit currents destroy charge stored at X and Q