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ECE 875: Electronic Devices. Prof. Virginia Ayres Electrical & Computer Engineering Michigan State University [email protected]. Lecture 31, 28 Mar 14. Chp 04: metal-insulator-semiconductor junction: GATES Capacitances: Low frequency voltage sweep: 1 Hz to 1KHz - PowerPoint PPT Presentation
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ECE 875:Electronic Devices
Prof. Virginia AyresElectrical & Computer EngineeringMichigan State [email protected]
VM Ayres, ECE875, S14
Lecture 31, 28 Mar 14
Chp 04: metal-insulator-semiconductor junction: GATES
Capacitances: Low frequency voltage sweep: 1 Hz to 1KHz High frequency voltage sweep: > 1Mz
- slow ramp: Pr. 4.06- fast ramp
Use Gate voltage:Sweeping Vgate for example ± 4 Volts over and over to turn the channel OFF and ON: binary logic
Low: 1- 1 kHz
Intermediate: 1 kHz - 1 MHz
High: > 1 MHzVgate: Slow rampVgate: Fast ramp
Slow ramp (sweep) Fast ramp (sweep)
C-V curves and Frequencies:
ON/OFF cycles per sec
“counting” charge per sec applied to gate
VM Ayres, ECE875, S14
C /
Ci
C-V curves for n-channel in p-substrate:
ONOFF
Low
High + slow ramp
Intermediate
High + fast ramp
VM Ayres, ECE875, S14
C /
Ci
What looks different in the readout: flat line in Vfor and Cmin shift
ONOFF
Low
High + slow rampCmin
C’min
Vmin
V’min = VT
VM Ayres, ECE875, S14
CDmin = CminCi
Ci + Cmin
Cmin = Ci CDmin
Ci + CDmin
You know the experimental values in the circles.Therefore it’s easy to get a number for Cdmin
Low frequency C-V:
VM Ayres, ECE875, S14
Low: 1- 1 kHz: develop (ON) and later remove (=> OFF) a full inversion layer and a full depletion region
++++++++++
oooooooooo
p-type Si: NA =B
B- B- B- B- B- B- B- B- B- B-
++++++++++
e- e- e- e- e- e- e- e- e- e-
CD Qs region
Ci across insulator region
Low frequency C-V:
VM Ayres, ECE875, S14
> 1 MHz: develop and later remove a full depletion region charge qNAWD. But e-’s don’t have time to form a full inversion layer at the surface
++++++++++
oooooooooop-type Si: NA =B
B- B- B- B- B- B- B- B- B- B-
++++++++++
e- e- e- e- e- e- e- e- e- e-
High frequency + slow ramp:
Fig. 8, (b)
VM Ayres, ECE875, S14
High frequency + slow ramp: simpler:
C’Dmin = s /WDmax
C’min = Ci C’Dmin
Ci + C’Dmin
So total capacitance C’min is:
VM Ayres, ECE875, S14
Qn smaller
WDmax is bigger
Low frequency High frequency,Slow ramp
VM Ayres, ECE875, S14
Have been finding WD = WDm at the start of inversion with s = 2 kT/q ln (NA/ni).
But (Qs, s) can be bigger
High frequency + slow ramp: WDmax
From strong inversion up to thermal energy
VM Ayres, ECE875, S14
High frequency + slow ramp: WDmax:
VM Ayres, ECE875, S14
Assume that Pr. 4.06 the high frequency- slow ramp condition
VM Ayres, ECE875, S14
Qn smaller
WDmax is bigger
Low frequency High frequency,Slow ramp
High frequency,Fast ramp
WDmax is biggest
Qn layer; no time to form at all
Qn biggest
VM Ayres, ECE875, S14
High frequency + fast ramp: during ON:
No Qn and big WDmax: “driven into deep depletion”
VM Ayres, ECE875, S14
s (@x = 0)CD Qs region
VM Ayres, ECE875, S14
Ci across insulator region
VM Ayres, ECE875, S14
s
VGate
Iterate Pr. 3.9 until donor concentration ND-nth – ND-(nth+1) = 0.01 x 1016 cm-3