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ECE 551: Digital System Design & Synthesis

Lecture Set 1010.1: Functional & Timing

Verification10.2: Faults & Testing

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ECE 551 - Digital System Design & Synthesis Lecture 10.1 - Functional & Timing Verification

Overview Functional Validation Timing Verification Elimination of ASIC Timing Violations False Paths Dynamically-Sensitized Paths System Tools for Timing Verification

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Functional Validation - 1 Validation of functionality of post-synthesis

netlist compared to pre-synthesis RTL model

Not verification of correctness which should be determined using RTL model

Approaches Formal methods - proof of equivalence Simulation

• Comparison of simulation outputs resulting from application of a rigorously-derived input tests

• Can be simulated simultaneously or separately with post-simulation comparison of results

• Coverage of mismatches depends heavily on the test pattern sequences applied

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Functional Validation - 2 Simulation Mismatch

RTL model is delay-free; gate-level model contains propagation delays.

• Mismatch may be due to improperly written RTL model or due to the speed of the synthesized circuit

• Code modification, re-synthesis, and/or change in target specifications may be necessary to resolve.

The RTL description contains races between assignment of one or more variables, improperly used blocking assignments, or asynchronous logic

Don’t care conditions in the RTL model become “care” conditions in the gate-level model

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Timing Verification

Dynamic Timing Analysis - Simulation

Static Timing Analysis - Signal path analysis

Timing Specifications Pragmatics: Factors that Affect

Timing

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Dynamic & Static Timing Analysis Comparison

Dynamic StaticMethod Simulation Path Analysis

Test Vectors Used

Yes No

Coverage Test Pattern Dependent

Test Pattern Independent

Risk Missed violations False Violations

Min-Max Analysis

No Yes

Coupled with Synthesis

Not Feasible Yes

CPU Run Time Days/Weeks Hours

Memory Use Heavy Low-Moderate

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Dynamic Timing Analysis - 1 Coverage of timing violations dependent

on effectiveness of applied test vectors Vectors are not just static, but also

involve one or more changing inputs For the simplest timing model, pairs of

vectors are required In sequential circuits, to achieve a

“vector pair” internally may require a long sequence of vectors on the external ports

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Dynamic Timing Analysis - 2 How are effective test patterns produced? Critical path concept - longest delay path through

a circuit - requires consideration of flip-flop propagation delays, flip-flop setup times, delays to inputs from flip-flops and delays from outputs to flip-flops per prior discussion

Elimination of one critical path may simply produce others until timing constraints are meet - thus a set of many paths may need to be considered

How are critical paths identified? Ad Hoc Using timing analysis!

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Dynamic Timing Analysis - 3 Critical path determination may be very

difficult since it can be dependent on applied values

Once path determined, need to “sensitize” the output of the path to an input change

Requires fixing of “off path” values according to controlling input patterns on gates

Can be made very complex due to reconvergent fanout paths

More complex when using tPHL and tPLH values due to changes in delay based on inversion control on the path

Example of complex DTA case

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Static Timing Analysis - 1 Creates directed, acyclic graph (DAG) of

circuit by abstracting the topology of the net list

Implicitly analyzes all possible paths to determine critical delay path

Example of simple STA case (no slide) But there are issues re accuracy

Problems of multiple paths with the same entry and exit points due to reconvergent fan-out

Complexity introduced by tPHL and tPLH values Issue of false paths - paths through the DAG

down which no signal can propagate from input to output

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Static Timing Analysis - 2

Requires introduction of functional information: Dealing with multiple paths with same

entry and exit point Dealing with tPHL and tPLH and inversions on

path Requires user assistance

Dealing with false paths Example of complex STA case (no slide)

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Timing Specifications

Already covered in Synthesis Constraints lecture (9.1)

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Pragmatics: Factors that Affect Timing Basics covered in lecture on Synthesis

Constraints (9.1) Addition of Concepts of Skew and Jitter in timing

equations: skew = tclk2 - tclk1 - clock period If tclk2 is late, then skew > 0, if early, skew < 0 jitter = the absolute value of the worst case variation

at a given location with respect to the ideal periodic reference clock edge

In the worst case, with a + jitter on the driving FF clock edge and a - jitter on the driven FFs clock edge, the reduction in the clock period is 2 x jitter.

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Synchronous

Slack - the extra time available for signals to propagate from the clock to the input of a flip-flop (FF) slack = ideal clock period - path delay - setup

+ skew - 2 x jitter

Constraint - setup slack

specified clock periodMaximum FF, combinationaland wiring delay

slack

setup

skew < 0

jitterjitter

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Synchronous

“Hold” Slack - the extra delay present for signals to propagate from the clock to the input of a flip-flop (FF)

slack = path delay - skew - 2 x jitter - hold

Constraint - hold slack

Minimum FF, combinationaland wiring delay

slack

holdskew > 0

jitter

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Elimination of ASIC Timing Violations

Action EffectRe-synthesize with changed options

Reduce path delays

Rewrite Verilog code Reduce path delays

Substitute a different algorithm Reduce Path delays

Substitute architectures Reduce path delays

Resize and substitute devices Reduce device delays

Reroute critical paths Reduce net delays

Redesign the clock gen & tree Reduce clock skew & jitter

Lengthen the clock cycle Eliminates violation, but …

Change technologies Reduce path delays

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False Paths

See Figure 11-18 in Text See Figure 11-20 in Text

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Dynamically Sensitized Paths

Will be missed by static timing analyzer

May or may not be handle by simulation depending on inputs

Example

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System Tasks for Timing Verification

Tests for: Setup condition Hold condition Setup and hold conditions Pulse width constraint Signal Skew Constraint Clock period Recovery time

Use of specify block

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Setup and Hold Tests

Common statements for examples `timescale 100 ps / 10 ps reg [7:0] data; reg clk;

$setup(data_event, reference_event, limit) Example: $setup(data, posedge clk, 1)

$hold(reference_event, data_event, limit) Example: $hold(posedge clk, data, 0.5)

$setuphold(reference_event, data_event, setup_limit, hold_limit) Example: $setuphold(posedge clk, data, 1, 0.5)

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Clock and Recovery Tests

Common statements for examples `timescale 100 ps / 10 ps reg [7:0] data; reg clk, clk1, clk2;

$width(reference_event, limit) Example: $setup(posedge clk, 2)

$skew(reference_event, data_event, limit) Example: $skew(posedge clk1, posedge clk2, 1)

$period(reference_event, limit) Example: $period(posedge clk, 5)

$recovery(reference_event, data_event, limit) Example: $recovery(negedge reset, posedge clk, 2)