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ECE 551: Digital System Design & Synthesis

Lecture Set 99.1: Constraints and Timing

(In separate file)9.2: Optimization - Part 1

9.3: Optimization - Part 2

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ECE 551 - Digital System Design & Synthesis Lecture 9.2 - Optimization and Timing Analysis

Overview Optimization Phases Compilation Types Optimization Flow Compilation Strategies Controlling Specific Optimization Steps Controlling Logic-Level and Gate-Level

Optimization

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References

Design Compiler Reference Manual: Optimization and Timing Analysis

Design Compiler User Guide

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Optimization Process

Optimization modifies the initial netlist resulting from elaboration. Uses cells from the technology library Attempts to meet all specified constraints

The process is divided into major phases All or some selection of the major phases

may be performed during optimization Phase selection can be controlled by the

user

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Major Optimization Phases

Combinational optimization Technology-independent Technology-dependent

Sequential optimization Initial Final

I/O pad optimization Local optimizations

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Combinational Optimization Converts a logic-level description to a gate-level

netlist Example: See next slide Subphases: See slide after next

Technology-independent • Operates at the Boolean level with interconnected gates

represented by Boolean equations.• Applies algebraic and Boolean techniques• Flattening and Structuring (covered later!)

Technology-specific (mapping)• Operates at the gate level • Selects components from library to approach defined area

and delay goals (covered later!)

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Combinational Optimization

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Combinational Optimization

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Initial Sequential Optimization

Maps sequential logic to cells in the library First phase of technology-specific

optimization Cannot select optimum sequential cell due to

lack of combinational delay info Defines sequential cells producing “islands”

of combinational logic Sets timing constraints on combinational

“islands” required to meet setup and hold constraints on the sequential cells

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Final Sequential Optimization

Optimizes timing critical sequential logic Later phase of technology-dependent optimization Has accurate values for delays through I/Os and through

combinational logic Effects:

• Improve delay by using higher-performance sequential cells

• Reduce delay and area by use of complex sequential cells

• Improve area by remapping sequential elements (due to setting compile_sequential_area_recovery to true)

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I/O Pad Optimization

Insertion and mapping of I/O pads Follows mapping of combinational logic

and initial mapping of sequential logic Adds input and output buffers to each

port in top-level design Sizes buffers to meet timing constraints

on paths involving inputs and outputs Uses smallest buffer that meets timing

specs to reduce current and power consumption

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Local Optimization Incremental modifications to locally

optimize gate level logic Final phase of gate level optimization Example: See next slide Effects

• Improve delay• Improve area

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Local Optimization

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Compilation Types

Full - optimizes a complete RTL design Can include all of the various phases

both technology-independent and technology-dependent

Removes and rebuilds logic/gate structure across entire design

Invoked by compile

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Compilation Types (continued)

Test-Ready - integrates optimization and scan insertion Accounts for timing impact of scan

design throughout the synthesis process Eliminates recompile after scan

insertion Invoked by compile -scan

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Compilation Types (continued)

Incremental - focuses on areas of design where constraints not met Structures where constraints met are

preserved Incremental mapping begins with existing

gates from earlier compilation Restructuring only if area or speed

improved Invoked with compile -incremental_mapping

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Compilation Types (continued)

Top Level - fixes constraint violations at top level as subblocks in the design are assembled. Assumes subblocks compiled and

meeting timing constraints Design rule violations fixed even if in

subblocks Invoked with compile -top

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Compilation Types (continued)

Critical Path Resynthesis Finds critical path and attempts full

compilation on logic along that path Repeats on new critical path Requires DC Expert version Invoked with compile -map_effort_high

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Compilation Types (continued) Logic Duplication and Mapping to Wide-

Fanin Gates (DC Ultra only) Evaluates cells along critical path Determines if timing or area can be improved

by replacing cell groups with complex, wide-fanin cells

Also improves timing of high-fanout or heavily-loaded nets by duplicating and restructuring large sections of logic

Improves timing at expense of area

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Compilation Types (continued) Optimizing Once for Best- and Worst-

Case Conditions Optimizing with Multiple Libraries

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Optimization Flow FSM Optimization Subdesign Ungrouping (set_ungroup) High-Level Optimization Synthetic Library Implementation Selection Sequential Inference Flattening Structuring Initial Combinational Mapping I/O Pad Insertion and Optimization

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Optimization Flow (continued) Mapping Optimization

Phase 1: Delay Optimization Phase 2: Design Rule Fixing, Part 1 (no

delay cost increase) Phase 3: Design Rule Fixing, Part 2 (delay

cost increase; not set_cost_priority delay) Phase 4: Area Optimization

Verifying Design Functionality

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Compilation Strategies

StrategiesTop-down hierarchicalCompile-characterize-write script-recompile

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Top-Down Hierarchical Compile (TDHC) Hierarchy not collapsed Constraints at top level Continues to optimize circuit until all

constraints met after each module compiled

Requires recompile of subdesigns on critical paths

Stops when no further improvement or goals achieved

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TDHC (continued) Note that entire design is being

manipulated at once Default strategy Intermodule dependencies handled

automatically Multiple instances of same design must be

handled using: uniquify set_dont_touch ungroup

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TDHC (continued) Procedure:

Read in entire design Make top level the current design Resolve multiple references: dcug 8-18 to 8-26 Apply constraints and attributes at the top level Compile

Preserves hierarchy and optimizes individual levels based on constraints at top level

Example: dcrmo pp. 2-5 to 2-7 Acrobat Document

Acrobat Document

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Compile-Characterize- Write Script-Recompile (CCWSR) Optimize (nonunique) designs using

context information or time budgets Mark lower level blocks that have been

optimized don’t_touch Optimize higher level blocks in succession Useful for medium/large designs without

good interblock specifications Facilitates large designs since only single

block in optimization at a time

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CCWSR (continued)

Requires iteration until design is stable Requires manual revision control Procedure:

1. Compile subblocks independently using a default script for drive and load estimates

2. Read in entire compiled design3. Characterize one subblock4. Use write_script to save characterization

info

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CCWSR (continued)

5. Clear memory; read in previously characterized subblock and recompile using saved script

6. Read in the entire compiled design again without the old subblock; use recompiled subblock

7. Choose another subblock and repeat steps 3 through 7 until all subblocks are recompiled, using their actual environments.

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CCWSR (continued)

Comments Compile automatically goes down

hierarchy to submodules - to restrict to current design, remove or omit submodule from database or use set_dont_touch

Compile is bottom-up Characterize is top-down

Example: dcrmo pp. 2-9 and 2-10Acrobat Document

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CCWSR (Continued)

What is really being done if pure CCWSR used? Compile all subblocks bottom up using rough

estimates of drive, load and timing constraints. Note that some constraints such as clock period are known.

Read in the entire design and apply the top level constraints. Then the attributes and constraints of any subblock can be determined based on the prior compile of all subblocks.

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CCWSR (Continued)

The above is precisely what characterize does.

The script written captures the attributes and constraints of the subblock chosen (one with worst violations is a good choice)

The subblock can then be recompiled based on this current “state” of the optimization process.

The new subblock replaces the old and process repeated for a different subblock

See Chapter 7 of User Guide for Script!

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Mixing Strategies

See figure on next slide Detailed time budget for A, B, C, and D

means they can be compiled separately.

Procedure• Compile A• Use CCWSR for the ascending the hierarchy at B• Compile C• Use TDHC for the hierarchy at D

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Mixing Strategies