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VLSIBasic Concepts
V(x)
V(y)
fVOH = f (VIL)
VIL VIH
V(y)=V(x)
Switching ThresholdVM
VOL = f (VIH)
V(y)V(x)
Contents
Property of Digital CircuitsQuantization of AmplitudesRegenerativeDirectivityFan-In, Fan-Out
Power and Energy Dissipation
NoiseCapacitiveInductivePower and Ground Bounce
Noise MarginsExample TTLExample CMOS
Noise Immunity
Ideal Logic ElementVTCDelay DefinitionsDelay Simplicity
InvertersCMOS Properties CMOS InverterVTCDetermining VIL and VIHDelay ComputingComputing the CapacitancesPower ConsumptionDelay Minimizing
Property of Digital Circuits
Quantization of AmplitudesRegenerativeDirectivityFan-In, Fan-OutPower and Energy Dissipation
Voltage Transfer Characteristics (VTC)
V(x)
V(y)
fV(y)V(x)
VOH = f (VIL)
VIL VIH
V(y)=V(x)
Switching ThresholdVM
VOL = f (VIH)
Nominal Voltage Levels
Quantization (Mapping Logic Levels)
V(x)
V(y)Slope = -1
Slope = -1
VOH
VOL
VIL VIH
The regions of acceptable high and low voltages are determined by VIH and VIL that represent the points on the VTC curve where the gain=-1
"1"
"0"
UndefinedRegion
VOH
VOL
VIL
VIH
V(y)V(x)
Property of Digital Circuits
Quantization of AmplitudesRegenerativeDirectivityFan-In, Fan-OutPower and Energy Dissipation
The Regenerative Property
v0 v1 v2 v3 v4 v5 v6
-1
1
3
5
0 2 4 6 8 10
t (nsec)
V (v
olts
) v0
v2v1
A gate with regenerative property ensure that a disturbed signalconverges back to a nominal voltage level
Conditions for Regeneration
v1 = f(v0) ⇒ v1 = finv(v2)
v0 v1 v2 v3 v4 v5 v6
v0
v1
v2
v3 f(v)
finv(v)
Regenerative Gate
v0
v1
v2
v3
f(v)
finv(v)
Nonregenerative Gate
To be regenerative, the VTC must have a transient region with a gain greater than 1 (in absolute value) bordered by two valid zones where the gain is smaller than 1. Such a gate has two stable operating points.
Property of Digital Circuits
Quantization of AmplitudesRegenerativeDirectivityFan-In, Fan-OutPower and Energy Dissipation
Directivity
A gate must be undirectional: changes in an output level should not appear at any unchanging input of the same circuit
In real circuits full directivity is an illusion (e.g., due to capacitive coupling between inputs and outputs)
Key metrics: output impedance of the driver and input impedance of the receiver
ideally, the output impedance of the driver should be zeroinput impedance of the receiver should be infinity
Property of Digital Circuits
Quantization of AmplitudesRegenerativeDirectivityFan-In, Fan-OutPower and Energy Dissipation
Fan-In and Fan-Out
N
M
Fan-out – number of load gates connected to the output of the driving gate
gates with large fan-out are slower
Fan-in – the number of inputs to the gate
gates with large fan-in are bigger and slower
Property of Digital Circuits
Quantization of AmplitudesRegenerativeDirectivityFan-In, Fan-OutPower and Energy Dissipation
Power and Energy Dissipation
Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates
supply line sizing (determined by peak power)Ppeak = Vddipeak
battery lifetime (determined by average power dissipation)p(t) = v(t)i(t) = Vddi(t) Pavg= 1/T ∫ p(t) dt = Vdd/T ∫ idd(t) dt
packaging and cooling requirements
Two important components: static and dynamic
E (joules) = CL Vdd2 P0→1 + tsc Vdd Ipeak P0→1 + Vdd Ileakage
P (watts) = CL Vdd2 f0→1 + tscVdd Ipeak f0→1 + Vdd Ileakage
f0→1 = P0→1 * fclock
Power and Energy Dissipation
Propagation delay and the power consumption of a gate are related Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors
the faster the energy transfer (higher power dissipation) the faster the gate
For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant
Power-delay product (PDP) – energy consumed by the gate per switching event
An ideal gate is one that is fast and consumes little energy, sothe ultimate quality metric is
Energy-delay product (EDP) = power-delay
peak peak supplyP i V max(p(t))= =
T Tsupply
av supply0 0
VP p(t)dt i (t)dt
T T= =∫ ∫
1
av pPDP P t Energy dissipated per operation= × =
Power-Delay Product
tp=?
Power and Energy Dissipation
Ring Oscillator for Delay Measurement
v0 v1 v2 v3 v4 v5
v0 v1 v5
T = 2 × tp × N
Other Specification
NoiseCapacitiveInductivePower and Ground Bounce
Noise MarginsExample TTLExample CMOS
Noise Immunity
Noise
In a digital circuit, noise is unwanted voltages.If noise amplitude at the input of any logic circuit is smaller than a specified critical magnitude known as the noise margin of that circuit, the noise amplitude will be attenuated. In actual practice, the noise is greater because the voltage must be increased to the switching threshold.Switching actually occurs in the undefined region. Varies widely by manufacturer, temperature and quality of chip.
Sources of Noise in Digital Integrated Circuits
v(t)
i(t)
VDD
from two wires placed side by sidecapacitive coupling
• voltage change on one wire can influence signal on the neighboring wire
inductive coupling• current change on one wire can
influence signal on the neighboring wire
from noise on the power and ground supply rails
can influence signal levels in the gate
Other Specification
NoiseCapacitiveInductivePower and Ground Bounce
Noise MarginsExample TTLExample CMOS
Noise Immunity
Noise Margins
OLILL
IHOHH
VVNMVVNM
−=−=
VIH and VIL are defined by the points on the voltage transfer curve where the slope is 1.
Noise Margins
UndefinedRegion
"1"
"0"
Gate Output Gate Input
VOH
VIL
VOL
VIHNoise Margin High
Noise Margin Low
NMH = VOH - VIH
NML = VIL - VOL
Gnd
VDD VDD
Gnd
Example TTL
InputVoltage
2V
.8V
+5.5V
GND
High
Low
Undefined
High
Low
Undefined
OutputVoltage
GND
+5.5V
2.4V
.4V
Typical 3.5V
Typical .1V
TTLVoltage characteristics of TTL Logical 0 (Low): GND - 0.8VLogical 1 (High): 2- 5.5V NML=?NMH=?NM=?
Example CMOS
InputVoltage
3V
+10V
GND
High
Low
Undefined
High
Low
Undefined
OutputVoltage
GND.5V
7V
+10V9.5V
CMOSVoltage characteristics of CMOSLogical 0 (Low): GND - 0.5VLogical 1 (High): 7-10VNML=?NMH=?NM=?
Other Specification
NoiseCapacitiveInductivePower and Ground Bounce
Noise MarginsExample TTLExample CMOS
Noise Immunity
Noise Immunity
Noise margin expresses the ability of a circuit to overpower a noise source
noise sources: supply noise, cross talk, interference, offsetAbsolute noise margin values are deceptive
a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)
Noise immunity expresses the ability of the system to process and transmit information correctly in the presence of noiseFor good noise immunity, the signal swing (i.e., the difference between VOH and VOL) and the noise margin have to be large enough to overpower the impact of fixed sources of noise
The Ideal Logic Element
VTCDelay DefinitionDelay Simplicity
g = - ∞
Vout
Vin
Ri = ∞
Ro = 0
Fanout = ∞
NMH = NML = VDD/2
The Ideal Logic Element (VTC)
The ideal Logic should haveinfinite gain in the transition regiona gate threshold located in the middle of the logic swinghigh and low noise margins equal to half the swinginput and output impedances of infinity and zero, respectively
o inV =V
VTC of Real Inverter
0.0 1.0 2.0 3.0 4.0 5.0Vin (V)
1.0
2.0
3.0
4.0
5.0
Vou
t (V
)
VMNMH
NML
The Ideal Logic Element
VTCDelay DefinitionDelay Simplicity
Delay Definitions
t
Vin
Vout
inputwaveform
t
50%
tpHL
50%
tpLH
tf
90%
10%tr
signal slopes
tp = (tpHL + tpLH)/2
Propagation delay
outputwaveform
The Ideal Logic Element
VTCDelay DefinitionDelay Simplicity
Delay Simplicity
cyclet
cyclet
t
t
0
0OLV
inV
outV
OHV
PLHtPHLt
OHV
50%
OLV
Vin Vout
Propagation delay
tp = (tpHL + tpLH)/2
Inverters
CMOS PropertiesCMOS Inverter
VTCDetermining VIL and VIHDelay ComputingComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
CMOS Properties
Full rail-to-rail swingSymmetrical VTCPropagation delay function of load capacitance and resistance of transistorsNo static power dissipationDirect path current during switching
Inverters
CMOS Properties CMOS Inverter
VTCDetermining VIL and VIHDelay ComputingComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
CMOS Inverter
Polysilicon
In Out
VDD
GND
PMOS 2λ
Metal 1
NMOS
OutIn
VDD
PMOS
NMOS
Contacts
N Well
Inverters
CMOS Properties CMOS Inverter
VTCDetermining VIL and VIHDelay ComputingComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
Vout
Vin1 2 3 4 5
12
34
5
NMOS linPMOS off
NMOS satPMOS sat
NMOS offPMOS lin
NMOS satPMOS lin
NMOS linPMOS sat
CMOS Inverter VTC
MV
0.1 0.3 1.0 3.2 10.01.0
2.0
3.0
4.0
kp/kn
VM
Switching Threshold (VM) as a Function of Transistor Ratio
DD Tp TnM
r(V V )+VV
1+r−
=p
n
kr=
k
Inverters
CMOS Properties CMOS Inverter
VTCDetermining VIL and VIHDelay ComputingComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
Determining VIL and VIH(Method1)
Write the large signal equation for input/output relationAt VIH (or VIL):
out
in
VV
∂= −
∂1
Determining VIL and VIH(Method2)
VOH
VOL
Vin
Vout
VM
VIL VIH
( )OH OL DDIH IL
MIH M
DD MIL M
DD IH
IL
V V VV Vg g
VV Vg
V VV Vg
NMH=V VNML=V
− −− = − =
= −
−= +
−
A simplified approach
Determining VIH and VIL(Method2)
inV mn ing V outVonr oprmp ing V
( ) ( )outmn mp on op
in
vg= g g r rv
= − + ×
Inverter Gain
0 0.5 1 1.5 2 2.5-18
-16
-14
-12
-10
-8
-6
-4
-2
0
Vin (V)
gain
Gain as a function of VDD
0 0.05 0.1 0.15 0.20
0.05
0.1
0.15
0.2
Vin (V)
Vou
t (V)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin (V)
Vou
t(V)
Gain=-1
Impact of Process Variations
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin (V)
V out(V
)
Good PMOSBad NMOS
Good NMOSBad PMOS
Nominal
Inverters
CMOS Properties CMOS Inverter
VTCDetermining VIL and VIHDelay computingComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
Delay Computing Approach 1
VDD
Vout
Vin = VDD
CLIav
tpHL = CL Vswing/2
Iav
CL
kn VDD~
Delay Computing Approach 2
Switch Model of CMOS Transistor
Ron
|VGS| < |VT| |VGS| > |VT|
|VGS|
Delay Computing Approach 2
tpHL = f(Ron.CL)
V outVout
R n
R p
V DDV DD
CLCL
(a) Low-to-high (b) High-to-low
Delay Computing Approach 2
Model circuit as first-order RC networkvout (t) = (1 – e–t/τ)V
where τ = RC
Rvout
C
vin Time to reach 50% point ist = ln(2) τ = 0.69 τ
tpHL = 0.69RonCL
Time to reach 90% point ist = ln(9) τ = 2.2 τ
Transient Response
0 0.5 1 1.5 2 2.5
x 10-10
-0.5
0
0.5
1
1.5
2
2.5
3
t (sec)
Vou
t(V)
tp = 0.69 CL (Reqn+Reqp)/2
tpLHtpHL
Inverters
CMOS Properties CMOS Inverter
VTCDetermining VIL and VIHDelayComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
Computing the Capacitances
VDD VDD
Vin Vout
M1
M2
M3
M4Cdb2
Cdb1
Cgd12
Cw
Cg4
Cg3
Vout2
Fanout
Interconnect
VoutVin
CLSimplified
Model
The Miller Effect
Vin
M1
Cgd1Vout
∆V
∆V
Vin
M1
Vout ∆V
∆V
2Cgd1
“A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.”
Computing the Capacitances
Capacitor Expression
Cgd1 2 CGD0 Wn
Cgd2 2 CGD0 Wp
Cdb1 Keqn(ADnCJ+PDnCJSW)
Cdb2 Keqp(ADpCJ+PDpCJSW)
Cg3 CoxWnLn
Cg4 CoxWpLp
Cw From Extraction
CL ∑
t pH
L(ns
ec)
0.35
0.3
0.25
0.2
0.15
trise (nsec)10.80.60.40.20
Impact of Rise Time on Delay
2 2pHL pHL(step) rt t (t /2)= +
0
4
8
12
16
20
24
28
2.00 4.001.00 5.003.00
Nor
mal
ized
Del
ay
VDD (V)
Delay as a function of VDD
Propagation Delay Scaling
NMOS/PMOS ratio
1 1.5 2 2.5 3 3.5 4 4.5 53
3.5
4
4.5
5x 10
-11
β
t p(sec
)
tpLH tpHL
tp
β = Wp/Wn
Inverters
CMOS Properties CMOS Inverter
VTCVIL and VIHDelayComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
Power Consumption
Static Power ConsumptionLeakage Diodes and TransistorsSubthreshold Leakage Component
Dynamic Power ConsumptionCharging and Discharging of CapacitorsShort Circuit path Between Supply Rails During Switching
Inverters
CMOS Properties CMOS Inverter
VTCVIL and VIHDelayComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
Static Power ConsumptionStatic Power Consumption
Vin=5V
Vout
CL
Vd d
Istat
Pstat = P(In=1).Vdd . Istat
Leakage
Sub-threshold current one of the most compelling issues in low-energy circuit design!
Vout
Vdd
Sub-ThresholdCurrent
Drain JunctionLeakage
ReverseReverse--Biased Diode LeakageBiased Diode Leakage
Np+ p+
Reverse Leakage Current
+
-Vdd
GATE
IDL = JS × A
JS = 10-100 pA/µm2 at 25 deg C for 0.25µm CMOSJS doubles for every 9 deg C!
Subthreshold Leakage Component
Leakage control is critical for low-voltage operation
Inverters
CMOS Properties CMOS Inverter
VTCVIL and VIHDelayComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
Dynamic Power Consumption
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Vin Vout
CL
Vdd
Not a function of transistor sizes!Need to reduce CL, Vdd, and f to reduce power
Vin Vout
CL
Vdd
I VD
D (m
A)
0.15
0.10
0.05
Vin (V)5.04.03.02.01.00.0
Short Circuit CurrentsShort Circuit Currents
How to keep ShortHow to keep Short--Circuit Currents Low?Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,but can’t do this for cascade logic, so ...
Minimizing ShortMinimizing Short--Circuit PowerCircuit Power
0 1 2 3 4 50
1
2
3
4
5
6
7
8
tsin/tsout
P norm
Vdd =1.5
Vdd =2.5
Vdd =3.3
Keep the input and output rise/fall times the same(<10% of total Consumption)
IEEE JSSC Aug. 1984 by Veendrick
If Vdd < Vtn + |Vtp| then Short-circuit power can be eliminated!
Principles for Power Reduction
Prime choice: Reduce voltage!Recent years have seen an acceleration in supply voltage reductionDesign at very low voltages still open question (0.6 … 0.9 V by 2010!)
Reduce switching activityReduce physical capacitance
Total Power Dissipation
( )fCVP
VIIP
PPP
DDdynamic
DDleakagequiescentstatic
dynamicstatictotal
2=
+=
+=
Propagation Details
Most of Load is simple, but:Non-linear Self Capacitance
• Drain Junction and SidewallsRatio Logic
• Other current sources/sinks
Beware Body EffectSource at different potential from back
Inverters
CMOS Properties CMOS Inverter
VTCVIL and VIHDelayComputing the Capacitances
Power ConsumptionStatic Power ConsumptionDynamic Power Consumption
Delay Minimizing
Delay Minimizing
Inverter ChainInverter DelayOptimum Delay
Example1Example2( Buffer Design)
Inverter Chain
CL
In Out
If CL is given:How many stages are needed to minimize the delay?How to size the inverters?
May need some additional constraints.
Delay Minimizing
Inverter ChainInverter DelayOptimum Delay
Example1Example2( Buffer Design)
Inverter Delay
WNunit
Nunit
unit
PunitP RR
WWR
WWRR ==⎟⎟
⎠
⎞⎜⎜⎝
⎛≈⎟⎟
⎠
⎞⎜⎜⎝
⎛=
−− 11
tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL
2.5W
W
unitunit
gin CWWC 3=
Minimum length devices, L=0.5umAssume that for WP = 2.5WN = 2.5W
same pull-up and pull-down currentsapprox. equal resistances RN = RPapprox. equal rise tpLH and fall tpHL delays
Analyze as an RC network
Delay (D):
Load for the next stage:
Inverter with LoadDelay
RW
RW
CL
Load (CL)
tp = k RWCL
k is a constant, equal to 0.69Assumptions: no load -> zero delay
Wunit = 1
Inverter with Load
Load
Delay
Cint CL
CN = Cunit
CP = 2.5Cunit
2.5W
W
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)= Delay (Internal) + Delay (Load)
Delay Formula
( )
( ) ( )γ/1/1
~
0int ftCCCkRt
CCRDelay
pintLWp
LintW
+=+=
+
Cint = γCgin with γ ≈ 1f = CL/Cgin - effective fanoutR = Runit/W ; Cint =WCunittp0 = 0.69RunitCunit
Apply to Inverter Chain
In
CL
Out
1 2 N
tp = tp1 + tp2 + …+ tpN
⎟⎟⎠
⎞⎜⎜⎝
⎛+ +
jgin
jginunitunitpj C
CCRt
,
1,1~γ
LNgin
N
i jgin
jginp
N
jjpp CC
CC
ttt =⎟⎟⎠
⎞⎜⎜⎝
⎛+== +
=
+
=∑∑ 1,
1 ,
1,0
1, ,1
γ
Delay Minimizing
Inverter ChainInverter DelayOptimum Delay
Example1Example2( Buffer Design)
Optimal Sizing for Given N
1,1,, +−= jginjginjgin CCC
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivativesResult: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
each stage has the same effective fanout (Cout/Cin)each stage has the same delay
Optimum Delay and Number of Stages
1,/ ginLN CCFf ==
N Ff =
( )γ/10N
pp FNtt +=
When each stage is sized by f and has same fanout f:
Effective fanout of each stage:
Minimum path delay
Delay Minimizing
Inverter ChainInverter DelayOptimum Delay
Example1Example2( Buffer Design)
Example1
CL= 8 C1
In Out
C11 f f2
283 ==f
CL/C1 has to be evenly distributed across N = 3 stages:
Optimum Number of Stages
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛+=+=
fffFt
FNtt pNpp lnln
ln1/ 0/1
0γ
γγ
0ln
1lnln2
0 =−−
⋅=∂
∂
fffFt
ft pp γ
γ
For γ = 0, f = e, N = lnF
fFNCfCFC in
NinL ln
ln with ==⋅=
( )ff γ+= 1exp
For a given load, CL and given input capacitance Cin Find optimal sizing f
Delay Minimizing
Inverter ChainInverter DelayOptimum Delay
Example1Example2( Buffer Design)
Example2( Buffer Design)N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
1 64
1 8 64
1 4 6416
1 642.8 8 22.6