IMPORTANT GUIDELINES VHDL is case insensitive language. Either asynchronous or synchronous RESET will be asked. If nothing is mentioned its Asynchronous RESET "With Enable" or "without Enable" will be asked in the exam. If nothing is mentioned you can write your choice. The module size may vary from what you did in the lab (eg. 8-bit counter instead of 4-bit / 4x16 decoder instead of 3x8 decode etc..) Specifically behavioral OR Data flow style will be asked for selected programs. Prepare both styles. SRAM,ROM, FIFO programs will also be asked in the final exam Develop the habit of modularity and commenting in the programming Dont forget to add the following lines at the beginning; else you will not get results. Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Note: This document is NOT error-free... so use with caution! REPORT ERROR TO ME VISIT www.esnips.com/user/ttreddy for softcopy and visit regularly for many more useful documents and links. --------------------------------------------------------------------Program No1(A): 3x8 Decoder DATA-FLOW style --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity V3to8dec is port ( enable : in STD_LOGIC; A : in STD_LOGIC_VECTOR(2 downto 0); Y : out STD_LOGIC_VECTOR(0 to 7) ); end V3to8dec; architecture arch_V3to8dec of V3to8dec is signal Y_temp: STD_LOGIC_VECTOR(0 to 7); begin with A select