Ecad Lab Manual1

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VIGNANA BHARATHI INSTITUTE OF TECHNOLOGY, HYDERABAD 1

BY VIDYA SAGAR.P

IC&ECAD LABORATORY

MANUAL III B.Tech

I Sem PREPARED BY

VIDYA SAGAR.P M.Tech(VLSI)

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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

III Year B.Tech. ECE. I-Sem T P C 0 3 2

IC APPLICATIONS AND ECAD LAB Minimum Twelve Experiments to be conducted : (Six from each part A & B) Part A (IC Application Lab): 1. OP AMP Applications – Adder, Subtractor, Comparator Circuits. 2. Active Filter Applications – LPF, HPF (first order) 3. Function Generator using OP AMPs. 4. IC 555 Timer – Monostable and Astable Operation Circuit. 5. IC 566 – VCO Applications. 6. Voltage Regulator using IC 723. 7. 4 bit DAC using OP AMP. Part B (ECAD Lab): Simulate the internal structure of the following Digital IC’s using VHDL / VERILOG and verify the operations of the Digital IC’s (Hardware) in the Laboratory 1. D Flip-Flop 7474 2. Decade counter-7490 3. Shift registers-7495 4. 3-8 Decoder -74138 5. 4 bit Comparator-7485 6. 8 x 1 Multiplexer -74151 and 2x4 Demultiplexer-74155 7. RAM (16x4)-74189 (Read and Write operations) Equipment required for Laboratories: 1. RPS 2. CRO 3. Function Generator 4. Multi Meters 5. IC Trainer Kits (Optional) 6. Bread Boards 7. Components:- IC741, IC555, IC566, IC1496, IC723, 7805, 7809, 7912 and other essential components. 8. Analog IC Tester For Software Simulation 1 Computer Systems 2 LAN Connection (Optional) 3 Operating Systems 4 VHDL/ VERILOG 5 FPGAS/CPLDS (Download Tools)


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1. IC7474—D FLIP FLOP AIM: To verify the functioning of the IC7474— D FLIP FLOP using VHDL simulator. APPPARATUS:

For Software Simulation

1 Computer Systems. 2 LAN Connection (Optional). 3 Operating Systems. 4 VHDL/ VERILOG. 5 FPGAS/CPLDS (Download Tools).

THEORY:

Data Latch: This device contains two independent positive edge-triggered D flip- flops with

complementary outputs. The information on the D input is accepted by the flip-flops on

the positive going edge of the clock pulse. The triggering occurs at a voltage level and is

not directly related to the transition time of the rising edge of the clock. The data on the D

may be changed while the clock is low or high without affecting the outputs as long as

the data setup and hold times are not violated. A LOW logic level on the preset or clear

inputs will set or reset the outputs regardless of the logic levels on the other inputs.

One of the main disadvantages of the basic SR NAND Gate Bistable circuit is that the

indeterminate input condition of "SET" = logic "0" and "RESET" = logic "0" is

forbidden. That state will force both outputs to be at logic "1", overriding the feedback

latching action and whichever input goes to logic level "1" first will lose control, while

the other input still at logic "0" controls the resulting state of the latch. In order to prevent

this from happening an inverter can be connected between the "SET" and the "RESET"

inputs to produce a D-Type Data Latch or simply Data Latch as it is generally called.


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Data Latch Circuit

We remember that the simple SR flip-flop requires two inputs, one to "SET" the output

and one to "RESET" the output. By connecting an inverter (NOT gate) to the SR flip-flop

we can "SET" and "RESET" the flip-flop using just one input as now the two latch inputs

are complements of each other. This single input is called the "DATA" input. If this data

input is HIGH the flip-flop would be "SET" and when it is LOW the flip-flop would be

"RESET". However, this would be rather pointless since the flip-flop's output would

always change on every data input. To avoid this an additional input called the "CLOCK"

or "ENABLE" input is used to isolate the data input from the flip-flop after the desired

data has been stored. This then forms the basis of a Data Latch or "D-Type latch".

The D-Type Latch will store and output whatever logic level is applied to its data

terminal so long as the clock input is high. Once the clock input goes low the SET and

RESET inputs of the flip-flop are both held at logic level "1" so it will not change state

and store whatever data was present on its output before the clock transition occurred. In

other words the output is "latched" at either logic "0" or logic "1".


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PIN DIAGRAM:

LOGIC SYMBOL:


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LOGIC DIAGRAM:

FUNCTION TABLE:


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TRUTH TABLE:

for the D-type Flip-flop

Clk D Q QN OUTPUT

0 x Q Q HOLD

1 0 0 1 RESET

1 1 1 0 SET

PROCEDURE: Write the concerned VHDL program for the given design following the steps in

implementation process in VHDL text editor, check the syntax, check the synthesis if

synthesis completes successfully then go for the simulation and verify the design using

test bench wave form and then implement it into the desired FPGA or CPLD.

VHDL CODE: --VHDL code for the circuit----comments----

library ieee; use ieee.std_logic_1164.all; entity dff is port(d,clk:in bit; q,qn:out bit); end dff; architecture dffbh of dff is begin process(d,clk) begin if(clk'event and clk='1')then q<=d; qn<=not d; end if; end process; end dffbh;


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RESULT: WAVEFORMS:

VIVA QUESTIONS:

1. Write the behavioral code for the IC 74x74. 2. Write the dataflow code for the IC 74x74. 3. What is the difference between sequential and combinational circuit? 4. What is a flip-flop? 5. Explain the functions of preset and clear inputs in flip-flop? 6. What is meant by a clocked flip-flop? 7. What is meant by excitation table? 8. What is the difference between flip-flop and latch? 9. What are the various methods used for triggering flip-flops? 10. Explain level triggered flip-flop? 11. Write the behavioral code for IC 74X74. 12. Write the syntax of IF statement? 13. Realize D flip-flop using data flow model. 14. How can delay be incorporated? 15. Write a program for the structural model of D-Flip-flop using logic gates. 16. Explain “Synchronize the asynchronous signals”. 17. Generate a program, which uses the output of a 4 bit MUX as the D input of a D

flip-flop using structural model. 18. Write a VHDL program for a gated D latch. 19. Write a program for DFF with asynchronous reset. 20. Write a VHDL program for DFF with synchronous reset. 21. Show how a JKFF can be constructed using a DFF. 22. Construct a clocked DFF, triggered on rising edge of CLK, using two

transparent D latches and any necessary gates. 23. A gated D latch will hold its o/p value if a=0 and o/p follows D if a is 1. Write

a VHDL Description of a gated D latch using a process.


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2.IC 74x90 – DECADE COUNTER AIM: To verify the functioning of the IC 74x90 – DECADE COUNTER using VHDL Simulator. APPPARATUS:



THEORY:

The binary counters previously introduced have two to the power n states. But counters

with states less than this number are also possible. They are designed to have the number

of states in their sequences, which are called truncated sequences. These sequences are

achieved by forcing the counter to recycle before going through all of its normal states.

A common modulus for counters with truncated sequences is ten. A counter with ten

states in its sequence is called a decade counter. The circuit below is an implementation

of a decade counter.

Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice that

only Q1 and Q3 are used to decode the count of ten. This is called partial decoding, as

none of the other states (zero to nine) have both Q1 and Q3 HIGH at the same time.


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The sequence of the decade counter is shown in the table below:

The 7490 integrated circuit counts the number of pulses arriving at its input. The number of pulses counted (up to 9) appears in binary form on four pins of the ic.

When the tenth pulse arrives at the input, the binary output is reset to zero (0000) and a single pulse appears at another output pin. So for ten pulses in there is one pulse out of this pin. The 7490 therefore divides the frequency of the input by ten. If this pulse is applied to the input of a second 7490 then this second ic will count the pulses from the first ic. It will give one pulse out after 100 pulses have been applied to the first ic.


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The 7490 can be connected to divide by other values.

Decimal Binary

0 0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001

PIN DIAGRAM:


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LOGIC SYMBOL:

LOGIC DIAGRAM:


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FUNCTION TABLE:

TRUTH TABLE:

OUTPUT Q(0) Q(3) Q(2) Q(1)

0 0 0 0 0 1 1 1 1 1

0 0 0 0 1 0 0 0 0 1

0 0 1 1 0 0 0 1 1 0

0 1 0 1 0 0 1 0 1 0






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VHDL CODE:

library IEEE; --library definition use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;

entity Counter is --entity definition port ( clk:in std_logic; reset: in std_logic; q: out std_logic_vector(3 downto 0) ); end Counter;

architecture Counter of Counter is -- Architecture definition begin process(clk,reset) -- Process definition

variable qtemp: std_logic_vector(3 downto 0); -- temporary variable for begin output q[3..0] if reset='1' then qtemp:="0000"; -- Reset asychroniously else if clk'event and clk='1' then -- Counting state if qtemp<9 then qtemp:=qtemp+1; -- Counter increase else qtemp:="0000"; -- Return the zero state end if; end if; q<=qtemp; -- Output end if; end process; -- End Process end Counter;


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RESULT: WAVEFORMS:

VIVA QUESTIONS: 1. Write the behavioral code for IC 74x90. 1. What is a sequential circuit? 2. Differentiate between synchronous and asynchronous counter? 3. How many no. of flip-flops are required for decade counter? 4. What is meant by excitation table? 5. What are the meanings of different types of values in std_ulogic? 6. What are the objects in VHDL? 7. Write the syntax for a signal? 8. Write the difference between signal and variable? 9. Explain about enumeration types? 10. If the modulus of a counter is 12 how many flip-flops are required? 11. Realize decade counter using data flow model 12. State the purpose of IEEE 1164 library 13. What do you mean by 9 value logic? 14. Write a VHDL model for 74163 counter. 15. A synchronous (4bit) up down decade counter with o/p q works as follows. all state changes occur on the rising edge of CLK i/p , except the asynchronous clear (CLR).When CLR = 0 , the counter is reset regardless of values of other inputs If the load input is 0, the data i/p is loaded into the counter. If Load =ENT = ENP= UP=1 the counter is incremented If Load =ENT=ENP=1 and UP=0, the counter is decremented If ENT=UP=1, the carry output (CO) =1 when counter is in state a. If ENT =1 and UP=0, the carry output =1 when counter is in state 0. 16. Write a VHDL model for a 74HC192 synchronous UP/ down counter. 17. Write a Structural model for 74163 counter. 18. Write a VHDL Behavioral model for 7490 BCD counters. 19. Write a VHDL structural model for 7490-ripple counter. 20. Write a VHDL data flow model for 74290 BCD counter.


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3.IC 74x95 – SHIFT REGISTER AIM: To verify the functioning of the IC 74x95 -SHIFT REGISTER using VHDL simulator. APPPARATUS:



THEORY:

Shift Registers:

Shift Registers consists of a number of single bit "D-Type Data Latches" connected together in a chain arrangement so that the output from one data latch becomes the input of the next latch and so on, thereby moving the stored data serially from either the left or the right direction. The number of individual Data Latches used to make up Shift Registers are determined by the number of bits to be stored with the most common being 8-bits wide. Shift Registers are mainly used to store data and to convert data from either a serial to parallel or parallel to serial format with all the latches being driven by a common clock (Clk) signal making them Synchronous devices. They are generally provided with a Clear or Reset connection so that they can be "SET" or "RESET" as required.

Generally, Shift Registers operate in one of four different modes:

Serial-in to Parallel-out (SIPO) Serial-in to Serial-out (SISO) Parallel-in to Parallel-out (PIPO) Parallel-in to Serial-out (PISO)


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Serial-in to Parallel-out:

4-bit Serial-in to Parallel-out (SIPO) Shift Register

Lets assume that all the flip-flops (FFA to FFD) have just been RESET (CLEAR input) and that all the outputs QA to QD are at logic level "0" ie, no parallel data output. If a logic "1" is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and the resulting QA will be set HIGH to logic "1" with all the other outputs remaining LOW at logic "0". Assume now that the DATA input pin of FFA has returned LOW to logic "0". The next clock pulse will change the output of FFA to logic "0" and the output of FFB and QB HIGH to logic "1". The logic "1" has now moved or been "Shifted" one place along the register to the right. When the third clock pulse arrives this logic "1" value moves to the output of FFC (QC) and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level "0" because the input has remained at a constant logic level "0".

The effect of each clock pulse is to shift the DATA contents of each stage one place to the right, and this is shown in the following table until the complete DATA is stored, which can now be read directly from the outputs of QA to QD. Then the DATA has been converted from a Serial Data signal to a Parallel Data word.

Clock Pulse No QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0


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Serial-in to Serial-out:

This Shift Register is very similar to the one above except where as the data was read directly in a parallel form from the outputs QA to QD, this time the DATA is allowed to flow straight through the register. Since there is only one output the DATA leaves the shift register one bit at a time in a serial pattern and hence the name Serial-in to Serial-Out Shift Register.

4-bit Serial-in to Serial-out (SISO) Shift Register

This type of Shift Register also acts as a temporary storage device or as a time delay device, with the amount of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly available IC's include the 74HC595 8-bit Serial-in/Serial-out Shift Register with 3-state outputs.

Parallel-in to Serial-out

Parallel-in to Serial-out Shift Registers act in the opposite way to the Serial-in to Parallel-out one above. The DATA is applied in parallel form to the parallel input pins PA to PD of the register and is then read out sequentially from the register one bit at a time from PA to PD on each clock cycle in a serial format.

4-bit Parallel-in to Serial-out (PISO) Shift Register


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As this type of Shift Register converts parallel data, such as an 8-bit data word into serial data it can be used to multiplex many different input lines into a single serial DATA stream which can be sent directly to a computer or transmitted over a communications line. Commonly available IC's include the 74HC165 8-bit Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out

Parallel-in to Parallel-out Shift Registers also act as a temporary storage device or as a time delay device. The DATA is presented in a parallel format to the parallel input pins PA to PD and then shifts it to the corresponding output pins QA to QD when the registers are clocked.

4-bit Parallel-in/Parallel-out (PIPO) Shift Register

As with the Serial-in to Serial-out shift register, this type of register also acts as a temporary storage device or as a time delay device, with the amount of time delay being varied by the frequency of the clock pulses.

Today, high speed bi-directional universal type Shift Registers such as the TTL 74LS194, 74LS195 or the CMOS 4035 are available as a 4-bit multi-function devices that can be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and as a parallel-parallel Data Registers, hence the name "Universal".


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PIN DIAGRAM:


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LOGIC SYMBOL:

LOGIC DIAGRAM:


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TRUTH TABLE:

mode control

clock function

0 1

clk0 clk1

Serial operation

q(2) to q(3), q(1) to q(2), q(0) to q(1),

si to q(0)

Parallel operation A to q(0) B to q(1) C to q(2) D to q(3)


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FUNCTION TABLE:






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VHDL CODE: -- Description :shiftregister :in this one we r going to use one --control line . depending on that it rotates shift left , shiftright and --it will rotate left and rotateright. library IEEE; use IEEE.STD_LOGIC_1164.all; entity sregister is port( control : in STD_LOGIC_vector(1 downto 0); reset : in STD_LOGIC; clk : in STD_LOGIC; din : in STD_LOGIC_vector(3 downto 0); rout : out STD_LOGIC_vector(3 downto 0) ); end sregister; architecture sregister of sregister is signal REG: STD_LOGIC_VECTOR(3 downto 0); begin process (CLK,reset) begin if(reset='0')then reg<="0000"; elsif clk'event and clk='1' then case control is when "00"=> reg<=din(2 downto 0)& '0'; --shift left when "01"=> reg<='0'& din(3 downto 1); --shiftright when "10"=> reg<=din(2 downto 0)& din(3);--rotateleft when "11"=> reg<=din(0)&din(3 downto 1);--rotateright when others=> null; end case; end if; end process; rout <= reg; end sregister;


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VHDL code in structural style: library ieee; use ieee.std_logic_1164.all; entity ic7495 is port(ds,p0,p1,p2,p3,s,cp1bar,cp2bar:in std_logic; q0,q1,q2,q3:out std_logic); end ic7495; architecture sftrg of ic7495 is component rsff port(r,s,clk,set,clr:in std_logic; q:buffer std_logic); end component; signal d0,d1,d2,d3,db0,db1,db2,db3,clk:std_logic; signal one,q11,q22,q33,q44:std_logic; begin one <= '1'; clk <= cp2bar when s = '1' else cp1bar; d0<= not((not(s) and ds)or(s and p0)); d1<= not((not(s) and q11)or(s and p1)); d2<= not((not(s) and q22)or(s and p2)); d3<= not((not(s) and q33)or(s and p3)); db0<=not(d0);db1<=not(d1);db2<=not(d2);db3<=not(d3); q0<=q11;q1<=q22;q2<=q33;q3<=q44; u1 : rsff port map ( d0,db0,clk,one,one,q11 ) ; u2 : rsff port map ( d1,db1,clk,one,one,q22 ) ; u3 : rsff port map ( d2,db2,clk,one,one,q33 ) ; u4 : rsff port map ( d3,db3,clk,one,one,q44 ) ; end sftrg;


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--rs flip-flop--neg edge with set and clr library ieee; use ieee.std_logic_1164.all; entity rsff is port(r,s,clk,set,clr:in std_logic; q:buffer std_logic); end rsff; architecture rsf of rsff is begin process(clk,set,clr) begin if (clr = '0') then q <= '0'; elsif(set = '0') then q <= '1'; elsif falling_edge(clk) then q <= (not(r) and s)or(r and s)or(not(r) and not(s) and q); end if; end process; end rsf; ________________________________________________________________________ RESULT:


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WAVEFORMS:

VIVA QUESTIONS: 1. What are the applications of shift registers? 2. Which flip flop is used in shift register? 3. What is universal shift register? 4. What are different types of shift registers? 5. Which shift gives multiplication by 2? 6. Which shift gives division by 2? 7. Can we use shift register as counter? 8. How timing sequences can be generated using shift registers? 9. Explain the working of 4-bit SIPOshift register? 10. What are glitches in digital circuits? 11. Realize shift register using data flow model. 12. Realize shift register structural model. 13. How can bits be rotated in VHDL? 14. Write a VHDL module that describes a 16-bit serial –in serial out shift register with i/ps SI(serial i/p), En (enable), and CK (clock) and serial o/p (So). 15. Write a VHDL code for 8 bits serial – in, parallel out. 16. Write a VHDL code for 4 but parallel in serial out shift register. 17. Realize a 8-bit serial –in serial out shift register. 18. Realize 7491 using VHDL code.


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5.3x8 DECODER

AIM: To verify the functioning of the IC74138 -3 TO 8 DECODER using VHDL

simulator.

APPARATUS:



THEORY:

A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. The input code generally has fewer bits than the output code, and there is a one-to- one mapping from input code words into output code words. In a one-to-one mapping, each input code word produces a different output code word. The general structure of a decoder circuit is shown in Figure5-31. The enable inputs, if present, must be asserted for the decoder to perform its normal mapping function. Otherwise, the decoder maps all input code words into a single, “disabled,” output code word. The most commonly used input code is an n-bit binary code, where an n-bit word represents one of 2n different coded values, normally the integers from 0 through 2 n −1. Sometimes an n-bit binary code is truncated to represent fewer than 2 n values. For example, in the BCD code, the 4-bit combinations 0000through 1001 represent the decimal digits 0–9, and combinations 1010 through 1111 are not used. The most commonly used output code is a 1-out-of-m code, which contains bits, where one bit is asserted at any time. Thus, in a 1-out-of-4 code with active-high outputs, the code words are 0001, 0010, 0100, and 1000. With active-low outputs, the code words are 1110, 1101, 1011, and 0111. A decoder is similar to demultiplexer except that there is no input line. It is a circuit with many inputs & many outputs. An n x m decoder means that there are n inputs and m outputs. Out of the m outputs, only one of the output line will be in state ‘1’ and remaining m - 1 outputs will be ‘0’. For example, a 2 to 4 decoder will have 2 inputs and 4=22 outputs. Some decoders have one or more enable inputs that are useful for expanding decoders. Large expanded decoders will have more gate delays than an equivalent array of AND gates. One advantage of an expanded decoder is the number of input signals to each AND gate is less.


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Truth Table

2 x 4 Decoder

Enable Select Outputs G S1 S0 Y0 Y1 Y2 Y3 0 X X 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1

A decoder has a single data input, n control inputs and 2 outputs. The control inputs (called select S) represent Binary index of output to which the input is connected. The data input is usually called "enable" (G) Consider (O0, O1 .. On) as outputs, (S0, S1 .. Sn) as select inputs, and G as enable input.

For a 1:2 Decoder:

O0 = G . S

O1= G . S

For a 2:4 Decoder

O0 = G . S0 . S1

O1 = G . S0 . S1

O2 = G . S0 . S1

O3 = G . S0 . S1


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For a 3:8 Decoder

O0 = G . S0 . S1 . S2

O1 = G . S0 . S1 . S2

O2 = G . S0 . S1 . S2

O3 = G . S0 . S1 . S2

O4 = G . S0 . S1 . S2

O5 = G . S0 . S1 . S2

O6 = G . S0 . S1 . S2

O7 = G . S0 . S1 . S2

A decoder generates appropriate minterms based on control signals

Example: F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D' + A B C F3 = (A' + B' + C' + D')

The 74138 decodes one-of-eight lines based upon the conditions at the three binary select

inputs and the three enable inputs. Two active low and one active-high enable inputs

reduce the need for external gates or inverters when expanding. A 24-line decoder can be

implemented with no external inverters, and a 32-line decoder requires only one inverter.

An enable input can be used as a data input for demultiplexing applications.


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PIN DIAGRAM:

LOGIC SYMBOL:


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LOGIC DIAGRAM:

FUNCTION TABLE:


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VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity ic74138 is port(a:in std_logic_vector (2 downto 0); en1bar,en2bar,en3:in std_logic; o:out std_logic_vector(7 downto 0)); end ic74138; architecture decoder3x8 of ic74138 is signal enable:std_logic; begin enable <= not(en1bar) and not(en2bar) and en3; process(a,enable) begin if(enable='1') then case a is when "000" => o <= "11111110"; when "001" => o <= "11111101"; when "010" => o <= "11111011"; when "011" => o <= "11110111"; when "100" => o <= "11101111"; when "101" => o <= "11011111"; when "110" => o <= "10111111"; when "111" => o <= "01111111"; when others => o <= "11111111"; end case; else o <= "11111111"; end if; end process; end decoder3x8;


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VHDL CODE: using with select statement. library IEEE; use IEEE.STD_LOGIC_1164.all; entity decoder3-8 is

port( a : in STD_LOGIC_VECTOR(3 downto 1);

d : out STD_LOGIC_VECTOR(7 downto 0) );

End decoder3-8 ;

Architecture decoder3-8 of decoder3-8 is

begin

with a select

d<="00000001" when"000",

"00000010" when"001",

"00000100" when"010",

"00001000" when"011",

"00010000" when"100",

"00100000" when"101",

"01000000" when"110",

"10000000" when"111",

"00000000" when others;

end decoder3-8 ; RESULT:


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WAVEFORMS:

VIVA QUESTIONS:

1. What does priority encoder mean? 2. How many decoders are needed to construct 4X16 decoder? 3. What is the difference between decoder and encoder? 4. Implement 3-8 decoder using case statement. 5. Differentiate between process statement with & with out sensitivity list. 6. Realize a 3-8 decoder using structural model. 7. Design a 4 to 16 decoder-using 74x138. 8. Realize a Behavioral style architecture for a 74x138, 3 – 8 decoder. 9. Write a Behavioral VHDL program for 74x148 like 8- input priority encoder. 10. Realize a data flow style architecture for a 74x138 using 3-8 decoder. 11. Design a 4 to 16 decoder using two 3 to 8 decoders. 12. Design an 8-bit Arithmetic and logic unit using Behavioral style architecture. 13. What are the applications of decoder? 14. What is the difference between decoder & encoder? 15. For n- 2n Decoder how many i/p lines & how many o/p lines? 16. What are the different codes & their applications? 17. What are code converters? 18. What is even parity & odd parity? 19. Which gate can be used as parity generator & checker? 20. Using 3:8 decoder and associated logic, implement a full adder? 21. Implement a full subtract or using IC 74138? 22. What is the difference between decoder and demux?


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BY VIDYA SAGAR.P

8.IC 74x85 – 4-BIT COMPARATOR AIM: To verify the functioning of the IC 74x85 – 4 BIT COMPARATOR using VHDL simulator.

APPARATUS:



THEORY: The 7485 is a 4-bit magnitude comparator that can be expanded to almost

any length. It compares two 4-bit binary, BCD codes and presents the three possible

magnitude results at the outputs. The 4-bit inputs are weighted (A0-A3) and (B0-B3)

where A3 and B3 are the most significant bits. The operation of the 7485 is described in

the function table, showing all possible logic conditions.

Digital Comparators Another common and very useful combinational logic circuit is that of the Digital

Comparator circuit. Digital or Binary Comparators are made up from standard AND,

NOR and NOT gates that compare the digital signals at their input terminals and

produces an output depending upon the condition of the inputs. For example, whether

input A is greater than, smaller than or equal to input B etc.

Digital Comparators can compare a variable or unknown number for example A (A1,

A2, A3, .... An, etc) against that of a constant or known value such as B (B1, B2, B3, ....

Bn, etc) and produce an output depending upon the result. For example, a comparator of

1-bit, (A and B) would produce the following three output conditions.

This is useful if we want to compare two values and produce an output when the

condition is achieved. For example, produce an output from a counter when a certain

count number is reached. Consider the simple 1-bit comparator below.


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1-bit Comparator

Then the operation of a 1-bit digital comparator is given in the following Truth Table.

Truth Table

Inputs Outputs

B A A > B A = B A < B

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

You may notice two distinct features about the comparator from the above truth table. Firstly, the circuit does not distinguish between either two "0" or two "1"'s as an output A = B is produced when they are both equal, either A = B = "0" or A = B = "1". Secondly, the output condition for A = B resembles that of a commonly available logic gate, the

Exclusive-NOR or Ex-NOR gate giving Q = A ⊕ B

Digital comparators actually use Exclusive-NOR gates within their design for comparing the respective pairs of bits in each of the two words with single bit comparators cascaded together to produce Multi-bit comparators so that larger words can be compared.

Magnitude Comparators:

As well as comparing individual bits, multi-bit comparators can be constructed to compare whole binary or BCD words to produce an output if one word is larger, equal to or less than the other. A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit words ("nibbles") are compared to produce the relevant output with one word connected to inputs A and the other to be compared against connected to input B as shown below.


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4-bit Magnitude Comparator

Some commercially available Magnitude Comparators such as the 7485 have additional input terminals that allow more individual comparators to be "cascaded" together to compare words larger than 4-bits with magnitude comparators of "n"-bits being produced. These cascading inputs are connected directly to the corresponding outputs of the previous comparator as shown to compare 8, 16 or even 32-bit words.

8-bit Word Comparator


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Expansion of 4-bit magnitude comparator:


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PIN DIAGRAM:

LOGIC SYMBOL:


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LOGIC DIAGRAM:

TRUTH TABLE: S.No. Cascade

inputs Present input

condition AGTBOUT AEQBOUT ALTBOUT

A>B A=B A<B

1 AGTBIN=1 X X X 1 0 0 2

AEQBIN=1

1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1

5 ALTBIN=1 X X X 0 0 1


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FUNCTION TABLE:






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VHDL CODE: library IEEE; use IEEE.std_logic_1164.all; entity comparater is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); iagb : in STD_LOGIC; ialb : in STD_LOGIC; iaeb : in STD_LOGIC; agb : out STD_LOGIC; alb : out STD_LOGIC; aeb : out STD_LOGIC); end comparater; architecture Behavioral of comparater is begin process(iagb,ialb,iaeb,a,b) begin if(a>b) then agb<='1'; aeb<='0'; alb<='0'; elsif(a<b)then alb<='1'; agb<='0'; aeb<='0'; elsif (a=b) then if(iagb='1')then agb<='1'; alb<='0'; aeb<='0'; elsif(ialb='1')then alb<='1'; agb<='0'; aeb<='0'; elsif(iaeb='1')then agb<='0'; aeb<='1'; alb<='0'; end if; end process; end Behavioral; RESULT:


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BY VIDYA SAGAR.P

WAVEFORMS:

VIVA QUESTIONS:

1. What is Comparator? 2. Write the dataflow model for the IC 74x85. 3. Write the VHDL code for the IC 74x85 using CASE statement. 4. Write the VHDL code for the IC 74x85 using WITH statement. 5. Write the VHDL code for the IC 74x85 using WHEN--ELSE statement. 6. Write the structural program for IC 74x85. 7. How many 4-bit comparators are needed to construct 12-bit comparator? 8. What does a digital comparator mean? 9. Design a 2-bit comparator using gates? 10. Explain the phases of a simulation? 11. Explain briefly about wait statement? 12. What are the applications of Comparator? 13. Which logic is used as 1 bit comparator? 14. What are different arithmetic comparisons? 15. Can we use subtractor & divider as comparators? 16. What is the significance of 74 on IC’s? 17. Design a 5 bit comparator using a single IC 7485, and one gate? 18. Design a 2 bit comparator using a single Logic gates? 19. Design a 8 bit comparator using a two numbers of IC 7485? 20. Design a 24 bit comparator using a six numbers of IC 7485?


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BY VIDYA SAGAR.P

5.8x1 MULTIPLEXER AIM: To verify the functioning of the IC74151—8x1 MULTIPLEXER using VHDL simulator.

APPARATUS:



THEORY: The multiplexers contains full on-chip decoding unit to select desired data source. The

74151 selects one-of-eight data sources. It has a enable input which must be at a LOW

logic level to enable these devices. These perform parallel-to-serial conversion.

The Multiplexer:

Multiplexers which sometimes are simply called "Mux" or "Muxes", are devices that act

like a very fast acting rotary switch. They connect multiple input lines 2, 4, 8, 16 etc one

at a time to a common output line and are used as one method of reducing the number of

logic gates required in a circuit. Multiplexers are individual Analogue Switches as

opposed to the "mechanical" types such as normal conventional switches and relays.

They are usually made from MOSFETs devices encased in a single package and are

controlled using standard logic gates. An example of a Multiplexer is shown below.


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4-to-1 Channel Multiplexer

Addressing Input

Selected b a

0 0 A

0 1 B

1 0 C

1 1 D

The Boolean expression for this 4 to 1 Multiplexer is given as:

Q = abA + abB + abC + abD

In this example at any instant in time only one of the four analogue switches is closed,

connecting only one of the input lines A to D to the single output at Q. As to which

switch is closed depends upon the addressing input code on lines "a" and "b", so for this

example to select input B to the output at Q, the binary input address would need to be

"a" = logic "0" and "b" = logic "1". Adding more control address lines will allow the

multiplexer to control more inputs. Multiplexers can be used to switch either analogue,

digital or video signals, with the switching current in analogue circuits limited to below

10mA to 20mA per channel to reduce heat dissipation.

Multiplexers are not limited to just switching a number of different input lines or

channels to one common single output. There are also types that can switch their inputs to

multiple outputs and have arrangements or 4 to 2, 8 to 3 or even 16 to 4 etc

configurations and an example of a simple Dual channel 4 input multiplexer (4 to 2) is

given below:


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4-to-2 Channel Multiplexer

Here in this example the 4 input channels are switched to 2 individual output lines but

larger arrangements are also possible. This simple 4 to 2 configuration could be used for

example, to switch audio signals for stereo pre-amplifiers or mixers.

Digital multiplexers are sometimes also referred to as "Data Selectors" as they select the

data to be sent to the output line and are commonly used in communications or high

speed network switching circuits such as LAN´s and Ethernet applications. Some

multiplexer IC´s have a single inverting buffer (NOT Gate) connected to the output to

give a positive logic output (logic "1", HIGH) on one terminal and a complimentary

negative logic output (logic "0", LOW) on another different terminal.

It is possible to make simple multiplexer circuits from standard AND and OR gates but

commonly multiplexers/data selectors are available as standard i.c. packages such as the

common TTL 74LS151 8-input to 1 line multiplexer or the TTL 74LS153 Dual 4-input to

1 line multiplexer.

The De-multiplexer

De-multiplexers or "De-muxes", are the exact opposite of the Multiplexers we saw in the

previous tutorial in that they have one single input data line and then switch it to any one

of their individual multiple output lines one at a time. The De-multiplexer converts the

serial data signal at the input to a parallel data at its output lines as shown below.


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1-to-4 Channel De-multiplexer

Addressing Output

Selected b a

0 0 A

0 1 B

1 0 C

1 1 D

The Boolean expression for this De-multiplexer is given as: F = ab A + abB + abC + abD

The function of the De-multiplexer is to switch one common data input line to any one

of the 4 output data lines A to D in our example above. As with the multiplexer the

individual solid state switches are selected by the binary input address code on the output

select pins "a" and "b" and by adding more address line inputs it is possible to switch

more outputs giving a 1-to-2n data lines output. Some standard De-multiplexer IC´s also

have an "enable output" input pin which disables or prevents the input from being passed

to the selected output. Also some have latches built into their outputs to maintain the

output logic level after the address inputs have been changed. However, in standard

decoder type circuits the address input will determine which single data output will have

the same value as the data input with all other data outputs having the value of logic "0".

Standard De-multiplexer IC packages available are the TTL 74LS138 1 to 8-output De-

multiplexer, theTTL 74LS139 Dual 1 to 4-output De-multiplexer or the CMOS CD4514

1 to 16-output De-multiplexer. Another type of De-multiplexer is the 24-pin, 74LS154

which is a 4-bit to 16-line De-multiplexer/decoder. Here the output positions are selected

using the 4-bit binary coded input.


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PIN DIAGRAMS:


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LOGIC SYMBOLS:


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LOGIC DIAGRAM:


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FUNCTION TABLE:

TRUTH TABLE

S.No en_l Data select lines A B C

Output Y

1

0 0 0 0 I(0)

2

0 0 0 1 I(1)

3

0 0 1 0 I(2)

4

0 0 1 1 I(3)

5

0 1 0 0 I(4)

6

0 1 0 1 I(5)

7

0 1 1 0 I(6)

8

0 1 1 1 I(7)

9

1 X X X 0


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VHDL CODE: library ieee; use ieee.std_logic_1164.all; entity ic74151 is port(d:in std_logic_vector (7 downto 0); s,c,b,a:in std_logic; y:buffer std_logic; w:out std_logic); end ic74151; architecture mux8x1 of ic74151 is signal sel:std_logic_vector (2 downto 0); begin sel <= c&b&a; w<=not(y); process(d,sel,s) begin if(s='1') then y <= '0'; else case sel is when "000" => y <= d(0); when "001" => y <= d(1); when "010" => y <= d(2); when "011" => y <= d(3); when "100" => y <= d(4); when "101" => y <= d(5); when "110" => y <= d(6); when "111" => y <= d(7); when others => y <= '0'; end case; end if; end process; end mux8x1; RESULT:


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BY VIDYA SAGAR.P

WAVEFORMS:

VIVA QUESTIONS:

1. What is meant by multiplexer? 2. What does demultiplexer mean? 3. How many 8X1 multiplexers are needed to construct 16X1 multiplexer? 4. Compare decoder with demultiplexer? 5. Design a full adder using 8X1 multiplexer? 6. What are the two kinds of subprograms? 7. What are the difference between function and procedure? 8. What are the applications of multiplexer? 9. What is the difference between multiplexer & demultiplexer? 10. In 2n to 1 multiplexer how many selection lines are there? 11. How to get higher order multiplexers? 12. Implement full subtractor using demux?. 13. Implement a 8:1 mux using 4:1 muxes?. 14. Design full adder using 8:1 Mux Ics?. 15. Design a BCD-to- gray code connecter using 8:1 muxes? 16. Draw and explain the design of a32:1 mux using 8:1 MUX and 4:1 MUX.? 17. Use if statement only and realize the logic. 18. Write the structural program for IC 74x151. 19. Realize behavioral VHDL program for a 4- input, 8 bit multiplexer. 20. Realize behavioral VHDL program for specialized 4- bit, 3-bit multiplexer. 21. Realize behavioral VHDL program for a 9- input parity checker. 22. Write a Behavioral VHDL program for Hamming error correction.


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BY VIDYA SAGAR.P

6.IC 74X89—READ AND WRITE OPERATIONS OF RAM AIM: To verify the functioning of the IC 74X89— RAM (16X4) using VHDL simulator.

APPARATUS:



THEORY: Programs and data in computers are held in the main memory. These main

memories are called RAM (Random Access Memory). RAM are essential parts in

computer systems. A RAM consists of a large number of storage cells. Each cell can

hold only one bit of information, either logic 0 or logic 1. Storage cells are organized into

groups, words, of fixed size. Each word occupies one location in the RAM. The word in

this location can be read or written in a single operation. Each location has its unique

address that can be used to read from or write to this location. The word size specifies

the size of the data bus. The maximum accessible number of RAM locations is specified

by the address bus.

In this exercise we will examine the general issues involved in implementing such

memory. A diagram of the random access memory (RAM) module that we will

implement is shown in Figure It contains 16 four-bit words (rows), which are accessed

using a four-bit address port, an four-bit data port, and a write control input. We will

consider two different ways of implementing this memory: using dedicated memory

blocks in an FPGA device, and using a separate memory chip.A common term used to

specify the size of a memory is its aspect ratio, which gives the depth in words and the

width in bits (depth x width. Given these requirements, we will implement the modified

16 x 4 RAM module shown in Figure . It includes registers for the address, data input,

and write ports, and uses a separate unregistered data output port.


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A memory unit stores binary information in groups of bits called words. A word in

memory is an entity of bits that move in and out of storage as a unit. The communication

between a memory and its environment is achieved through data input and output lines,

address selection lines, and control lines that specify the direction of transfer. A block

diagram of IC 7489 16 x 4 RAM is shown below. The 4 address inputs select one of 16

words in the memory. The least significant bit of the address is A0 and the most

significant is A3. The chip select (CS) input must be equal to 0 to enable the memory. If

CS is equal to 1, the memory is disabled and all four outputs are in a high impedance

state. The write enable (WE) input determines the type of operation as indicated in the

function table. The write operation is performed when WE = 0. This is the transfer of the

binary number from the data inputs into the selected word in memory. The read

operation is performed when WE = 1. This transfers the complement value stored in the

selected word into the output data lines. The memory has three-state outputs to facilitate

memory expansion.

ROM Simulator

A ROM simulator is obtained from a RAM when operated in the read mode only. The

pattern of 1’s and 0’s is first entered into the simulating RAM by placing the unit

momentarily in the write mode. Simulation is achieved by placing the unit in the read

mode and taking the address lines as inputs for the ROM. The ROM can then be used to

implement any combinational circuit.


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SRAM READ CYCLE

SRAM WRITE CYCLE


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Operation:- • RAM IC 7489 is 16 words x 4-bit Read/WriteMemory.

• The Truth Table for the RAM IC 7489 is given below.

• The memory Enable pin is used to select 1- of-n ICs i.e. like a Chip Select

signal.

For simply city, the memory enable pin is permanently held low.

• The address lines are given through an up /down counter with preset capability.

• The set address switch is held high to allow the user choose any location in the

RAM, using the address bits.

• The address and data bits are used to set an address and enter the data.

• The ‘ Read/Write ‘ switch is used to write data on to the RAM.


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Clearing the Memory: -The RAM IC 7489 is a volatile memory. This means that it

will lose the data stored in it, on loss of power. However, this dose not means that the

content of the memory becomes 0h, but not always. The RAM IC 7489 does not come

with a ‘ Clear Memory ‘ signal. The memory has to be cleared manually.

1. Position the ‘ Stack/Queue’ switch in the ‘ Queue’ position.

2. Position the ‘Set Address’ switch in the ‘1’ position.

3. Set the address bits to 0h (first byte in the memory)

4. Position the ‘Set Address’ switch in the ‘0’ position to disable random access and

enable the counter.

5. Position the ’ Read/Write ‘ switch in the ’ Write ’ position to write data on to the

memory.

6. Set the data bits to 0h (clearing the content)

7. Observe that the LEDs (D3 to D0) glow. This is to indicate that the content is 0h.

Refer the truth table above and observe that the data outputs of the RAM will be

compliments of the data inputs.

8. Position the ‘ Increment/Decrement ‘ switch in the ‘Increment’ position.

9. Press the ‘Clock’ to increment the counter to the next address. As the ‘Read /Write ‘

switch is already in the ‘Write’ position, and the data bits are set to the 0h, the content in

the new location is also replaced with 0h.

10. Repeat step 8 until the data in all the memory locations have been cleared.

Write Operation: -

1. Assume that the following data has to be written on to the RAM. The address and

data are given in the hexadecimal format.

2. Position the ‘Stack/Queue’ switch in the ‘ Queue’position.

3. Position the ’ Read/Write ‘ switch in the ’ Write ’ position to enable the entry of

data in to the RAM.


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4. Position the ‘Set Address’ switch in the ‘1’ position to allow random access of

memory.

5. Set the desired address (any address at random) using the address bit switches.

6. Set the desired data (refer table for the data to be entered in each location) using the

data bit switches.

7. Observe that the data is indicated by the LEDs (D3 toD0). This is because the data is

written on to the RAM.

8. Also observe that the data is indicated by the data outputs is the compliment of the

data input (refer truth table condition ME =L and WE=L) .

9. After each data entry, make a note of the location where data is entered. This is to

make sure that we are not re –entering data in the same location.

10. Repeat steps 4 and 5 until data has been entered in all the addresses listed in the

above table

11. Position the ’ Read/Write ‘ switch in the ’ Read’ position, to disable data entry.

12. This completes data entry.


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Read Operation: - 1. Position the ‘Stack/Queue’ switch in the ‘Queue’ position.

2. Position the ‘Set Address’ switch in the ‘0’ position to allow random access of

Memory.

3. Position Read/Write ‘ switch in the ’ Read’ position, to disable unauthorized entry of

data.

4. Set the desired address (any address at random).

5. Observe that the data entered in the location is indicated by the LEDs (D3 toD0). This

is because the data was written during the data entry procedure.

6. Also observe that the data indicated by the data out puts is the compliment of the data

input (refer truth table condition ME=L and WE=H).

PIN DIAGRAM:


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LOGIC SYMBOL:

LOGIC DIAGRAM:


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TRUTH TABLE:

Memory Enable

RW Operation Output

0 0 1

0 1 X

Write Read the complemented data Inhibit

Logical “1” state complement of data stored in memory logical “1” state.

VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.all; entity ram1 is

port( rw : in STD_LOGIC;

clk : in STD_LOGIC;

addr : in STD_LOGIC_vector( 3 downto 0);

datain : in STD_LOGIC_vector(3downto 0);

dataout : out STD_LOGIC_vector(3 downto 0) );

end ram1;

architecture ram1 of ram1 is

type mem_type is array(15 downto 0)of std_logic_vector(3downto 0); signal memory:mem_type; begin

process (clk,rw)

begin

if (clk='1' and clk'event)then

if rw ='1' then -- write mode

memory (conv_integer(addr)) <= datain;

else dataout <=memory(conv_integer(addr));--read mode

end if;

end if;

end process;

end ram1;


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RESULT:

WAVEFORMS:

VIVA QUESTIONS:

1. What is the RAM? . 2. Give the applications of the RAM? . 3. What is the difference between RAM &ROM? . 4. What is the difference between static RAM &dynamic RAM? 5. Which can be used as 1-bit memory? 6. What are the different types of the ROM? . 7. What are the parameters of the RAM? 8. What are sequential access memories? 9. What are charge-coupled devices? 10. Write the behavioral code for IC 74x189 without declaring the function. 11. Explain about different types of RAMs? 12. How to specify the memory size? 13. Explain read and write operations? 14. Why configurations are needed? 15. What is binding? 16. State the purpose of unsigned IEEE library. 17. List out the different types of ROM. 18. What is sequential access memory? 19. Design 1Kx8 RAM using two 2114Ics. 20. What is a Flash memory and Non-Volatile RAM? .


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BY VIDYA SAGAR.P

1.OP AMP APPLICATIONS – ADDER, SUBTRACTOR,

COMPARATOR CIRCUITS.

AIM: To Study the Adder, Sub tractor and Comparator circuits using IC 741.

APPARATUS:

1. CRO (Dual trace) - 1 No

2. Signal Generator - 1 No

3. Bread Board - 1 No.

4. dual channel power supply- 1 No 0 to 20 volts peak to peak

independently.

Components: 1. IC 741 2.Resistors

1. OP- AMP as ADDER

Let V1 and V2 are two inputs applied to the inverting terminal of op-amp through R1and R2 resistors as shown in fig.1. A feed back resistor Rf is connected between o/p and inverting i/p. Then the o/p will be the summation of i/p voltages. Considering an ideal op-amp so that Aol= α Ri= α thus no current into op-amp.

At node A

1

2

3

V1

1 K

741 OP-AMP

Vo6

3

1 K

1 K

V2

FIG 1. OP-AMP ADDER


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PROCEDURE:

1. Apply a sine wave of 1 V peak to peak at input 1 with 1kHz frequency

v1= V1sint from function generator1.

2. Apply a sine wave of 2 V peak to peak at input 2 with 1 KHz frequency

V2 = V2 sint from function generator2.

3. Connect one channel of the C.R.O to function generator1 and display this

signal on the C.R.O.

4. Check the output on C.R.O. it is the addition of two input signals and

amplitude will be of 3 V peak to peak with same frequency.

5. Draw the relevant waveforms.

6. Now apply a square wave of 1v(p-p) at input 1 with 1kHz frequency from

function generator1 as input 1 and apply a triangular wave of 1 Vpp at

input 2 with 1 KHz frequency from function generator 2.

7. Check the output on C.R.O. it is the addition of two input signals and

amplitude will be of 3 V p-p with same frequency.


2,OP- AMP as SUBTRACTOR

Let V1 and V2 are two inputs applied to the inverting terminal and Non –

inverting terminals of op-amp through R1and R2 resistors as shown in fig.2. A

feed back resistor Rf is connected between o/p and inverting i/p. Then the o/p

will be the difference of two i/p voltages.

VO = V1 – V2


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PROCEDURE:

1. Apply a sine wave of 1V peak to peak at input 1 with 1kHz frequency v1=

V1sint from function generator1.

2. Apply a sine wave of 2 V peak to peak at input 2 with 1 KHz frequency

v2= V2 sint from function generator.

3. Connect one channel of the scope to function generator1 and display this


4. Check the output on C.R.O. it is the difference of two input signals and

amplitude will be of 1 V p-p with same frequency.


6. Now apply a square wave of 2 V peak to peak at input 1 with 1kHz

frequency from function generator1 as input 1 and apply a triangular wave

of 1 V peak to peak at input 2 with 1 KHz frequency from function

generator 2.

7. Check the output on C.R.O. it is the difference of two input signals and

amplitude will be of 1 V peak to peak with same frequency.


1

2

3

V1

1 K

741 OP-AMP

Vo6

3

1 K

1 K

1 K

V2

FIG 2. OP-AMP SUBTRACTOR


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3.OP- AMP AS COMPARATOR Comparator is a non-linear application of in open loop configuration. A

Comparator circuit compares the input signal voltage with a reference voltage at

the terminals of an open loop op amp. An inverting comparator circuit shown in

fig 3 with input voltage applied to inverting terminal and Vref to non- inverting

input terminal.The output voltage will be Vsat (= Vcc) and its transfer

characteristics as shown in fig.4. The transfer characteristics for a practical

comparator is shown.

When Vi < Vref ; Vo= +Vsat

When Vi>Vref ; Vo= -V sat

When Vi < - Vref

Vo = +Vsat

Vi > - Vref

Vo = - Vsat

1

2

3

Vi

- 12 Vref

1 K- ohm

Vz

Vo6

3

- Vee

+ Vcc

50%

1 K- ohm

10 MicroF

FIG 2. OP-AMP COMPARATOR


IC&E-CAD LAB


BY VIDYA SAGAR.P

Vo

Vi

Vm

t

t

FIG 4. TRANSFER CHARACTERISTICS OF IDEAL OP-AMP COMPARATOR

+ Vsat

- Vsat

Vi - Vref

+ Vref

- Vsat

Vi - Vref

Vi < Vref

+ Vsat

- Vsat

Vi - Vref

Vi > Vref


IC&E-CAD LAB


BY VIDYA SAGAR.P

PROCEDURE:

1. Set the reference voltage as 5 V peak to peak.

2. Apply a sine wave of 1V peak to peak at input 1 with 1kHz frequency from

function generator1.

3. Connect one channel of the C.R.O to function generator1 and display this


4. Check the output on C.R.O. It is the difference signal between input signal

and reference signal, this causes the output voltage to saturate either + V sat

or – V sat.

5. Now connect the Non- inverting terminal; to ground i.e., Vr = 0.

6. Apply a sine / Triangular / square wave of 1V peak to peak at input 1 with

1kHz frequency from function generator1.

7. The output of Comparator will swings to either + V sat or – V sat when ever

the input signal crosses the zero voltage. This is a Zero crossing detector.

8. Check the output on C.R.O.

9. Plot the waveforms on graph sheet.

PRECAUTIONS:

1. Always use a straight lead probe to insert into the breadboard.

2. Apply proper grounding for IC’s.

3. Check the starting pin number for each IC indicated with a dot as starting

pin.

4. Use IC remover to remove IC from breadboard to avoid damage of pins.

5. Don’t touch the pins of IC’s while power on.

6. Don’t bend the pins of IC’s.

7. Insert the components into the breadboard firmly.

8. Loose contact may result in error at output.


IC&E-CAD LAB


BY VIDYA SAGAR.P

RESULT:

Succesfully constructed Adder, Subtractor and comparator circuits using

OP-AMP IC 741.


IC&E-CAD LAB


BY VIDYA SAGAR.P

2.ACTIVE FILTERS EXPERIMENT NO 1 : LOW PASS FILTER AIM: To Design a Low pass, first order Butterworth Filter with a cut-off frequency

of fH=1.0 kHz and pass band gain of 5.

APPARATUS 1. CRO (Dual trace) - 1 No



4. dual channel power supply- 1 No

0 to 20 volts peak to peak independently.

THEORY: A frequency selective electric circuit that passes electric signals of specified

band of frequencies and attenuates the signals of frequencies outside the brand

is called an electric filter. The first order low pass filter consists of a single RC

network connected to the non-inverting input terminal of the operational

amplifier. Resisters R1 and RF determine the gain of the filter in the pass band.

The low pass filter as maximum gain at f = 0Hz. The frequency range from 0

to FH is called the pass band the frequency range f > fh is called the stop band.

An Op-Amp Low pass filter is shown in fig. The circuit allows the low

frequency signals freely through it and attenuates the signals above a cut off

frequency called Higher cut off frequency( fH). The inverting terminal is

grounded through a resistor Ri. A resistor Rf is connected in feedback path.


IC&E-CAD LAB


BY VIDYA SAGAR.P

1

Vo = A jωC R + 1

A Resistor R is connected between the input signal source and the inverting

terminal of the Op-Amp and a Capacitor C is connected between the inverting

terminal and ground.

Let Vi = input voltage

Vg = the voltage at the Non-inverting input

Vo = output voltage.

A = Gain of the Op-Amp = 1+Rf /Ri

Xc = Capacitive Reactance = 1/jωC

But Vo = AVg

But ω = 2Π f

Where fH is the Higher cut off frequency of the Low pass filter = 1/2 Π RC.

Xc

Vg = Vi

R + Xc 1/jωC

Vg = R + 1/jωC

1/jωC

Vo = [1+Rf /Ri ] R + 1/jωC

1/jωC

Vo = A R + 1/jωC

1

Vo = A j2Π f C R + 1 A

Vo =

1 + jf / 2Π Rc

A

Vo =

1 + Jf / fH


IC&E-CAD LAB


BY VIDYA SAGAR.P

Transfer function of Low pass filter is given as H (s) = Vo / Vi

CIRCUIT DIAGRAM:

Vo1

2

36

3

741 OP-AMP

ViC=0.01 Micro F

Rf

Ri

R=

A

H (s) =

1 + j f / fH

A

│H (s) │ =

1 + j f / fH

Magnitude is given by │H (s) │ =20 log A

√1 +{f / fH}2


IC&E-CAD LAB


BY VIDYA SAGAR.P

PROCEDURE: 1. Insert the Op-Amp IC 741 into the breadboard correctly.

2. Connect the power supply to the pin 7 with a positive voltage of 15 V and

ground the other.

3. Connect the 2nd power supply negative voltage of 15 V to the pin 4 and

ground the positive terminal.

4. and a Capacitor C is connected between the inverting terminal and ground.

5. The inverting terminal pin 2 is grounded through a resistor Ri.

6. A resistor Rf is connected in feedback path between the pin 2 and 6.

7. A Resistor R is connected between the input signal source ( Function

generator) and the inverting terminal pin 2 of the Op-Amp

8. A Capacitor C is connected between pin 2 and other end 3 is grounded.

9. Take output at pin6.

10. Apply a sine wave of any frequency between 0 to 2 K Hz from function

generator.

11. Observe the output waveform of Low pass filter on CRO.

12. Increase the frequency from 1 Hz to 200 K Hz in steps as shown in table

and note down the output waveform amplitude and tabulate these values.

13. From the above tabulated values, draw graph between frequency and output

voltage.

14. From the graph it is observed that Higher cut off frequency f H is between

11 KHz to 12 K Hz.

15. Compare the observed Higher cutoff frequency from graph with the

theoretical Higher cut off frequency.


IC&E-CAD LAB


BY VIDYA SAGAR.P

OBSERVATIONS:

CALCULATIONS: i. Choose a standard value of Capacitor C say 0.1 μF.

Then R= fC2

1 =

63 101.01012

1xxxx

= 1.6kΩ

ii. Ao=1+1R

RF=5

Rf=4R1 Choose a value of 10kΩ for R1

Then Rf=40 kΩ

GRAPH:

Sl.No Input frequency Output voltage Gain 20 log Vo/Vi 1. 100 2 200 3 500 4. 1kHz 5. 1.5KHz 6. 2.0kHz 7. 5kHz


IC&E-CAD LAB


BY VIDYA SAGAR.P

RESULT: i. The cut-off frequency of the low pass filter = kHz

ii.The pass band gain of low pass filter =

INFERENCE: i. The working of active low pass filter is observed and the output is plotted.

ii. The frequency response of the low pass filter is plotted on a semi-log graph

paper.

iii. It is observed that the gain rolls of at the rate of 20dB per decade at the cut

of frequency.

REVIEW QUESTIONS:

i.Define an electric filter.

ii.Classify filters

iii.Discuss the disadvantages of passive filters

iv.Why are active filters preferred?

v.List the commonly used filters.

vi.Define pass band and stop band of a filter.

vii.What is roll-off rate of a first order filter?

viii.Why do we use higher order filters?

ix.On what does the damping coefficient of a filter depend?

x.What is sallen key filter?


IC&E-CAD LAB


BY VIDYA SAGAR.P

EXPERIMENT NO 2 : HIGH PASS FILTER AIM: To Design a Low pass, first order Butterworth Filter with a cut-off frequency

of fL=1.0 kHz and pass band gain of 5.

EQUIPMENTS AND COMPONENTS:

APPARATUS

1. CRO (Dual channel) - 1 No



4. Dual channel power supply –1 No

THEORY: A frequency selective electric circuit that passes electric signals of specified

band of frequencies and attenuates the signals of frequencies outside the brand

is called an electric filter. The first order high pass filter consists of a single RC

network connected to the non-inverting input terminal of the operational

amplifier. Resisters R1 and RF determine the gain of the filter in the pass band.

The high pass filter has maximum gain at f = fl Hz. The frequency range from

0 to Fl is called the stop band the frequency range f > fl is called the pass band.

An Op-Amp High pass filter is shown in fig 2. The circuit allows the high

frequency signals freely through it and attenuates the signals below a cut off

frequency called Lower cut off frequency (fL). The inverting terminal is

grounded through a resistor Ri. A resistor Rf is connected in feedback path.


IC&E-CAD LAB


BY VIDYA SAGAR.P

A Capacitor C is connected between the input signal source and the inverting

terminal of the Op-Amp and a Resistor R is connected between the inverting

terminal and ground.

Let Vi = Input voltage

Vg = Voltage at the Non-inverting input

Vo = output voltage.

A = Gain of the Op-Amp

Where fL is the Lower cut off frequency of the High pass filter = 1/2 Π RC.

R

Vg = Vi

R + Xc

R

Vo = A R + 1/jωC

1

Vo = A 1 + 1/jωRC

1

Vo = A

1 + 1/j2Π f RC

A

Vo =

1 – j fL / f


IC&E-CAD LAB


BY VIDYA SAGAR.P

Transfer function of High pass filter is given as H (s) = Vo / Vi

CIRCUIT DIAGRAM:

Vo1

2

36

3

741 OP-AMP

Vi

C=0.01 Micro F

Rf

Ri

R

A

H (s) =

1 – j fL / f

A

│H (s) │ =

1 – j fL / f

Magnitude is given by │H (s) │ =20 log A

√1 +{fL / f}2


IC&E-CAD LAB


BY VIDYA SAGAR.P

PROCEDURE:

1. Insert the Op-Amp IC 741 into the breadboard correctly.

2. Connect the power supply to the pin 7 with a positive voltage of 15 V

and ground the other.

3. Connect the 2nd power supply negative voltage of 15 V to the pin 4 and

ground the positive terminal.

4. The inverting terminal pin 2 is grounded through a resistor Ri.

5. A resistor Rf is connected in feedback path between the pin 2 and 6.

6. A Capacitor C is connected between the input signal source ( Function

generator) and the inverting terminal pin 2 of the Op-Amp

7. A Resistor R is connected between pin 2 and other end is grounded.

8. Take output at pin6.

9. Apply a sine wave of any frequency between 5 to 10 K Hz from

function generator.

10. Observe the output waveform of High pass filter on CRO.

11. Decrease the frequency from 10 KHz to 1 K Hz in steps of 1 KHz as

shown in table and note down the output waveform amplitude and

tabulate these values.

12. From the above tabulated values, draw graph between frequency and

output voltage.

13. From the graph it is observed that lower cut off frequency f L is between

1 KHz to 2 K Hz.

14. Compare the observed lower cutoff frequency from graph with the

theoretical lower cut off frequency.


IC&E-CAD LAB


BY VIDYA SAGAR.P

OBSERVATIONS:

CALCULATIONS: i. Choose a standard value of Capacitor C say 0.1 μF.

Then R= fC2

1 =

63 101.01012

1xxxx

= 1.6kΩ

ii.Ao=1+1R

RF=5

Rf=4R1 Choose a value of 10kΩ for R1 Then Rf = 40 kΩ GRAPH:

Sl.No Input frequency Output voltage Gain 20 log Vo/Vi 1. 100 2 200 3 500 4. 1kHz 5. 1.5KHz 6. 2.0kHz 7. 5kHz


IC&E-CAD LAB


BY VIDYA SAGAR.P

RESULT: The lower cutoff frequency of the high-pass filter = ------- KHz.

The pass band gain = -------

INFERENCE: i. The working of active high pass filter is observed and the output is plotted.

ii. The frequency response of the high pass filter is plotted on a semi-log graph

paper.

iii. It is observed that the gain increases at the rate of 20dB per decade at the

cut of frequency.

REVIEW QUESTIONS i.Define Bessel , Butterworth and Chebyshev filters, and compare their

response.

ii.What are the important parameters of a band pass filter?

iii.Define Notch filter.

iv.How do we get a notch filter from a band pass filter?

v.Define state variable filter.

vi.What is switched capacitor ?

vii.Discuss the importance of switched capacitors.

viii.Give the circuit of a switched capacitor low pass filter

ix.Discuss the advantages of active filters

x.What is the roll-off rate of second order filter?


IC&E-CAD LAB


BY VIDYA SAGAR.P

3. FUNCTION GENERATOR USING OP AMPS.

AIM: Study the Function generator circuit and generating square and triangular

waveforms using IC-741 Op- Amp.

APPARATUS REQUIRED: Components: 1. IC 741 Op-Amp --- 2 nos.

2. Capacitors ----- 0.01 μF, 0.1 μF

3. Resistors ------ 68 KΩ & 100 KΩ---3 nos.

Equipment: 1. CRO

2. Bread board.

3. Power supply.

THEORY:

A Function generator is a circuit that provides Square wave and a

Triangular wave output signal.

Square wave generator:

A constant amplitude squarewave generator using IC 741 Op-Amp is shown in

Fig. The inverting terminal is grounded through a capacitor. A resistor is

connected in feed back path. A potentiometer is connected between output and

ground. The inverting terminal is connected between the potentiometer circuit as

shown.


IC&E-CAD LAB


BY VIDYA SAGAR.P

1

2

3

OP-AMP 741

C

100nF

R1

100kohm

A BT

G

XSC1

R2 100kohm

R3 68kohm

When ever power is applied to this circuit Op-Amp is forced to operate in

saturation region. The output of Op-Amp is forced to swing respectively between

positive saturation and negative saturation (-VEE). The output of Op-Amp is a

square wave. It is also known as Astable multivibrator.

Triangular waveform Generator: The Triangular waveform generator can be constructed using two Op-Amps as

shown in fig, here the first Op-Amp acts as an Astable multivibrator that produces

a square wave output. The second Op-Amp is an integrator, which converts the

square wave into a triangular waveform. The output of Op-Amp is connected to

the inverting terminal of the 2nd Op-amp through a resistor (100 KΩ). The

noninverting terminal is grounded. A capacitor C=0.1μF is connected in feed back

path as shown. The square wave input charges and discharges the capacitor.

6

3


IC&E-CAD LAB


BY VIDYA SAGAR.P

1

2

3

OP-AMP 741

C

100nF

R1

100kohm

R2 100kohm

R3 68kohm

1

2

3

OP-AMP 741

R

100kohm

C2

100nF

A BT

G

XSC2

When the negative half cycle or squire is applied to non-inverting

terminal, the output of op-amp-2 starts rising linearly at the rate of I/C V/sec. Here

‘I’ is current determined by input resistor (100 KΩ). As a consequence the bias

voltage at positive input of op-amp 1 also rises and when it crosses the zero volt

level the output of OP-Amp-1 rises to fully positive value (i.e. During positive half

cycle). Now the capacitor starts discharging at the same rate linearly till the

positive voltage crosses zero level. The cycle repeats continuously. The amplitude

of triangular waveform depends on the ratio of 68 K and 100 KΩ.

MODEL WAVEFORMS:

Vo1

t

t

Vo2


IC&E-CAD LAB


BY VIDYA SAGAR.P

PROCEDURE:

1. Connect the circuit as shown in the fig to generate a square wave.

2. Connect the CRO probe between output terminal and ground of OP-AMP

1.

3. Observe the waveform on CRO, which is a square wave.

4. Now connect the circuit at the output of OP-AMP1 to generate the

Triangular waveform.

5. Connect the CRO probe between output terminal of OP-AMP 2 and

ground.

6. Observe the waveform on CRO, which is a Triangular wave.

7. Plot the waveforms on graph sheets and calculate the time period and

frequency of the waveforms theoretically and practically.

RESULT:

The Square and Triangular waveforms are generated and calculated their

frequencies and amplitudes.


IC&E-CAD LAB


BY VIDYA SAGAR.P

4. MULTI-VIBRATORS

EXPERIMENT NO 1: 555 TIMER-ASTABLE MULTI-VIBRATOR

AIM: To design and test astable multi-vibrator with fixed and adjustable duty cycle.

EQUIPMENTS AND COMPONENTS: APPARATUS 1. DC power supply - 1 No.

2. CRO - 1 No.


COMPONENTS: 1. 3.62 kΩ Resistor – 1 No.

2. 7kΩ Resistor – 1 No.

3. 0.1 F Capacitor – 1 No

3. IC555 - 1 No.

4. Diode – 1 No.

THEORY: IC 555 Timer

IC-555 Timer is a versatile Monolithic timing circuit that can produce accurate

and highly stable time delays or oscillations. It can be used as an Astable and

Monostable multivibrators. It is available as an 8- pin mini DIP-package.

IC Timer 555 as a Monostable Multivibrator

Monostable Multivibrator has only one stable state. We can change the stable

state by applying a trigger pulse. The capacitor charges through R. The larger

the time constant RC, the longer it takes the capacitor voltage to reach 1/3 VCC.


IC&E-CAD LAB


BY VIDYA SAGAR.P

The time constant controls the pulse width. After the time period given by R

and C elements the circuit goes back to its stable state. Even the trigger pulse is

removed in between still the circuit will not comeback to its stable state until

its time period is reached..

CIRCUIT DIAGRAM:

Ra = 560 Ohm

0.1 Micro F

Rb = 100 K Ohm

0.1 Micro F

555

A BT

G

+ Vcc = 15 V

CRO

2

6

7

8

4

3

5

1

TriggerInput


IC&E-CAD LAB


BY VIDYA SAGAR.P

PROCEDURE: 1. 1. The pulse width design equation is T=1.1RC sec. If T = 0.1msec, choose

R=10kΩ and C=0.01μF.

2. Keep the connections as shown in figure-1.

3. A trigger circuit consisting of a differentiator and a diode connected as

shown.

4. A square wave input is applied to this circuit from astable multivibrator

whose output is spikes and the diode will remove the positive spikes.

5. The output of the trigger circuit is applied at the trigger input of the

monostable multivibrator at pin 2.

6. The input and output waveforms are observed on the CRO.

7. The control pin-5 input is grounded through a capacitor 0.01 μF, this

provides noise filtering for control voltage.

8. The time period of input square waveform have to be verified from the

input waveform.

9. Observe the output waveform on the CRO and measure the pulse width T

on the CRO and compare with the theoretical value.

10. Observe the output waveform across the capacitor for both Astable and

Monostable operations and note down the corresponding amplitudes.

OBSERVATIONS: 1.tON = 69 (RA + RB) C 2.tOFF = 0.69 RBC

3. 100% xtt

tDutycycle

OFFON

ON


IC&E-CAD LAB


BY VIDYA SAGAR.P

CALCULATIONS: i. Design of astable multi-vibrator of 1 kHz with a 75% duty cycle

tON = 69 (RA + RB) C

tOFF = 0.69 RBC

100100% xT

tx

tt

tDutycycle ON

OFFON

ON

Where T = 1/f, the time period of the output waveform

T= 1msec, tON = 0.75 m/sec, tOFF 0.25msec

Lec C = 0.1 F

RB = 3.62 k

Choose RB = 1.8 k + 1.8 k

cRRTf

BA )2(

45.11

Eq. (1)

ii. Design of astable multivibrator to produce 1 KHz output waveform with

adjustable duty cycle of 10% to 90% The circuit is as shown in Fig. 2 During

the charging period, the diode ‘D’ is forward biased, RB is bypassed Hence ton

= 0.69 RAC. During the discharge period, the discharging transistor is shorted

(ON) and the diode ‘D’ is reverse biased. Hence tOFF = 0.69RB C Output

frequency f= 1 KHz is assumed

cRRTf

BA )(

45.11

Eq. (2)

Let C = 0.1 F

RA + RB = 14.5 K Where tON= 0.1 m/sec (for 10% duty cycle)

RA= 1.44 K When tON = 0.9 m/sec (for 90% duty cycle)

RA = 12.96 K RA is to be varied form 1.414 K to 12.96K for 10% to

90% duty cycle. Therefore choose RA as 1.0 K fixed resistor + 15.0k pot,

similarly RB


IC&E-CAD LAB


BY VIDYA SAGAR.P

Vi

t

t

Vd

t

Vo

t

Vc

GRAPH:

Vi Input square wave

Vd Differentiator output

VC Discharge capacitor output

VO Output pulse


IC&E-CAD LAB


BY VIDYA SAGAR.P

RESULT: tON = 69 (RA + RB) C = tOFF = 0.69 RBC =

100100% xT

tx

tt

tDutycycle ON

OFFON

ON

=

INFERENCE:

i. The working of 555 timer astable multivibrator is observed and the output is

plotted.

ii. The duty cycle is calculated

iii. Frequency of the output wave form is calculated

REVIEW QUESTIONS i.Explain the functional block diagram of a 555 timer

ii.Explain the function of reset

iii.What are the modes of operation of timer?

iv.What is the expression of time delay of a astable multivibrator?

v.Discuss some applications of timer in astable mode.

vi.Define duty cycle

vii.Give methods of obtaining symmetrical waveform.

viii.How is an astable multivibrator connected into a pulse position modulator

ix.How Schmitt trigger circuit is constructed using 555 timer

x.Draw the pin diagram of 555 timer.


IC&E-CAD LAB


BY VIDYA SAGAR.P

EXPMENT NO 2: 555 TIMER-MONOSTABLE MULTI-VIBRATOR AIM: To design and test monostable multi-vibrator using IC555 Timer. EQUIPMENTS AND COMPONENTS: APPARATUS 1. DC power supply - 1 No.

2. CRO - 1 No.


4. Function Generator - 1 No.


2. 1kΩ Resistor – 1 No.

3. 1 F Capacitor – 1 No

4. 1 F Capacitor – 1 No

5. IC555 - 1 No.

6. 1N4148 Diode – 1 No.

THEORY: The 555 timer can be used with supply voltage in the range of +5 v to +18 v

and can drive upto 200 mAmps. It is compatible with both TTL and CMOS

logic circuits because of the wide range of supply voltage the 555 timer is

versatile and easy to use in monostable multivibrator we will provide external

triggering in order to make the timer to switch over to high state (unstable).

This is also called as one-short multivibrator.


IC&E-CAD LAB


BY VIDYA SAGAR.P

CIRCUIT DIAGRAM:

PROCEDURE: 1. Connect the circuit using the component values as per the design

2. Set the square wave 2.5V peak and 1KHz trigger input on function

generator

3. Apply the trigger input at pin-2 through capacitor C1. Observe both trigger

input and the output of the multivibrator on CRO simultaneously and

sketch the waveforms

4. Repeat the step 3 for trigger input of 2KHz frequency

OBSERVATIONS: 1 TP = 1.1 R.C. = 1.3 m/sec

2. T = 1/ f = 1m/sec


IC&E-CAD LAB


BY VIDYA SAGAR.P

CALCULATIONS: i. To produce a pulse of 1.3 m/sec duration:

TP = 1.3mSec

TP = 1.1 R.C.

Let C = 0.1 F

R = 11.8K

To provide negative edge triggering a circuit of fig.2 is to be connected

between pin 2 and 8.

Design of Differentiator:

Let the trigger input frequency is 1KHz

i.e., T = 1/f = 1mSec

Assume 1 = R1 C1 = 0.01mSec

Let C = 0.01 F

Therefore R1 = 1.0 K

GRAPH:

RESULT: Tp = 1.1R.C. =


IC&E-CAD LAB


BY VIDYA SAGAR.P

INFERENCE: i. The working of 555 timer monostable multivibrator is observed and the

output is plotted.

ii. The time period of the output waveform is calculated


REVIEW QUESTIONS i. Explain the functional block diagram of a 555 timer

ii. Explain the function of reset

iii. What are the modes of operation of timer?

iv. What is the expression of time delay of a monostable multivibrator?

v. Discuss some applications of timer in monostable mode.

vi. Define duty cycle

vii. Give methods of obtaining symmetrical waveform.

viii.How is an monostable multivibrator connected into a pulse position

modulator

ix. How Schmitt trigger circuit is constructed using 555 timer

x. Draw the pin diagram of 555 timer.


IC&E-CAD LAB


BY VIDYA SAGAR.P

5. IC566 VCO

AIM: To study the operation of NE566 VCO APPARATUS 1. DC power supply - 1 No.

2. CRO - 1 No.




2. 15 kΩ Resistor – 1 No.

3. 100 kΩ Resistor – 1 No.

4. 75 pF Capacitor – 1 No

5. IC566 - 1 No.

. THEORY: A common type of VCO available in IC form in Stigmatic NE/SE566.

Referring to the circuit diagram a timing capacitor CT is linearly charged or

discharged by a constant current source/sink. The amount of current can be

controlled by changing the voltage vc applied at the modulating input (pin5) or

by changing the timing resistor RT external to IC chip. The voltage at pin 6 is

held at the same voltage as pin 5. Thus, if the modulating voltage at pin5 is

increased, the voltage pin 6 also increases, resulting in less voltage across RT

and thereby decreasing the charging current.


IC&E-CAD LAB


BY VIDYA SAGAR.P

The voltage across the capacitor CT is applied to the inverting input terminal

of Schmitt Trigger the output voltage swing of the Schmitt Trigger is designed

to Vcc and 0.5 Vcc. The output frequency of the VCO can be calculated as

follows:

The total voltage on the capacitor changes from 0.25 Vcc to 0.5 Vcc. Thus v

= 0.25 Vcc. The capacitor charges with a constant current source.

So, TC

i

t

v

TC

i

t

Vcc

25.0

t = i

VccCT25.0

The time period T of the triangular wave form equal to 2t. The frequency of

oscillator fo is,

fo = tT

2

11

= TCVccC

i

5.0

But i = T

CC

R

VcV

Where Vc is the voltage at pin 5. Therefore,

fo = CCTT

CC

VRC

VcV )(2

The output frequency of the VCO can be changed either by (i) RT, (ii) CT are

(iii) The voltage VC at the modulating input terminal pin 5. The voltage VC can

be varied by connecting a R1R2 circuit.


IC&E-CAD LAB


BY VIDYA SAGAR.P

IV. CIRCUIT DIAGRAM:

V. PROCEDURE: 1) Make connections of the VCO as show in the Circuit diagram.

2) Measure the free running frequency of VCO at Pin 4, with the input signal

V in set = 0. Compare it with the theoretical calculated value.

3) Draw the output wave form obtained at Pin No 3.

4) Draw the output wave form obtained at Pin No 4

5) Compare the theoretical and practical values of free running frequency.

VI. OBSERVATIONS:

fo = CCTT

CC

VRC

VcV )(2 = ___________

Output amplitude at Pin 4 = _____________ Output amplitude at Pin 3 = _____________


IC&E-CAD LAB


BY VIDYA SAGAR.P

VII. CALCULATIONS:

TC

i

t

v

TC

i

t

Vcc

25.0

t = i

VccCT25.0

The time period T of the triangular wave form equal to 2t. The frequency of

oscillator fo is,

fo = tT

2

11

= TCVccC

i

5.0

But i = T

CC

R

VcV

Where Vc is the voltage at pin 5. Therefore,

fo = CCTT

CC

VRC

VcV )(2


IC&E-CAD LAB


BY VIDYA SAGAR.P

VIII. GRAPH:

IX: RESULT: fo = _________

X: INFERENCE: i. The working of 566PLL is observed and the output is plotted.

ii. The time period of the output waveform is calculated



IC&E-CAD LAB


BY VIDYA SAGAR.P

XV REVIEW QUESTIONS i. List the basic building blocks of a VCO.

ii. Define free running frequency.

Iii .Define lock range

Iv .Explain the block diagram of IC 566 VCO.

v. What is the range of modulating input voltage applied to a VCO?

vi. What is the frequency transfer coefficient of VCO.

vii. List the applications of VCO,

viii. Explain about Schmitt trigger circuit.

Ix .Explain how VCO is used in PLL.

X .Explain the operation of constraint current source.


IC&E-CAD LAB


BY VIDYA SAGAR.P

6. VOLTAGE REGULATOR USING IC 723.

I AIM: To study the operation of IC723 voltage regulator II EQUIPMENTS AND COMPONENTS: (i).APPARATUS 1. DC power supply - 1 No.

2. Digital Multimeter - 1 No.

3. Ammeter - 1 No.


COMPONENTS: 1. 1kΩ Resistor – 1 No.

2. 33Ω Resistor – 1 No.

3. 10k Ω Resistor – 1 No

4. 680 Resistor – 1 No.

16. 2.2 k Resistor – 1 No.

17. 100 pF Capacitor – 1 No

18. IC723


IC&E-CAD LAB


BY VIDYA SAGAR.P

III. THEORY: The three-terminal regulators have the following limitations

1. No short-circuit protection

2. Output voltage (+ve or –ve) is fixed

These limitations have been overcome in 723 general purpose regulator. This

IC is inherently low current device but can be boosted to provide 5 amps or

more current by connecting external components. The limitation of 723 is that

it has no in-built thermal protection. It also has no short-circuit current limits.

The IC723 has two sections. The first section consists of Zener Diode constant

current source and a reference amplifier. The other section of the IC consists of

an error amplifier series pass transistor and a current limit transistor. This is a

14-pin DIP package. The main

Features of 723 include an input voltage of 40v max, output voltage is

adjustable from 2V to 37V, 150 mA output current without external pass

resistor, can be used as either a linear or a switching regulator.



IC&E-CAD LAB


BY VIDYA SAGAR.P

V. PROCEDURE: 1. Connect the 723 regulator as shown in the circuit diagramSet Dc power

supply voltage Vin to +10V measure and record Vref with respect to ground.

With load RL(10k pot) removed from the circuit (output open). Measure

the minimum and maximum output voltage by rotating the 1k pot through

its full range.

2. Now adjust the 1k pot so that Vo is +5V dc. Measure the voltage between

the wiper arm of the 1 k pot and ground.

3. Adjust the load RL (10 k) pot until the load current IL = 1 mA. Record VL.

Repeat for different values of load currents 5mA, 10mA, 15mA, 18mA.

Calculate the load regulation and compare with manufacturer’s

specifications

4. Gradually increase the load current above 18mA, you will see that the load

voltage suddenly decreases when the load current is about 18 to 20 mA.

Now the voltage across RSC is enough to begin current limiting. Measure

and record a few values of load current and load voltage below and above

the current limiting point. Plot a graph of VL vs IL from the data obtained in

steps 4 and 5

VI. OBSERVATIONS: 1. The load regulation = _____ %

2. The line regulation = ______%


IC&E-CAD LAB


BY VIDYA SAGAR.P

VII. CALCULATIONS: 1. The load regulation can be calculated by using the below formulae

%load regulation = ( (Vfl – Vnl) / (Vfl)) * 100

2. The line regulation can be calculated by using the below formulae

%line regulation = ( Vo / Vi )

VIII. GRAPH:

IX: RESULT: i.The % load regulation =

ii. The % line regulation =

X: INFERENCE: i. The working of 723 regulator is observed and the output is plotted.

ii. The load regulation is calculated

iii. The line regulation is calculated


IC&E-CAD LAB


BY VIDYA SAGAR.P

XV REVIEW QUESTIONS i.What is the maximum input voltage that we can give to 723 regulator?

ii.What output voltage range we can obtain from 723 regulator?

iii.What is the output current in case of 723 regulator?

iv.What are the applications of 723 regulator?

v.Define line regulation

vi.Define load regulation

vii.Define ripple rejection

viii.Define long term stability

ix.What is the current limit protection

x.What are the ideal values of load and line regulations


IC&E-CAD LAB


BY VIDYA SAGAR.P

7. 4 bit DAC using OP AMP.

I AIM: To construct a 4-bit R – 2 R ladde type D/A converter. Plot the transfer

characteristics, that is, binary input vs output voltage. Calculate the resolution

and linearity of the converter from the graph.

II EQUIPMENTS AND COMPONENTS:

(i).APPARATUS

1. DC power supply - 1 No.

2. CRO - 1 No.



COMPONENTS:

1.10 kΩ Resistor – 1 No.

2.20 k Resistor – 1 No.

3.IC741 - 1 No.

.Bandwidth adjustment range = < 1 to 60%

III. THEORY:

Most of the real world physical quantities such as voltage current temperature

pressure are available in analog form. It is very difficult to process the signal in

analog form, hence ADC and DAC are used.


IC&E-CAD LAB


BY VIDYA SAGAR.P

The DAC is to convert digital signal into analog and hence the functioning of

DAC is exactly opposite to that of ADC. The DAC is usually operated at the

same frequency as the ADC. The output of the DAC is commonly staircase.

This staircase like digital output is passed through a smoothing filter to reduce

the effect of quantization noise. There are three types of DAC techniques (i)

Weighted resistor DAC (ii) R-2R ladder. (iii) Inverted R-2R ladder. Wide

range of resistors is required in binary weighted resistor type DAC. This can be

avoided by using R-2R ladder type DAC where only two values of resistors are

required it is well suited for integrated circuit realization.



IC&E-CAD LAB


BY VIDYA SAGAR.P

V. PROCEDURE: i. Set up the circuit shown in Fig.

ii. With all inputs (d0 to d3) shorted to ground, adjust the 20 k pot until the

output is 0V. This will nullify any offset voltage at the input of the op-amp.

Iii ..Measure the output voltage for all binary input states (0000 to 1111) and plot

a graph of binary inputs vs output voltage.

iv. .Measure the size of each step and hence calculate resolution

v. .Calculate linearity

VI. OBSERVATIONS: Output Voltage = ____________

Size of each step = ____________

Resolution = ____________

Linearity = ____________

VII. CALCULATIONS: VO = VR / 2 = VFS / 2

Resolution (in volts) = VFS / (2n –1) = 1 LSB increment.


IC&E-CAD LAB


BY VIDYA SAGAR.P

VIII. GRAPH:

. IX: RESULT: Output Voltage = ____________

Size of each step = ____________

Resolution = ____________

Linearity = ____________

X: INFERENCE: i. The working of D / A converter is observed and the output is plotted.

ii. The staircase wave form is plotted.

iii. Resolution is calculated.


IC&E-CAD LAB


BY VIDYA SAGAR.P

XV REVIEW QUESTIONS

i. Classify DAC on the basis of their output.

ii. Name the essential parts of a DAC.

iii. Describe the various types of electronic switches used in DAC.

vi. How many resistors are required in 12 bit weighted resistor DAC?

v. Why is an inverted R-2R ladder network DAC is better than R-2R ladder

DAC.

vi. Define resolution.

vii. Define linearity.

Viii .Define monotonicity.

Ix .Define step size.

x. Define settling time.


Documents

Ecad Lab Manual1