Early Monolithic Pipelined ADCs

Stephen H. Lewis

Solid-State Circuits Research LaboratoryDepartment of Electrical and Computer Engineering

University of California, Davis CA USA

1

Pipelining

Input Stage1

Stage2

StageN Output

• Break a repetitive job into sequential stages

• When full, pipelines are fast

• Each stage can be optimized for the job it does

• All outputs come through the same path

• The same concept as in assembly lines

2

Pipelined ADC Concept

• Gordon, TCAS, 7/78Jepperson, US Patent #3,119,105, 1/64Waldhauer, US Patent #3,187,325, 6/65

• Black, PhD Thesis, UC Berkeley, 11/80• McCharles, PhD Thesis, UC Berkeley, 6/81• Martin, Asilomar, 9/81

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Pipelined ADCs Need SHAs

Vi

φ1 C φ1

φ2

−+ Vo

• CMOS provides simple SHAs

• MOS transistor switches have VDS = 0 when ID = 0

• Little leakage

4

Algorithmic ADCs

AnalogInput

1+

Σ 2SHASHA

1-bitADSC

1-bitDASC−

• Reusing stages saves area

• McCharles, Saletore, Black, and Hodges, ISSCC, 1977

• Li, Chin, Gray, and Castello, JSSC 12/84

• Shih and Gray, JSSC, 8/86

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The First Monolithic Pipelined ADCs

AnalogInput

Stage 1 Stage i Stage k

Digital RegistersDigital Output

+Σ 2

SHA

1-bitADSC

1-bitDASC−

• Masuda, Kitamura, Ohya, and Kikuchi, CICC 19847-b res. and linearity at 3 Msamples/s

• Yiu and Gray12-b res. and 10-b linearity at 278 ksamples/s

• No redundancy

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Masuda’s SHA

Vi 2C C

φ1

φ̄1

φ̄1

φ1

−+ Vo

• Single ended in 1.5-µm CMOS

• Uses partial offset cancellation at the input

• Uses dummy switch to reduce charge-injection error

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Yiu’s SHA

Vip

Vin

C

C

−

+G1 Vo

−+

g2CH

• Fully differential in 3-µm CMOS• Cancels offset at aux. input (Degrauwe, JSSC 8/85)• Uses reference refreshing (Shih and Gray, JSSC 8/86)• 9 clock phases per conversion• Fabricated in 1984, PhD Thesis, UC Berkeley, 1992

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Increased Stage Resolution and Interstage Gain

AnalogInput

Stage 1 Stage i Stage k

Digital RegistersDigital Output

+Σ 2n

SHA

n-bitADSC

n-bitDASC−

• Increasing n reduces significance of errors after first stage

• Still sensitive to first-stage comparator offsets

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Residue Plots

Held Input+

ΣResidue

8SHA

3-bitADSC

3-bitDASC−

0 HeldInput

Conv.Range

ResidueVR/8

−VR/8

0 HeldInput

Conv.Range

ResidueVR/4VR/8

−VR/8−VR/4 Negative

OffsetPositiveOffset

• If DASC is ideal, digital output and residue together are still accurate• However, increasing max. |Residue| saturates next stage

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Reduced Interstage Gain

Held Input+

ΣResidue

4SHA

3-bitADSC

3-bitDASC−

0 HeldInput

Conv.Range

ResidueVR/4VR/8

−VR/8−VR/4

−1

NegativeOffset

+1

PositiveOffset

• Halving the gain doubles the next-stage range• Now the errors shown can be measured and corrected• Correction requires ±1• Correction range is ±0.5 LSB @ 3-b level

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Previous Work on Redundancy and Dig. Correction

• Verster, IEEE Trans. on Electronic Computers, 12/64

• Gorbatenko, IEEE National Convention Record, 3/66

• Kinniment, Aspinall, and Edwards, IEE Proc., 12/66

• Horna, Comsat Technical Review, 1972

• Taylor, PhD Thesis, UC Berkeley, 1978

• Enabled by CMOS technologies

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Interstage Offset without Redundancy

Stagei +

ΣStagei + 1

VOS+

Front end Back end

OutputCode

VOS = 0

Analog Input

OutputCode

VOS > 0

Analog Input

Nonlinearity

• If VOS 6= 0, fine and coarse thresholds are not aligned

• Nonlinearity appears

• Offset cancellation is usually needed without redundancy13

Interstage Offset with Redundancy

+Σ

+Σ 1

22n

VOS+SHA

n-bitADSC

n-bitDASC−

+Σ 1

22n+Σ

VOS+

SHA+

Σ

n-bitADSCVOS

−

n-bitDASC−

• If VOS < correction range,Nonlinearity does not appearVOS 6= 0 causes only input-referred offset

• Offset cancellation is not requiredReduces power dissipation

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Berkeley Pipeline

• 3-µm double-poly CMOS

• Area = 5.5 mm2

• Power Diss. = 180 mW

• Speed = 5 Msamples/s

• Resolution = 9 bits

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Digital Correction with Offsets

Held Input+

ΣResidue

4SHA+

3-bitADSC

Σ 0.5 LSB−

3-bitDASC

+Σ

−0.5 LSB+

0 HeldInput

Conv.Range

VR/4VR/8

−VR/8−VR/4

ResidueWithoutOffsets

0 HeldInput

Conv.Range

VR/4VR/8

−VR/8−VR/4

ResidueWith

Offsets

• Correction requires +1 when Residue > 0• Correction range is still ±0.5 LSB @ 3-b level

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Sutardja’s SHA

Vi

φ1 C

Vi

φ1

Cφ2

φ1

φ2

−+ Vo

• Uses feedforward to increase the gain

• Gives ideal gain = 2 with equal capacitors

• Increases FB factor and speed & improves accuracy

• PhD Thesis, UC Berkeley, 1988

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Drop the Top Comparator

0 HeldInput

Conv.Range

ResidueVR/4VR/8

−VR/8−VR/4

With top comparator

0 HeldInput

Conv.Range

ResidueVR/4VR/8

−VR/8−VR/4

Without top comparator

• Forces error that can be corrected (simplifies testing)• Does not change the correction range• Requires 2n − 2 comps (Res = log2(7) ' 2.8 b/stg)• Not fast enough for video in 0.9-µm CMOS

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1.5-bit Stage Resolution

0 HeldInput

Conv.Range

Residue

−VR −VR/4 VR/4 VR

VR/2VR/4

−VR/4−VR/2

100100

• Requires 2 comps and 3 DAC levels (Res = log2(3) ' 1.5 b/stg)• Same as in

Jusuf, Memo No. UCB/ERL M90/69, UC Berkeley, 8/90Ginetti, Jespers, and Vandemeulebroecke, JSSC 7/92

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Multiplying-Digital-to-Analog Converter

Vin

φ1

C Cφ1X

Vrn

Y

Vrp

ZC C

φ1φ1X

Vrp

Y

VrnVip

φ2

−+φ1

′′

−φ1

′′

φ1′

φ2

+

Vop

Von

• Feed forward improves accuracy and speed• Generates 3 DAC levels• Fast enough for video in 0.9-µm CMOS

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AT&T Pipeline

• 0.9-µm double-poly CMOS

• Area = 8.7 mm2

• Power Diss. = 240 mW

• Speed = 20 Msamples/s

• Resolution = 10 bits

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Other Work

• Karanicolas, Lee, and Bacrania, JSSC, 12/93

• Cho and Gray, JSSC, 3/95

• Cline and Gray, JSSC, 3/96

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Acknowledgments

• Professor Paul R. Gray

• Professor T. R. Viswanathan

• My colleagues at Berkeley and Bell Labs

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