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Module-3

Professor K. N. BhatCentre for Nano Science and Engineering

(CeNSE)

Indian Institute of Science

Bangalore-560 012Email : knbhat@gmail.com

NON-classical MOSFETs

Silicon On Insulator (SOI) MOSFETS

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Requirement for High Performance nanoscale MOSFETs

Doping concentrations should not be highElectric field E(x) normal to the channel to be kept lowVDDshould be kept low to minimize power dissipation- Need to minimize threshold voltage.This calls for idealsub-threshold slope-in conventional devices this is

difficult to achieve

For electrons

Low field mobility should be high

VDSVGS

E(y)E(x)

E(0+) =E(y) at y=0+

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High Performance nanoscale MOSFETs

1. Non classical devices SOI MOSFETs and variations.

2. Germanium based MOSFETs

3. Schottky Barrier S/D MOSFETs4. Strained layers to achieve higher mobility MOSFETs

5. GaAs FETsand HEMTS

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4

Shallow junctions formation and metal

spiking and shorting the junction

(100) Bulk silicon wafer

Bulk Silicon wafer cross section and Bulk Si MOSFET

N+P

DrainGateSource

N+

N+

(100) Silicon

Silicon

< 0112 >Sapphire

(Al2O3 )

Gate DS

N+N

+

P

Silicon On Sapphire (SOS) Wafer and SOS MOSFET cross-section

< 0112 >Sapphire

(Al2O3 )

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BOX= Buried Oxide

Lateral and vertical scaling easier.

Spiking and shorting the junction is not an issue

SOI Layer

Silicon substrate

BOX

Back Gate

Front GateDS

N+ N+P

(100) Silicon

SOI Wafer Cross section and SOI MOSFET

SiO2 SiO2

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6

Silicon-On-Insulator (SOI) Technologies

1. Silicon-On-Sapphire (SOS)

Low channel electron mobility is observed in SOS

MOSFETs (n= 230-250 cm2/V-sec)

Used mainly for Defense applications for operation in

harsh environment (high Temperature and radiation )

(100) Silicon

(0112) Sapphire (Al2O3)

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Multiple implants often reduce defectdensity

Typical BOX thickness: 100, 200, 400 nm SOI film thickness varies from ~50 - 240 nm

Oxygen implant at:-Energy 120-200 keV-Dose ~0.3-1.8x1018cm-2

Anneal in inert ambientabove 1300C, 3-6 hours

SOI

BOX

Substrate

2.Separation by Implanted Oxygen (SIMOX)

Implant1.8x1018/cm2

for 400nm

BOX thickness

There are 4.4x1022O2atoms /cm3

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1m SiO2is formed by oxidation of 0.44 m thickness of Si(Oxidation of 0.44m of Si gives an oxide thickness = 2.27x044=1m )

No of Si atoms in 0.44m thick Si = (5x1022 )x0.44x10-4= 2.2x1018

No of Oxygen atoms in 1m thick SiO2is = 4.4x1018/cm2 (twice that of

no of Si atoms )

O2atoms implanted to achieve 1m thick BOX layer =4.4x1018/cm2

Therefore, Oxygen dose required for 400 nm (=0.4 micron) BOX = 1.76 x

1018/ cm2.

Number oxygen atoms in SiO2layer of 1 micron thickness

Si: Molecular wt = 28 ; Density = 2.33 gm/cm3

SiO2: Molecular wt = 60 ; Density = 2.27 gm/cm3

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Thermally Oxidize

Wafer-A

Etch back the topwafer to the required

SOI thickness

Bond wafer -B

on the oxide bySFB

BOX

A

B

Silicon Fusion Bonding (SFB) is done in two steps :

(1) Press the two hydrophilic wafers at lowtemperature (400 C ) OH bonding due to Vanderwalforce.(2) Anneal ~1100C to drive H out and

strengthen the bond by Si-O-Si bonding

3. Bonded and Etch back SOI (BESOI)

BOX

A

BOX

A

SOI

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Hydrogen implantationthrough thermal oxide

dose ~1-5x1016cm-2

At ~400-600C wafer A

separates from B

at H2peak

BOX

A

B

Handle wafer B

is bonded

BOX

A

B

After low temperature splitting, SOI wafer (B) is annealed~1100C to strengthen the bond. Wafer (A) is reused.

SOI thickness set by H2implant energy and BOX thickness

4. Smart- Cutprocess

BOX

H2peak

A

Range RPfor H2in Si is 8 nm/KV

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Benefits of SOI MOSFET

11

Low drain / source junction Capacitances and lowleakage currents

Ability to operate in harsh environments

(high temperature and high radiation dose rate)

N+

P

DrainGateSource

N+ N+

Bulk Silicon MOSFET SOI MOSFET

N+ N+P

Front

Gate DrainSource

SiO2

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SOI CMOS: Capacitance Advantage

Junction capacitance: smaller than in bulk

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Planarized surface by etching and LOCOS

Etch the SOI layer partially

leaving 0.44 tSOI un-etched as

shown

SOI layer

LPCVD nitride Thermally oxidize. The Si3N4

oxidation rate is about 30 times

smaller than that of Si oxidation

rate. The region where nitride is

absent oxidizes. The volume of

SiO2is 2.27 times that of Si. Thesurface of oxide is the same as

that of Si

Local Oxidation Of Silicon

(LOCOS)

SiO2

SiO2

SiO2

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Bulk CMOS SOI CMOS

SOI CMOS: Latch-up advantage

latch-up free operation

INOUT VDGND

IN

P+ P+ P+ N+N+ N+

N-well

P-substrate

P-Channel

VD

N-Channel

N+ N+P P+ P+N

OUTGND

Latch-up free operationSusceptible to Latch up

SiO2

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15

CMOS - Bulk vs. SOI

Bulk CMOS structure Complicated with

trench isolation etc

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SOI CMOS structure Simpler Technology

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N+ N+P P+ P+N

OUTGND VDD

Benefits of SOI CMOS Technology over bulk CMOS

Low parasitic capacitances :Drain /Source junctions and interconnectsAbility to operate at higher temperaturesand radiation environment

Simpler technology with no wells or trenchesShallow junctionseasy to fabricate

Better dielectric isolation in bothvertical and horizontal directions

Latch up free CMOS Low voltage operation Ideal sub-threshold slope S

(60mV per decade)N-Channel P-Channel

N NPS D

Gf

Gb

Summary

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SOI MOSFET Structure

Front Gate Oxide

(FOX), Thickness =G1 DS

G2

N+ N+P

Substrate

BOX Buried Oxide (BOX)Thickness=

Symmetrical Double Gate (DG) MOSFET: G1 and G2identical material and

Undoped Ultra Thin Body (UTB) MOSFET:

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Common types of SOI MOSFET

Partially Depleted SOI MOSFETFully Depleted MOSFET

Reference:J.F.Colinge, Silicon On Insulator Technology:Materials

to VLSIKluwer Academic Publishers , 1991 (first

edition ), 1997 (second edition)

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Case (i) Double Gate MOSET

is PD if

Case (ii) Single Gate MOSFET

is PD if

PartiallyDepleted (PD) SOI MOSFET

The basic device equations of PD SOI MOSFETs are the sameas for bulk devices.

In this case two inverted channels independent of each othercan exist in parallel

Handle wafer

BOX

FOX

N+N+

+VGf

+VGb

SOI

Handle wafer

When Surface inverted , the

surface potential is and thedepletion layer width is xd(max)

2 f

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Case (i) Double Gate MOSET

is PD if

Case (ii) Single Gate MOSFET

is PD if

PartiallyDepleted (PD) SOI MOSFET

The basic device equations of PD SOI MOSFETs are the sameas for bulk devices.

In this case two inverted channels independent of each othercan exist in parallel

Handle wafer

BOX

FOX

N+N+

+VGf

+VGb

SOI

Handle wafer

When Surface inverted , the

surface potential is and thedepletion layer width is xd(max)

2 f

Neutral p-region

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Fully Depleted (FD) SOI MOSFET : tSOI< xd(max)

This electrostatic coupling, makes the front channelFD device parameters dependent on the back gate

voltage, including drain current, threshold voltage,

sub-threshold slope etc

In FDSOI case,the front and

back channels are

electro-statically

coupled duringdevice operation

VGb = 0 or +ve

BOX

FOX

N+N+

+VGf

Handle wafer

SOI

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23

Energy Band diagrams of

(A)Bulk, (B) Partially Depleted (PD) SOI MOSFET(C)Fully Depleted (FD) SOI MOSFETs

Shaded regions are depleted

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FD MOSFET: Operation Modes and Threshold Voltages

a) Front Channel inverted, Back channel accumulatedb) Front Channel inverted, Back channel depleted

c) Front Channel inverted Back Channel invertedd) Volume Inversion in UTB DG SOI MOSFET

VGf

pn+ n+tSi

tOxf

tOxb

P+-Substrate

VGb

Front channel

Back channel

Front Gate

Back Gate

VD

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N+ P N+

SOI MOSFET: Front channel and back

channel can have various bias conditions

Front n- Channel Inverted with the

(a)Back n-Channel accumulated (VGb< 0),

(b) Back n-Channel Depleted (VGb> 0)

( c) Back n-Channel Inverted

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Channel depletedChannel

accumulated

VG

x

P-Si

Accumula

tion

+ + + + + + +

P-Si

Depletion

-- -

E(x)

X

X

E(x) X

V(x) XV(x)

VSi

-V G

Bulk MOS Channel Inverted

P-Si

-- -- - - - - - - E

x

sE

sf Q

s Q

D

oxE

ox

sE

sf

Vox Eoxtox QDtoxox

QDC

ox

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Threshold voltages of MOSFETs:

P-Si

Depletion

Accumulation

Depletion layer width reaches a

maximum = and

reaches a minimum

At threshold voltage

Inversion

VOX+

-+

-VSi

(A) Bulk MOSFET

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(B)FD SOI MOSFET Back channel in Accumulati0n

E(x)

Dotted lines represent the situation

just when channel is fully depleted N+ P N+

(i) SOI Layer is just depleted (Vgf=Vgf1)Vgf1

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(C) Fully Depleted SOI MOSFET Back gate grounded

E

sfE

oxfEoxb

Dotted lines represent the situation

just when channel is just depleted

N+ P N+

When SOI Layer is just depleted

(represented by dotted lines)

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Using (2) in (1)

When

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(D) Vgf varied with Back channel in depletion

x1

Vgb =Vgb1is held constantand Vgf is increased from 0

to Vgf1

At Vgf= Vgf1 depletionlayers merge at x1.

E=0 at x1and potential isminimum and is 0 at x1.

If Vgfand Vgbare nowincreased by V, the electric

field distribution does not

change , but the potentialdistribution curve shifts up

by the voltage, V tillV

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Back VGf = VGbabove VpT

Esf

E

sb

Eoxf

Eoxb

N+P

N+

Both Channels Inverted

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General equations governing the VGf , VGb ,!sfand !sb

Similarly,

Using (3) in (1) we obtain, noting that

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Electric Field Esfon the surface of the SOI

Front Channel inverted

(1) Back channel in

accumulation:

(2) Back channel

depleted :

(3) Back channel

Inverted :

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Electric field and Potential distribution

Front surface is inverted

A- Back surface accumulated

B Back surface depleted

C - Back surface Inverted0

E

0

0

AB

B

A

C

C

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Effect of Coupling on VThf of FD SOI

Back Channel depleted

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3737

Measured ID - VGfcharacteristics at various

back gate bias voltages VGb

p n+n+

VGf

VGb

VD

tOxf = 115nm

tSi = 87nm

tOxb = 400 nm

W/L = 200m/ 15m

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Sub-threshold Swing FD SOI MOSFET

(PD)

(FD)

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Subthreshold slope vs. SOI Thickness

The subthreshold slope changes drastically in the

transition region from PD to FD SOI

NA=8X1016/cm3, toxf=25nm

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Electric field (Mobility): FD vs. Bulk

Since transverse electric fields are smaller in FD devices,mobility is higher

Also reflected in higher current drive

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00

E

Front surface is always in inversion

A Back surface is in accumulationB Back surface is in depletion

C Back surface is in inversion

Transverse Electric

Field in the channel

region is minimum

in DGFD SOI

MOSFET

A

B

C

Highest mobility

can be achieved in

DGFD FET

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Measured Transconductance of SOI MOSFET

toxf= 115nm, W/L = 200!m/15 !m, toxb= 400nm,

"=14-22ohms

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Extracted Mobility

-30 -20 -10 0 10 20 30 400

200

400

600

800

1000 mnfBESOIm

nbBESOIm

nf Smart Cutm

nb Smart Cut

Mobility(cm

2

/V-sec)

VGb(V)

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Higher Mobility in FD DG MOSFET

(1) Transverse electric field is low.Therefore high mobility

(2) Thin SOI layer leads to tight coupling of VG with

channel potential. Therefore no need to dope the channel

to control SCE and VTH. .This leads to higher low - field

mobility and relieves scaling limitation of VTH .

(a) Improvement in low field mobility

(b) Reduced 2D SCE and in shorter channel length

devices with (i) ideal sub-threshold slope, S=60mV

and (ii) negligible shift in VTH

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Criterion to Suppress SCE in FD DG MOSFET

Threshold voltage shift due to SCE

Sub-threshold voltage versus

L

SCE reduces for smaller silicon thickness

Electrical Distance of channel centre to

the gates

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Definition of VTHin un doped FD DG MOSFET

Since the silicon film is un doped, it is virtually equi-

potential across the thickness as shown.

This results in volume inversion. Popular definition of

VTH (surface potential equal to ) cannot be used.

Alternate definition :

Gate voltage when inversion charge density reaches aparticular value (QTH)

Inversion

DepletionAccumulation

Depth (nm)

Potential(V)

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Ultra thin DGSOI MOSFET Transconductance(Experimental results)

gm( dg )

( gm( fg )

gm( bg )

)

(dg)

(fg)

(bg)

Ref: Thomas Ernst, S.Cristoloveanu etal

Ultimately Thin Double Gate SOI MOSFETs

IEEE Transactions on Electron Devices, pp.

830-839, Vol.50 March 2003.

VGf

VGb

P N+N+

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Ultra Thin DG SOI MOSFET Carrier confinement in very

narrow potential wells isgoverned by the wavefunctions and energy levelsof the various sub-bands.

Self consistent solution ofSchrdinger and Poissonsequation is now necessaryto calculate carrierconcentration.

The striking featureobtained by this solution isthat most of the carriersflow through the middle ofthe film, and not at theinterfaces

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Ultra Thin DG SOI MOSFET

Interesting result The

transconductanceof DG SOI is morethan double SG

SOI Why ?

Most of carriers inDGSOI flow throughthe middle of thefilm, where carriermobility is muchhigher than at theinterfaces

I t f Q ti ti

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Impact of Quantization

Effects

Threshold voltage increases below 10 nmsilicon thickness due to increase of EO

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Sensitivity of lowest sub band Energy E0in thin

silicon quantum well to the silicon thickness a

Ultimate limit to SOI filmthickness is governed by

Quantum confinement which

increases the sub-band

energies for very thin Silicon

layers..

This makes the ofDGFET to be very sensitive

to thickness variations, thus

limiting the practical SOIthickness to above 3nm.

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Advanced MOSFET Structures

Special Triple Gate Device -

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Special Triple Gate Device -

FINFET

Relatively simple process Effective channel width (W) = 2 x Hfin+ Tfin W can be increased by having multiple fins Devices with L = 18 nm and tox= 2.5 nm have been

demonstrated

Empirical scaling rule to suppress SCE L > 3Tfin

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FD SOI MOS devices have several inherentadvantages over conventional bulk MOS deviceslike low VTh, Ideal S, Improved low fieldMobility and drive current mobility

SOI wafers are also being increasingly used forother applications such as MEMS, radiation harddevices and high temperature electronics.

Integrationof FD SOI MOSFETs has been madepossible withthe invention of Fin FET

Summary

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(1) Qiang Chen, K.A. Bowman, E.M.Harrell and J.D.MeindlDoubleJeopardy in nanoscale Court

, IEEE Circuits and Devices, pp.28-34,January 2003

(2)Thomas Ernst, S.Cristoloveanu etalUltimately Thin Double Gate SOI

MOSFETsIEEE Transactions on Electron Devices, pp.830-839, Vol.50

March 2003.

(3) B.Bindu, N.Lakshmi, K.N.Bhat , A.DasGupta,

Design of single gate n-channel and p-channel MOSFETs with enhanced current - drive due to

simultaneous switching of front and back channels in SOI CMOS

technologySolid State Electronics, Vol.50,pp.1359-1367, 2006

(4) IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5,

MAY 2002

(5)Aditya Sankar Medury, K. N. Bhat and Navakanta BhatThreshold

voltage modeling under size quantization for ultra-thin silicon double-

gate metal-oxide-semiconductor field-effect transistor J. Appl. Phys.

Some useful References