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E0-286: VLSI TestCourse Outline
Dr. Rubin ParekhjiDr. Srivaths Ravi
Dr. Devanathan Varadarajan
Texas Instruments India Pvt. Ltd.
09 Aug 2012
22
No. Topic Hours Who1 Background
.Design topics: SOC design methodology. IP components. Integration. Clocking. I/Os and interfaces. Device modes. Logic, memories, analog, I/Os, power management. Validation platforms.
2 SR
2 Test requirements. Test handoffs. Testers. Where DUT and DFT fit into design / manufacturing framework. Basic philosophy: Test, ATPG, DFT, BIST, COF, TTR. Test cost metrics and test economics.
2 RP
3 Fault models and
ATPG.
Logic fault models: SAF, TDF, PDF, Iddq, St-BDG, Dy-BDG, SDD, etc. Basics of test generation and fault simulation. Combinational circuits. Sequential circuits.
3 RP
4 Specific algorithmic approaches. Illustrative examples. CAD framework. Optimisations. 2 RP5 Scan
design.Scan design requirements. Types of scan and control mechanisms. Test pattern construction for scan. Managing scan in IPs and SOCs.
2 DV
6 Scan design optimisations. Partitioning. Clocking requirements for scan and delay fault testing. Speed of operation.
3 DV
7 Memory test.
Memory fault models. Functional architecture as applicable to test. Test of memories. Test of logic around memories. BIST controller configuration.
3 DV
8 Test of logic around memories. DFT and architecture enhancements. Algorithmic optimisations.
2 DV
9 Test interfaces.
Test control requirements. Test interfaces - 1500, JTAG. Hierarchical, serial control. 1 DV10 Module / IP test. SOC test. Board test. System test. Boundary scan. 1 DV
Mid-semester Test.
33
No. Topic Hours WhoMid-semester Test.
11 BIST. Motivation. Framework. Controller configurations. FSMs. LFSRs. STUMPS architecture. Scan compression and bounds. Test per cycle. Test per scan. Self-testing and self-checking circuits. Online test.
5 RP
12 Design considerations.
Design considerations. Physical design congestion. Partitioning. Clocks. Test modes. Pins. Test scheduling. Embedded test. Architecture improvements. Test in the presence of security. Advanced topics and D&T implications (ATPG improvements for SDD, cell internal faults).
4 SR
13 Power management during test. Methods for low power test. ATPG methods. DFT methods. Scan methods. Low power compression. Test of power management. Implications of power excursions. Optimisations. Industry techniques.
4 SR
14 Analog test.
Test requirements. DFT methods. BIST methods. Test versus measurement. Defect tests versus performance tests.
1 RP
15 Tests for specific modules - PLL, I/Os, ADC, DAC, SerDes, etc. RF test requirements. 2 RP16 Other
topics.Reliability. Fault tolerance. Characterisation requirements. Silicon debug. Testers. Optional ???
3 TBD
17 Lab. assignments. After mid-September 2012.18 Other assignments. After individual modules.
End semester test.40
44
E0-286: VLSI TestAn Introduction to VLSI Design and Test
Dr. Rubin ParekhjiDr. Srivaths Ravi
Dr. Devanathan Varadarajan
09 Aug 2012
55
Design complexity trend
q Exponential increase in complexity, follows Moore’s law
[ITRS_2011]
66
Evolution of IC design process
q IC design process improves significantly often to catch up with Moore’s law
Year
log
(#tr
ansi
stor
s)
Transistor-level
Gate-level
Register Transferlevel
IP/core based IP/core based SystemSystem--onon--Chip Chip
designdesign
77
A System-On-Chipinside the tablet
What is System-on-Chip?
[Amazon, ARM, IFixit, TI]
An example tabletBoard of the
tablet
An IP/core inside the SoC
SOC SOCFLASH
SOC
88
System-On-Chip
q Increasing integration of diverse components (which were earlier an entire system) into one chip¦ Logic, Memory, Analog, Power management, etc.
q Core-based SOC design¦ Develop components / IPs / ‘Core’s¦ Integrate IPs together to form a system¦ Test IPs stand-alone in SOC context
? Diverse IPs => Diverse tests¦ Test IP integration / interface / ‘system’
99
SOC Design Flow
Architecture and Specification
Behavioral / RTL Coding
RTL Verification
Synthesis
Gate LevelVerification
DFT Insertion &Test Generation
Static TimingAnalysis (STA)
Physical Design
STA
Timing Verification
Silicon Fab.
Test
Addressed by this course
1010
SOC Design Flow: Architecture specification
q Architecture¦ High-level block diagrams, cores used and the
system integrationq Specifications
¦ Power, performance, area and scheduleq Example: A 3-bit counter
¦ Functionality? Start from <D> and count up to 7? Set output to high when count reach 7
¦ Frequency: 100 MHZ¦ Power: 2.5mw¦ Voltage: 1.2V¦ Temperature: 0C – 85C
1111
SOC Design Flow: RTL design & verification
q Behavioral / RTL coding¦ Algorithmic description of the core functionality
? Languages: System C / Verilog / VHDL¦ Example:
q Verification¦ Ensure that design meets functionality and
specifications (frequency, power, etc.)
module counter (CLK, LOAD, D, Q);input CLK, LOAD;input [2:0] D;output Q;reg [2:0] tmp;
always @(posedge CLK) begin
if (LOAD) tmp = D; else tmp = tmp + 1'b1;
end
assign Q = (tmp == 3'b111) ? 1'b1: 1'b0 ;endmodule
1212
SOC Design Flow: Synthesis
q Synthesis¦ Maps the high-level design to logic gates / netlist
? “Technology” library, containing details on available logic gates, is an input to synthesis
¦ Optimizes the design to meet the specifications? Design “constraints” are input to synthesis§ Timing / area / power constraints
¦ Example: module counter ( CLK, ALOAD, D, Q );input [2:0] D;output Q;input CLK, ALOAD;wire N6, N7, N8, n8, n9, n10, n11, n12, n13;wire [2:0] tmp;
TDN16DHNHVQ \tmp_reg[0] ( .D(N6), .SD(tmp[0]), .SCAN(1'b0), .CLK(CLK), .Q( tmp[0]) );TDN16DHNHVQ \tmp_reg[1] ( .D(N7), .SD(tmp[1]), .SCAN(1'b0), .CLK(CLK), .Q( tmp[1]) );TDN16DHNHVQ \tmp_reg[2] ( .D(N8), .SD(tmp[2]), .SCAN(1'b0), .CLK(CLK), .Q( tmp[2]) );NO2D1HVQ U13 ( .A(tmp[2]), .B(n8), .Y(Q[0]) );MU112ZHVQ U14 ( .A(n9), .B(n10), .S(ALOAD), .Y(N8) );IV1D0BHVQ U15 ( .A(D[2]), .Y(n10) );EX21H0ZHVQ U16 ( .A(n8), .B(tmp[2]), .Y(n9) );NA2D0HVQ U17 ( .A(tmp[1]), .B(tmp[0]), .Y(n8) );IV1D0BHVQ U18 ( .A(n11), .Y(N7) );MU112ZHVQ U19 ( .A(n12), .B(D[1]), .S(ALOAD), .Y(n11) );EX21H0ZHVQ U20 ( .A(tmp[1]), .B(tmp[0]), .Y(n12) );MU112ZHVQ U21 ( .A(tmp[0]), .B(n13), .S(ALOAD), .Y(N6) );IV1D0BHVQ U22 ( .A(D[0]), .Y(n13) );
endmodule
1313
SOC Design Flow: Static Timing Analysis
q Static Timing Analysis (STA)¦ Verifies that timing “constraints” are met after
synthesis? Clock frequency, setup and hold times, etc.
q STA process¦ Uses mathematical techniques that propagate best
and worst case signal arrival times¦ Does not simulate / verify the functionality of the
design
1414
SOC Design Flow: Physical design
q Conversion of a design to a series of geometric patterns which performs the intended functionality¦ Conversion is based on design “rules” that
conform to the electrical and fabrication parameters of the technology and the circuit
q High-level steps in physical design¦ Partitioning - Divide-and-conquer
? Divide the design into manageable “blocks”¦ Floorplanning
? Organize “blocks” into physical regions¦ Placement
? Allocate gates within the block to physical locations, to meet the (timing) constraints
1515
SOC Design Flow: Physical design
q High-level steps in physical design (contd.)¦ Clock tree synthesis
? Route the clock to all sequential gates, to meet (timing) constraints
¦ Routing? Route the data/signal wires to interconnect the
placed gates, to meet (timing) constraints¦ Analysis
? Verify that all electrical and reliability rules are met in the placed+routed design
¦ Physical database creation? Convert the design into format (eg. GDS) readable
by semiconductor fabs for manufacturing
1616
SOC Design Flow: Physical design
q Illustration of the steps
After synthesis After parititioning After placement
After CTSAfter routingPhysical view
1717
SOC Design Flow: Test
q Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given function.
q Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
Design-Under-
Test
CompareUnit
Tester
Stimuli
Expectedresponse Pass/Fail
Outputresponse
Defective Via [K Butler, BITS 2010]
1818
SOC Design Flow: Verification vs. Test
q Verifies correctness of design.
q Performed by simulation, hardware emulation, or formal methods.
q Performed once prior to manufacturing.
q Responsible for quality of design.
q Verifies correctness of manufactured hardware.
q Two-part process:¦ 1. Test generation: software
process executed once during design
¦ 2. Test application: electrical tests applied to hardware using a tester
q Test application performed on every manufactured device.
q Responsible for quality of devices.
[V. Agrawal, Auburn]
Verification Test
1919
Testing IPs: Digital logic
q Testing combinational logic¦ Combinational logic may be expressed as boolean
function: Y = F(A0, A1, A2, … AN)? Find the input assignment (test) that sets Y = 1? Test generation problem => SAT problem =>
NP-complete
q Testing sequential logic¦ State/notion of time is an additional dimension of
complexity over combinational test generation¦ Testing all possible state transitions is impossible
? N flip-flops => 2N states? SOC shown earlier has 1+ Million flip-flops!
20
Testing IPs: Digital logic
q Design-For-Test¦ Techniques to modify / enhance the design so as to
make it testable or ease test generation effort¦ Example: “Scan” test technique helps generate
tests for sequential digital logic at combinational test generation complexity
¦ Example: Built-In Self-Test (BIST) technique uses on-chip test generation and comparison to ease tester interface requirements and/or reduce test time
Design-Under-Test
Tester
Pass/FailStart Test BIST
21
Testing IPs: Digital logic
q At-speed test¦ Both combinational logic functionality and
performance need to be tested.? Example: Need to verify that an 1GHz processor
core indeed works at 1GHz after manufacturing!¦ SOCs may have multiple clock domains, with each
core operating at its own clock source/frequency? Both intra-domain and inter-domain logic need to
be tested as per specification.¦ Additional complexity to test generation/application
? Hi-speed test application needed at tester? Need for enhanced DFT structures in the design
to ease test / tester considerations
22
Testing IPs: Memories
q Diverse on-chip memories used in SOC¦ SRAMs, DRAMs, FLASH, RFs, etc.
q On-chip RAMs are most sensitive part of the design¦ Highly dense => most memories even violate
design-for-manufacturability “rules” !¦ Most components within RAMs are analog¦ “Minor” marginality issues impact functionality
and not just performance
q DFT for testing memories => Memory BIST¦ Specialized test required to screen various analog
components within memories¦ Specialized sequence (write/read/refresh/etc.) required to
exercise defects¦ Due to high density and large memory bit count, Built-In-Self-
Test (BIST) is used to test memories on-chip
VssVss
WLWL
BLBL BLBL
VddVdd
23
Testing SOCs: Analog IPs
q Analog IPs have their own tests (“canned” tests), usually manually generated by IP designers¦ May require complex measurement instruments
which may not be supported by some testers to verify full functionality? Eg. High-speed IO interfaces (DDR / USB / etc.)
¦ Increasing use of BIST with loopback (DAC->ADC) to use only digital stimuli and response at tester
¦ Increasing use of BIST with on-chip measurement hardware? Example: On-chip “oscilloscope” is common in
many high-performance analog IPs!
2424
Testing SOCs
q Testing diverse IPs¦ DFT for logic test, memory test and other analog IP tests are
very different from each other¦ IPs may be developed by different teams or different vendor
companies? Tests for IPs may also be developed and delivered by the
IP vendors¦ Need for standard interface for test generation and test
application? Need to have full control of IP from SOC boundary to
apply IP tests
q Testing board / system¦ Each SOC to have standard interfaces to test itself and also
the board or system-level interconnect
q Example test interface standards: IEEE 1500, JTAG, IJTAG, etc.
2525
Test effectiveness metrics
q Manufacturing effectiveness¦ Yield
? Number of “Good” units / All manufactures units? Depends on process maturity and die area
q Test effectiveness¦ Coverage
? # “faults” detected / Total # faults? Ensures generated tests (during design
phase) are effective§ Faults are surrogates for defects
¦ DPPM? Defective parts escaped from Testing§ Parts returned by the Customer,
measured in parts-per-million!? Ensures applied tests (in the tester)
are effectiveq Some SOCs, especially those that are in
automotive (e.g. brake control) and medical application (e.g. pacemaker) have stringent 0 DPPM requirement
26
Test economics
qWhile we definitely need very high test quality, it is also essential to reduce test cost¦ Testers are expensive => Test time = Test cost¦ Ensuring test quality with minimal impact to test
time makes VLSI test research interesting!
