EE1411

Dynamic LogicDynamic Logic

EE1412

Dynamic CMOSDynamic CMOS

q In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.§ fan-in of n requires 2n (n N-type + n P-type)

devices

q Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.§ requires on n + 2 (n+1 N-type + 1 P-type)

transistors

EE1413

Dynamic GateDynamic Gate

In1

In2 PDNIn3

Me

Mp

Clk

ClkOut

CL

Out

Clk

Clk

A

BC

Mp

Me

Two phase operationPrecharge (CLK = 0) – Me is off => no static powerEvaluate (CLK = 1) – Mp is off

EE1414

Dynamic GateDynamic Gate

In1

In2 PDNIn3

Me

Mp

Clk

ClkOut

CL

Out

Clk

Clk

A

BC

Mp

Me

Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)

on

off

1off

on

((AB)+C)

EE1415

Conditions on OutputConditions on Output

q Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.

q Inputs to the gate can make at most one transition during evaluation.

q Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL (fundamentally different than static gates)

EE1416

Properties of Dynamic GatesProperties of Dynamic Gatesq Logic function is implemented by the PDN only§ number of transistors is N + 2 (versus 2N for static complementary

CMOS)q Full swing outputs (VOL = GND and VOH = VDD)q Non-ratioed - sizing of the devices does not affect the logic levels –

Sizing the PMOS doesn’t impact correct functionaility. Sizing it up improves the low-to-high transition time (not too critical), but trades-off increase in clock-power dissipation

q Faster switching speeds§ reduced load capacitance due to lower input capacitance (Cin)§ reduced load capacitance due to smaller output loading (Cout)§ no Isc, so all the current provided by PDN goes into discharging CL

EE1417

Properties of Dynamic GatesProperties of Dynamic Gatesq Overall power dissipation usually higher than static CMOS§ no static current path ever exists between VDD and GND (including

Psc)§ higher transition probabilities§ extra load on Clk -> higher dynamic power consumption

q Needs a precharge/evaluate clock

EE1418

Issues in Dynamic Design 1: Issues in Dynamic Design 1: Charge LeakageCharge Leakage

CL

Clk

ClkOut

A

Mp

Me

Leakage sources

CLK

VOut

Precharge

Evaluate

Dominant component is subthreshold current.Dynamic circuits require a minimal clock rate => unattractive for low speed products such as watches, hearing aids..etc.Note: PMOS leakage counteracts leakage of PDN. Output voltage is set by resistive divider composed of pull-down and pull-up paths.

EE1419

Solution to Charge LeakageSolution to Charge Leakage

CL

Clk

Clk

Me

Mp

A

B

Out

Mkp

Same approach as level restorer for pass-transistor logic.Keeper is made small to allow the strong PDN to lower the Out node substantially below the switching threshold of the next gate (to reduce contention – tradeoff between speed and robustness). The feedback configuration also eliminates static power in CMOS inverter.

Keeper

EE14110

Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge Sharing

CL

Clk

Clk

CA

CB

B=0

AOut

Mp

Me

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

EE14111

Charge SharingCharge Sharing

CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=

or

∆Vout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =

∆Vout VDD

CaCa CL+----------------------

–=

case 1) if ∆Vout < VTn

case 2) if ∆Vout > VTnB = 0

Clk

X

CL

Ca

Cb

A

Out

Mp

Ma

VDD

Mb

Clk Me

Boundary condition when ∆Vout=VTnTnDD

Tn

L

a

VVV

CC

−=

EE14112

Solution to Charge RedistributionSolution to Charge Redistribution

Clk

Clk

Me

Mp

A

B

OutMkp

Clk

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

EE14113

Issues in Dynamic Design 3: Issues in Dynamic Design 3: Crosstalk & Crosstalk & BackgateBackgate CouplingCoupling

CL1

Clk

Clk

B=0

A=0

Out1Mp

Me

Out2

CL2In

Dynamic NAND Static NAND

=1 =0

A transition in the input (In) may cause the output of dynamic gate Out1 to drop due to capacitive coupling. This may cause Out2 not to drop all the way to “0” + could cause static power to be dissipated. If the voltage drop is large enough, the circuit can evaluate incorrectly.

EE14114

Cascading Dynamic GatesCascading Dynamic Gates

Clk

Clk

Out1

In

Mp

Me

Mp

Me

Clk

Clk

Out2

V

t

Clk

In

Out1

Out2∆V

VTn

When Out1 > Vtn, Out2 keeps dischargingWhen Out1 < Vtn, Out2 is left at an intermediate levelThe correct level will not be recovered, since dynamic gates rely on capacitive storage. The reduced Out2swing, reduces the noise margins and may cause malfunction.

The cascading problems arises because the outputs of each gate are precharged to “1”. Setting all the inputs to “0” during precharge addresses this concern. When doing so, all transistors in the PDN are turned off after precharge, and no inadvertent discharging of the storage capacitors can occur during evauation.

EE14115

Domino LogicDomino Logic

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PDNIn5

Me

Mp

Clk

ClkOut2

Mkp

1 → 11 → 0

0 → 00 → 1

The inverter:(a) ensures that all inputs are set to “0” at the end of the precharge phase(b) has a low impedance output, which increases the noise immunity.(c) Can be used to drive a keeper device to combat leakage and charge

redistribution.

EE14116

Why Domino?Why Domino?

Clk

Clk

Ini PDNInj

Ini

Inj

PDN Ini PDNInj

Ini PDNInj

Like falling dominos!

q Since each dynamic gate has a static inverter, only non-inverting logic can be implemented (there are ways to deal with this)

q Very high speed§ Input capacitance reduced