dsPIC33FJXXXGSXXX Data Sheet Mock-up - · PDF filedsPIC33FJXXXGSXXX Data Sheet Core: 16-bit Architecture (40 MIPS) • 64K/128K Flash • 8K/16K RAM ... • AN1279 – Offline UPS

2011 Microchip Technology Inc. Data Sheet Mock-up DS00000A-page 1

dsPIC33FJXXXGSXXXData Sheet

Core: 16-bit Architecture (40 MIPS)• 64K/128K Flash• 8K/16K RAM• -40ºC to +150ºC• 1% internal oscillator• Programmable PLL and oscillator clock sources:

- Selectable on-the-fly- Fail Safe Clock Monitor (FSCM)- Independent Watchdog Timer

• Low-power management modes• Fast wake-up and start-up

High-Efficiency Math Engine• Two 40 bit wide accumulators • Single-cycle (MAC/MPY) with dual data fetch • Single-cycle MUL plus hardware divide

High-Speed PWM (1.04 ns Resolution)• Nine PWM generators with 18 outputs• Dead Time for rising and falling edges • 1.04 ns PWM resolution for:

• PWM support for:

• Programmable Fault inputs• Flexible trigger for ADC conversions

High-Speed Analog Features• 10-bit ADC with four or two Msps conversion rate:

- Up to 24 ADC input channels- Five Sample & Holds - Up to two Successive Approximation Registers- Flexible/Independent trigger sources

• High-Speed 20 ns Comparators:- Up to four Analog Comparator modules- 10-bit DAC for each Analog Comparator- DACOUT pin to provide DAC output

• Charge Time Measurement Unit (CTMU):- Capacitive Touch support- 1 ns time measurement resolution

Packages

Input/Output• Software remappable pin functions• 5V-tolerant pins• Selectable open drain, pull-ups and pull-downs• Up to 5 mA overvoltage clamp current• Multiple external interrupts

Direct Memory Access (DMA)• 8-channel hardware DMA• UART, SPI, ADC, ECAN, IC, OC, INT0• No CPU stalls/overhead

Communication Interfaces• USB 2.0 Full-speed interface• Two UART modules (6.25 Mbps)

- Supports LIN/J2602 protocols- RS-232, RS-485, and IrDA® support

• Two 4-wire SPI modules (15 Mbps) with Audio DAC and Codec support

• Two Enhanced CAN modules (1 Mbaud) with CAN 1.2, 2.0A, and 2.0B support

• Two I2C modules (100K, 400K and 1Mbaud) with SMbus support

System Peripherals• Up to nine 16-bit and up to three 32-bit Timers/

Counters• Up to eight Input Capture modules• Up to eight Output Compare modules• Up to two Quadrature Encoder Interface (QEI) modules

Class B Compliancy Support• Class B Safety Software Library• Meets IEC 60730 specification• VDE certified

- Duty Cycle - Phase-shift- Dead-time - Frequency

- Power Factor Correction - Stepper Motors- Switch Mode Power

Supplies- Permanent Magnet

Synchronous Motors- AC Induction Motors - Brushed DC Motors- Switched Reluctance

Motors- Brushless DC Motors

Type

TQFP QFN

Pin Count 64 64

I/O Pins 53 53

Dimensions 10x10x1 mm 9x9x0.9 mm

High-Performance, 16-bit Digital Signal Controllers Feature Set Summary

dsPIC33FJXXXGSXXX

APPLICATION USES

Motor Control (dsPIC33FJXXXMCXXX)• Brushless DC Motor (BLDC) Control• Stepper Motor Control• Permanent Magnet Synchronous Motor (PMSM) Control• AC Induction Motor (ACIM) Control

Power Conversion (dsPIC33FJXXXGSXXX) • PFC - Power Factor Correction• Boost Converter• Buck Converter• DC-to-DC Converters• LLC (Inductor-Inductor-Converters)• Solar Inverters• Battery Chargers• AC-to-DC Converters• Uninterruptible Power Supply (UPS)• Renewable Power• Pure Sine Wave Inverters• HID Lighting• Fluorescent Lighting• LED Lighting

Automotive • CAN – Controller Area Network• LED Lighting• KeeLoq - Remote Keyless entry, Security Systems• LIN – Local Interconnect Network• mTouch – Capacitive & inductive touch sensing• Graphics – VGA & Monochrome • Electronic Compass system• Angular position Sensor• Capacitive Discharge Ignition

DS00000A-page 2 Data Sheet Mock-up 2011 Microchip Technology Inc.

dsPIC33FJXXXGSXXX

APPLICATION USES (CONTINUED)

Wireless & Wired Communication• MiWi Wireless Networking, P2P (i.e., point-2-point)• IrDA remotes, data links• IEEE 802.11b wireless ethernet b/g/n routers • KeeLoq - Remote Keyless entry, Security Systems• Wireless Keyboards & mouse• TCP/IP – Internet Communication• Data Encryption• Modems, DTMF Generation/Detection• Point-Of-Sales Terminals• Set Top Boxes• Fire Panels• Internet-Enabled/connected Security Systems• Smart Power, Gas & Water meters• Smart Appliances and Industrial Monitoring• HVAC• Thermostats• Internet Radio• Remote signage• Gas, smoke and chemical sensors• Patient Monitoring• Graphic touch sensitive Displays• USB drives• Power Line Communication/Modem

Audio Applications/Uses• Automatic Gain Control• Noise Suppression• Speech Recognition• Equalizer• Speech Encoding/decoding• Acoustic Echo Cancellation• Audio Recording/Playback


dsPIC33FJXXXGSXXX

MICROCHIP PRODUCT RESOURCESThis section lists software libraries and applicationnotes that may be related to thedsPIC33FJXXXGSXXX family of devices.

These libraries and/or application notes may not bewritten specifically for the dsPIC33FJXXXGSXXXdevice family, but the concepts are pertinent and couldbe used with modification and possible limitations.

Refer to the Microchip website for the most up-to-dateinformation and files by visiting www.microchip.com.

Available Software Libraries:• dsPIC® DSC Soft Modem Library• dsPIC DSC Noise Suppression Library• dsPIC DSC Acoustic Echo Cancellation Library• dsPIC DSC Line Echo Cancellation Library• dsPIC DSC Equalizer• dsPIC DSC Automatic Gain Control Library• PIC24/dsPIC DSC G.711 Speech Encoding/Decoding Library• dsPIC DSC G.726A Speech Encoding/Decoding Library• dsPIC DSC Speex Speech Encoding/Decoding Library• ADPCM and Speex (Audio) Library for PIC32 MCUs• dsPIC DSC Symmetric Key Embedded Encryption Library2• dsPIC DSC Asymmetric Key Embedded Encryption Library3• Triple DES/AES Encryption Libraries• dsPIC DSC DSP Library Included in MPLAB® C Compiler• PIC32 DSP Library Included in MPLAB C Compiler• PIC24/dsPIC DSC Floating Point Math Library Included in MPLAB C Compiler• PIC24/dsPIC DSC Fixed Point Math Library Included in MPLAB C Compiler• PIC24/dsPIC DSC Peripheral Library Included in MPLAB C Compiler• PIC32 Peripheral Library Included in MPLAB C Compiler• PIC32 Floating Point Math Library Included in MPLAB C Compiler• PIC32 CAN Library Using MCP2515 CAN Controller• Microchip Graphics Library• Microchip TCP/IP Stack• Microchip USB Framework• IEEE-802.15.4: MiWi and MiWi P2P• IEEE-802.15.4: ZigBee®, ZigBee PRO, ZigBee Smart Energy Profile Suite• Microchip FAT File System for PIC24 and PIC32 MCUs and dsPIC DSCs• FATFs File System for PIC32 MCUs• PMBus™ Stack• FATFs File System for PIC32 MCUs


http://www.microchip.com

dsPIC33FJXXXGSXXX

MICROCHIP PRODUCT RESOURCES (CONTINUED):Application Solutions:• AN851 – Serial Boot Loader for PIC32 MCUs• AN908 – Using the dsPIC30F or dsPIC33F for Vector Control of an ACIM• AN957 – Sensored BLDC Motor Control Using the dsPIC30F or dsPIC33F• AN984 – Introduction to AC Induction Motor Control Using the dsPIC30F or dsPIC33F• AN992 – Using the dsPIC30F for Sensorless BLDC Motor Control• AN1017 – Sinusoidal Control of PMSM Motors with dsPIC30F or dsPIC33F• AN1045 – File I/O Functions Using Memory Disk Drive File System Library• AN1071 – IrDA® Standard Stack• AN1078 – Sensorless Field-oriented Control for PMSM Motor• AN1083 – Sensorless BLDC Control with Back EMF Filtering Using dsPIC® DSC• AN1094 – Boot loader for dsPIC30F/33F an PIC24F/24H Devices• AN1095 – Data EEPROM Emulation for PIC24 & PIC32 MCUs and dsPIC® DSCs• AN1106 – Power Factor Correction Using dsPIC® DSC• AN1107 – HTTP Server Using BSD Socket API for PIC32MX• AN1108 – Microchip TCP/IP Stack with BSD Socket API• AN1109 – SNMP Agent Using BSD Socket API for PIC32MX• AN1111 – FTP Server Using BSD Socket API for the PIC32MX• AN1115 – Implementing Digital Lock-In Amplifiers Using the dsPIC® DSC• AN1136 – Graphics Display Solution• AN1160 – Sensorless BLDC Control with Back EMF Filtering Using a Majority Function• AN1162 – Sensorless Field Oriented Control (FOC) of an AC Induction Motor (ACIM)• AN1206 – Sensorless Field Oriented Control (FOC) of an AC Induction Motor (ACIM) Using Field

Weakening• AN1208 – Integrated Power Factor Correction (PFC) and Sensorless Field Oriented Control (FOC) System• AN1229 – Class B Safety Software Library for PIC MCUs and dsPIC® DSCs• AN1249 – ECAN™ Operation with DMA on dsPIC33F an PIC24H Devices• AN1278 – Digital Power Interleaved PFC Reference Design• AN1279 – Offline UPS Reference Design• AN1292 – Sensorless Field Oriented Control for a Permanent Magnet Synchronous Motor Using PLL

Estimator and Field Weakening• AN1299 – Single-Shunt Three-Phase Current Reconstruction Algorithm for Sensorless FOC of a PMSM• AN1307 – Stepper Motor Control with dsPIC® DSCs• AN1114, AN1207 – AC/DC Reference Design User’s Guide


dsPIC33FJXXXGSXXX

dsPIC33FJXXXGSXXX PRODUCT FAMILIESThe device names, pin coun ts, memory sizes, andperipheral availability of each device are listed inTable 1. The following pages show their pinoutdiagrams.

TABLE 1: dsPIC33FJXXXGSXXX CONTROLLER FAMILIES

Device Pins

Prog

ram

Fla

sh (K

byte

)

RA

M (K

byte

s)

Remappable Peripherals

Mot

or C

ontr

ol P

WM

10-B

it, 1

.1 M

sps

AD

C

RTC

C

I2 C™

Com

para

tors

CTM

U

I/O P

ins

Pack

ages

Rem

appa

ble

Pins

16-b

it Ti

mer

(1)

Inpu

t Cap

ture

Out

put C

ompa

re

UA

RT

Exte

rnal

Inte

rrup

ts(2

)

SPI

dsPIC33FJ16GP101 18 16 1 10 3 3 2 1 3 1 — 1 ADC,4-ch

Y 1 3 Y 13 PDIP, SOIC

20 16 1 10 3 3 2 1 3 1 — 1 ADC,4-ch

Y 1 3 Y 13 SSOP

dsPIC33FJ16GP102 28 16 1 16 3 3 2 1 3 1 — 1 ADC,6-ch

Y 1 3 Y 21 SPDIP,SOIC,SSOP,QFN

36 16 1 16 3 3 2 1 3 1 — 1 ADC,6-ch

Y 1 3 Y 21 TLA

dsPIC33FJ16MC101 20 16 1 10 3 3 2 1 3 1 6-ch 1 ADC,4-ch

Y 1 3 Y 15 PDIP,SOIC,SSOP

dsPIC33FJ16MC102 28 16 1 16 3 3 2 1 3 1 6-ch 1 ADC,6-ch

Y 1 3 Y 21 SPDIP,SOIC,SSOP,QFN

36 16 1 16 3 3 2 1 3 1 6-ch 1 ADC,6-ch

Y 1 3 Y 21 TLA

Note 1: Two out of three timers are remappable.2: Two out of three interrupts are remappable.


dsPIC33FJXXXGSXXX

Pin Diagrams

18-Pin PDIP/SOIC

dsPIC33FJ16G

P101

MCLRPGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1

VDD

VSS

PGED1/AN2/C2INA/C1INC/CTMUC/RP0(1)/CN4/RB0

TMS/SCK1/INT0/RP7(1)/CN23/RB7PGEC3/SOSCO/T1CK/CN0/RA4PGED3/TDI/SOSCI/RP4(1)/CN1/RB4

VCAP

OSCO/CLKO/CN29/RA3OSCI/CLKI/CN30/RA2 VSS

TDO/SDA1/SDI1/RP9(1)/CN21/RB9TCK/SCL1/SDO1/RP8(1)/CN22/RB8

PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1

123456789

181716151413121110

RP15(1)/CN11/RB15RTCC/RP14(1)/CN12/RB14

dsPIC33FJ16G

P101

MCLR

VSS

PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1

AVDD

AVSS


TMS/SCK1/INT0/RP7(1)/CN23/RB7PGEC3/SOSCO/T1CK/CN0/RA4PGED3/TDI/SOSCI/RP4(1)/CN1/RB4

VCAP

OSCO/CLKO/CN29/RA3OSCI/CLKI/CN30/RA2 VSS



12345678910

20191817161514131211

RP15(1)/CN11/RB15RTCC/RP14(1)/CN12/RB14VDD

20-Pin SSOPdsPIC

33FJ16GP102

MCLR

VSS

VDD


AVDD

AVSS


ASCL1/RP6(1)/CN24/RB6

PGEC3/SOSCO/T1CK/CN0/RA4PGED3/SOSCI/RP4(1)/CN1/RB4

VSSOSCO/CLKO/CN29/RA3OSCI/CLKI/CN30/RA2 VCAP

SCK1/INT0/RP7(1)/CN23/RB7


AN5/C3IND/C2IND/RP3(1)/CN7/RB3AN4/C3INC/C2INC/RP2(1)/CN6/RB2


1234567891011121314

2827262524232221201918171615

RP15(1)/CN11/RB15RTCC/RP14(1)/CN12/RB14RP13(1)/CN13/RB13RP12(1)/CN14/RB12

TDI/RP10(1)/CN16/RB10TMS/RP11(1)/CN15/RB11

ASDA1/RP5(1)/CN27/RB5

28-Pin SPDIP/SOIC/SSOP

Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the l ist of availableperipherals.

= Pins are up to 5V tolerant


dsPIC33FJXXXGSXXX

Pin Diagrams (Continued)

dsPIC33FJ16M

C101

MCLR

VSS


VDD

VSS


FLTA1(2)/SCK1/INT0/RP7(1)/CN23/RB7PGEC3/SOSCO/T1CK/CN0/RA4PGED3/SOSCI/RP4(1)/CN1/RB4

PWM1H2/RP12(1)/CN14/RB12

OSCO/CLKO/CN29/RA3OSCI/CLKI/CN30/RA2 VCAP

SDA1/SDI1/PWM1L3/RP9(1)/CN21/RB9SCL1/SDO1/PWM1H3/RP8(1)/CN22/RB8


12345678910

20191817161514131211

PWM1L1/RP15(1)/CN11/RB15PWM1H1/RTCC/RP14(1)/CN12/RB14PWM1L2/RP13(1)/CN13/RB13

20-Pin PDIP/SOIC/SSOP


2: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults”for more information on the PWM faults.

dsPIC33FJ16M

C102

MCLR

VSS

VDD


AVDD

AVSS


FLTA1(2)/ASCL1/RP6(1)/CN24/RB6

PGEC3/SOSCO/T1CK/CN0/RA4PGED3/SOSCI/RP4(1)/CN1/RB4

VSSOSCO/CLKO/CN29/RA3OSCI/CLKI/CN30/RA2 VCAP

SCK1/INT0/RP7(1)/CN23/RB7




1234567891011121314

2827262524232221201918171615

PWM1L1/RP15(1)/CN11/RB15PWM1H1/RTCC/RP14(1)/CN12/RB14PWM1L2/RP13(1)/CN13/RB13PWM1H2/RP12(1)/CN14/RB12

TDI/PWM1H3/RP10(1)/CN16/RB10TMS/PWM1L3/RP11(1)/CN15/RB11

FLTB1(2)/ASDA1/RP5(1)/CN27/RB5

28-Pin SPDIP/SOIC/SSOP



dsPIC33FJXXXGSXXX


28-Pin QFN(2)


2: The metal pad at the bottom of the device is not connected to any pins and is recommended tobe connected to VSS externally.


10 11

23

6

1

1819

2021

22

12 13 1415

87

16

17

232425262728

9

dsPIC33FJ16GP102

54

MC

LR

PG

ED

2/A

N0/

C3I

NB

/C1I

NA

/CTE

D1/

CN

2/R

A0P

GE

C2/

AN

1/C

3IN

A/C

1IN

B/C

TED

2/C

N3/

RA1

VSS

VCAP

TDO/SDA1/SDI1/RP9(1)/CN21/RB9

RP13(1)/CN13/RB13

RP12(1)/CN14/RB12

TDI/RP10(1)/CN16/RB10

TMS/RP11(1)/CN15/RB11

VSS


OSCO/CLKO/CN29/RA3OSCI/CLKI/CN30/RA2


PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1V

DD

PG

EC

3/S

OSC

O/T

1CK

/CN

0/R

A4

ASD

A1/

RP

5(1) /C

N27

/RB

5

PGE

D3/

SO

SC

I/RP

4(1) /C

N1/

RB

4

ASC

L1/R

P6(1

) /CN

24/R

B6

SCK

1/IN

T0/R

P7(1

) /CN

23/R

B7

TCK/

SCL1

/SD

O1/

RP

8(1) /C

N22

/RB

8

AVD

D

AVS

S

RP

15(1

) /CN

11/R

B15

RTC

C/R

P14(1

) /CN

12/R

B14


dsPIC33FJXXXGSXXX


28-Pin QFN(2)




10 11

23

6

1

1819

2021

22

12 13 1415

87

16

17

232425262728

9

dsPIC33FJ16MC1025

4

MC

LR

PG

ED2/

AN0/

C3I

NB

/C1I

NA

/CTE

D1/

CN

2/R

A0

PG

EC2/

AN1/

C3I

NA

/C1I

NB

/CTE

D2/

CN

3/R

A1

VSS

VCAP


PWM1L2/RP13(1)/CN13/RB13


TDI/PWM1H3/RP10(1)/CN16/RB10

TMS/PWM1L3/RP11(1)/CN15/RB11

VSS


OSCO/CLKO/CN29/RA3OSCI/CLKI/CN30/RA2


PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1V

DD

PGE

C3/

SO

SC

O/T

1CK

/CN

0/R

A4

FLTB

1(3) /A

SD

A1/

RP

5(1) /C

N27

/RB5

PG

ED3/

SOS

CI/R

P4(1

) /CN

1/R

B4

FLTA

1(3) /A

SC

L1/R

P6(1

) /CN

24/R

B6

SC

K1/

INT0

/RP

7(1) /C

N23

/RB7

TCK

/SC

L1/S

DO

1/R

P8(1

) /CN

22/R

B8

AVD

D

AVS

S

PW

M1L

1/R

P15(1

) /CN

11/R

B15

PW

M1H

1/R

TCC

/RP

14(1

) /CN

12/R

B14



dsPIC33FJXXXGSXXX


36-Pin TLA



1

dsPIC33FJ16GP102

10

33 32 31 30 29 28

2

3

4

5

6

24

23

22

21

20

19

11 12 13 14 15

N/C

PGED

2/AN

0/C

3IN

B/C

1IN

A/C

TED

1/C

N2/

RA0

PGEC

2/AN

1/C

3IN

A/C

1IN

B/C

TED

2/C

N3/

RA1

MC

LR

AVD

D

RP1

5(1) /C

N11

/RB1

5

RTC

C/R

P14(1

) /CN

12/R

B14

AVSS

N/C

N/C

VSS


RP13(1)/CN13/RB13

RP12(1)/CN14/RB12

TDI/RP10(1)/CN16/RB10

TMS/RP11(1)/CN15/RB11

VDD

VCAPVDD


PGED3/SOSCI/RP4(1)/CN1/RB4

OSCO/CLKO/CN29/RA3

AN5/C3IND/C2IND/RP3(1)/CN7/RB3

AN4/C3INC/C2INC/RP2(1)/CN6/RB2


VSS

OSCI/CLKI/CN30/RA2

N/C

(Vss

)

N/C

ASD

A1/R

P5(1

) /CN

27/R

B5

PGEC

3/SO

SCO

/T1C

K/C

N0/

RA4

ASC

L1/R

P6(1

) /CN

24/R

B6

SCK1

/INT0

/RP7

(1) /C

N23

/RB7

TCK/

SCL1

/SD

O1/

RP8

(1) /C

N22

/RB8VD

D

N/C

(VD

D)

7

8

9

343536

16 17 18

27

26

25



dsPIC33FJXXXGSXXX


36-Pin TLA




N/CPG

ED2/

AN0/

C3I

NB/

C1I

NA/

CTE

D1/

CN

2/R

A0

PGEC

2/AN

1/C

3IN

A/C

1IN

B/C

TED

2/C

N3/

RA1

MC

LR

AVD

D

PWM

1L1/

RP1

5(1) /C

N11

/RB1

5

PWM

1H1/

RTC

C/R

P14(1

) /CN

12/R

B14

AVSS

N/C

N/C

VSS


PWM1L2/RP13(1)/CN13/RB13


TDI/PWM1H3/RP10(1)/CN16/RB10

TMS/PWM1L3/RP11(1)/CN15/RB11

VDD

VCAPVDD


PGED3/SOSCI/RP4(1)/CN1/RB4

OSCO/CLKO/CN29/RA3

AN5/C3IND/C2IND/RP3(1)/CN7/RB3

AN4/C3INC/C2INC/RP2(1)/CN6/RB2


VSS

OSCI/CLKI/CN30/RA2

N/C

(Vss

)

N/C

FLTB

1(3) /A

SDA1

/RP5

(1) /C

N27

/RB5

PGEC

3/SO

SCO

/T1C

K/C

N0/

RA4

FLTA

1(3) /A

SCL1

/RP6

(1) /C

N24

/RB6

SCK1

/INT0

/RP7

(1) /C

N23

/RB7

TCK/

SCL1

/SD

O1/

RP8

(1) /C

N22

/RB8VD

D

N/C

(VD

D)

dsPIC33FJ16MC102


1

10

33 32 31 30 29 28

2

3

4

5

6

24

23

22

21

20

19

11 12 13 14 15

7

8

9

343536

16 17 18

27

26

25


dsPIC33FJXXXGSXXX

Table of ContentsApplication Uses .................................................................................................................................................................................... 2Application Uses (Continued) ................................................................................................................................................................ 3Microchip Product Resources ................................................................................................................................................................ 4Microchip Product Resources (Continued): ........................................................................................................................................... 5dsPIC33FJXXXGSXXX Product Families.............................................................................................................................................. 61.0 Device Overview ........................................................................................................................................................................ 152.0 Application Design Examples..................................................................................................................................................... 213.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 294.0 CPU............................................................................................................................................................................................ 335.0 Memory Organization ................................................................................................................................................................. 456.0 Flash Program Memory.............................................................................................................................................................. 737.0 Resets ....................................................................................................................................................................................... 778.0 Interrupt Controller ..................................................................................................................................................................... 859.0 Oscillator Configuration ............................................................................................................................................................ 11710.0 Power-Saving Features............................................................................................................................................................ 12511.0 I/O Ports ................................................................................................................................................................................... 13112.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 14913.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 15514.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 16115.0 Special Features ...................................................................................................................................................................... 17516.0 Instruction Set Summary .......................................................................................................................................................... 18317.0 Development Support............................................................................................................................................................... 19118.0 Electrical Characteristics .......................................................................................................................................................... 19519.0 DC and AC Device Characterization Graphs ........................................................................................................................... 23720.0 Packaging Information.............................................................................................................................................................. 247Appendix A: Revision History............................................................................................................................................................. 265Index ................................................................................................................................................................................................. 267The Microchip Web Site..................................................................................................................................................................... 271Customer Change Notification Service .............................................................................................................................................. 271Customer Support .............................................................................................................................................................................. 271Reader Response .............................................................................................................................................................................. 272Product Identification System ............................................................................................................................................................ 273

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Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site; http://www.microchip.com• Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products.


mailto:[email protected]



dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

1.0 DEVICE OVERVIEW

This document contains device specific information forthe dsPIC33FJXXXGSXXX Digit al Signal Controller(DSC) Devices. The dsPIC33F devices containextensive Digital Signal Processor (DSP) functionalitywith a high-performance, 16-bit microcontroller (MCU)architecture.

Figure 1-1 shows a general block diagram of the coreand peripheral modules in the dsPIC33FJXXXGSXXXfamily of devices. Table 1-1 lists the functions of thevarious pins shown in the pinout diagrams.

Note: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX devices.However, it is no t intended to be a co m-prehensive reference source. Tocomplement the information in this dat asheet, refer to the latest family referencesections of the “dsPIC33F/PIC24H FamilyReference Manual”, which are availablefrom the Microchi p website(www.microchip.com).


dsPIC33FJXXXGSXXX

FIGURE 1-1: dsPIC33FJXXXGSXXX BLOCK DIAGRAM

16

OSC1/CLKIOSC2/CLKO

VDD, VSS

TimingGeneration

MCLR

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

Brown-outReset

Precision

ReferenceBand Gap

FRC/LPRCOscillators

RegulatorVoltage

VCAP

IC1-IC3 I2C1

PORTA

InstructionDecode and

Control

PCH PCL

16

Program Counter

16-bit ALU

23

23

24

23

Instruction Reg

PCU

16 x 16W Register Array

ROM Latch

16

EA MUX

16

16

8

InterruptController

PSV and TableData AccessControl Block

StackControl Logic

LoopControlLogic

Data Latch

AddressLatch

Address Latch

Program Memory

Data Latch

L

itera

l Dat

a 16 16

16

16

Data Latch

AddressLatch

16

X RAM Y RAM

16

Y Data Bus

X Data Bus

DSP Engine

Divide Support

16

Control Signals to Various Blocks

ADC1Timers

PORTB

Address Generator Units

1-3

CNx

UART1 OC/PWM1-2

RTCC

PWM6 Ch

RemappablePins

SPI1

CTMUExternalInterrupts

1-3

Comparators1-3

Note: Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specificpins and features present on each device.


dsPIC33FJXXXGSXXX

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name PinType

BufferType PPS Description

AN0-AN5 I Analog No Analog input channels. CLKICLKO

IO

ST/CMOS

—

NoNo

External clock source input. Always associated with OSC1 pin function.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

OSC1

OSC2

I

I/O

ST/CMOS

—

No

No

Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

SOSCISOSCO

IO

ST/CMOS

—

NoNo

32.768 kHz low-power oscillator crystal input; CMOS otherwise.32.768 kHz low-power oscillator crystal output.

CN0-CN7CN11-CN16CN21-CN24CN27CN29-CN30

I STSTSTSTST

NoNoNoNoNo

Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs.

IC1-IC3 I ST Yes Capture inputs 1/2/3. OCFAOC1-OC2

IO

ST—

YesYes

Compare Fault A input (for Compare Channels 1 and 2).Compare outputs 1 through 2.

INT0INT1INT2

III

STSTST

NoYesYes

External interrupt 0.External interrupt 1.External interrupt 2.

RA0-RA4 I/O ST No PORTA is a bidirectional I/O port.RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.T1CKT2CKT3CK

III

STSTST

NoYesYes

Timer1 external clock input.Timer2 external clock input.Timer3 external clock input.

U1CTSU1RTSU1RXU1TX

IOIO

ST—ST—

YesYesYesYes

UART1 clear to send.UART1 ready to send.UART1 receive.UART1 transmit.

SCK1SDI1SDO1SS1

I/OIO

I/O

STST—ST

YesYesYesYes

Synchronous serial clock input/output for SPI1.SPI1 data in.SPI1 data out.SPI1 slave synchronization or frame pulse I/O.

SCL1SDA1ASCL1ASDA1

I/OI/OI/OI/O

STSTSTST

NoNoNoNo

Synchronous serial clock input/output for I2C1.Synchronous serial data input/output for I2C1.Alternate synchronous serial clock input/output for I2C1.Alternate synchronous serial data input/output for I2C1.

TMSTCKTDITDO

IIIO

STSTST—

NoNoNoNo

JTAG Test mode select pin.JTAG test clock input pin.JTAG test data input pin.JTAG test data output pin.

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = InputPPS = Peripheral Pin Select

Note 1: An external pull-down resistor is required for the FLTA1 pin on dsPIC33FJ16MC101 (20-pin) devices.2: The FLTB1 pin is not available on dsPIC33FJ16MC101 (20-pin) devices.3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults” for more

information on the PWM faults.


dsPIC33FJXXXGSXXX

FLTA1(1,3)

FLTB1(2,3)

PWM1L1PWM1H1PWM1L2PWM1H2PWM1L3PWM1H3

IIOOOOOO

STST——————

NoNoNoNoNoNoNoNo

PWM1 Fault A input.PWM1 Fault B input.PWM1 Low output 1PWM1 High output 1PWM1 Low output 2PWM1 High output 2PWM1 Low output 3PWM1 High output 3

RTCC O Digital No RTCC Alarm output.CTPLSCTED1CTED2

OII

DigitalAnalogAnalog

YesNoNo

CTMU Pulse Output.CTMU External Edge Input 1.CTMU External Edge Input 2.

CVREFC1INAC1INBC1INCC1INDC1OUTC2INAC2INBC2INCC2INDC2OUTC3INAC3INBC3INCC3INDC3OUT

IIIIIOIIIIOIIIIO

AnalogAnalogAnalogAnalogAnalogDigitalAnalogAnalogAnalogAnalogDigitalAnalogAnalogAnalogAnalogDigital

NoNoNoNoNoYesNoNoNoNoYesNoNoNoNoYes

Comparator Voltage Positive Reference Input.Comparator 1 Positive Input A.Comparator 1 Negative Input B.Comparator 1 Negative Input C.Comparator 1 Negative Input D.Comparator 1 Output.Comparator 2 Positive Input A.Comparator 2 Negative Input B.Comparator 2 Negative Input C.Comparator 2 Negative Input D.Comparator 2 Output.Comparator 3 Positive Input A.Comparator 3 Negative Input B.Comparator 3 Negative Input C.Comparator 3 Negative Input D.Comparator 3 Output.

PGED1PGEC1PGED2PGEC2PGED3PGEC3

I/OI

I/OI

I/OI

STSTSTSTSTST

NoNoNoNoNoNo

Data I/O pin for programming/debugging communication channel 1.Clock input pin for programming/debugging communication channel 1.Data I/O pin for programming/debugging communication channel 2.Clock input pin for programming/debugging communication channel 2.Data I/O pin for programming/debugging communication channel 3.Clock input pin for programming/debugging communication channel 3.

MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.AVDD P P No Positive supply for analog modules. This pin must be connected at all times.

For devices without this pin, this signal is connected to VDD internally.AVSS P P No Ground reference for analog modules. For devices without this pin, this signal

is connected to VSS internally.VDD P — No Positive supply for peripheral logic and I/O pins.VCAP P — No CPU logic filter capacitor connection.VSS P — No Ground reference for logic and I/O pins.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name PinType

BufferType PPS Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = InputPPS = Peripheral Pin Select

Note 1: An external pull-down resistor is required for the FLTA1 pin on dsPIC33FJ16MC101 (20-pin) devices.2: The FLTB1 pin is not available on dsPIC33FJ16MC101 (20-pin) devices.3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults” for more

information on the PWM faults.


dsPIC33FJXXXGSXXX

1.1 Referenced SourcesThis device data sheet is b ased on the followingindividual chapters of th e “dsPIC33F/PIC24H FamilyReference Manual”. These documents should beconsidered as the primary re ference for the operationof a particular module or device feature.

• Section 1. “Introduction” (DS70197)• Section 2. “CPU” (DS70204)• Section 3. “Data Memory” (DS70202)• Section 4. “Program Memory” (DS70203)• Section 5. “Flash Programming” (DS70191)• Section 6. “Oscillator” (DS39700)• Section 7. “Reset” (DS39712)• Section 8. “Reset” (DS70192)• Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196)• Section 10. “I/O Ports” (DS70193)• Section 11. “Timers” (DS70205)• Section 12. “Input Capture” (DS70198)• Section 13. “Output Compare” (DS70209)• Section 16. “Analog-to-Digital Converter (ADC)”• Section 17. “UART” (DS70188)• Section 18. “Serial Peripheral Interface (SPI)”• Section 24. “Programming and Diagnostics” (DS70207)• Section 25. “Device Configuration” (DS70194)• Section 34. “Comparator” (DS70212)• Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70310)• Section 41. “Interrupts (Part IV)” (DS70300)• Section 52. “Oscillator (Part VI)” (DS70644)• Section 55. “Charge Time Measurement Unit (CTMU)” (DS70635)

Note: To access the documents listed below,browse to the dsPIC33FJ64GS610product page of the Mi crochip web site(www.microchip.com).

In addition to p arameters, features, andother documentation, the resulting pageprovides links to the related familyreference manual sections.





http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en547034#1

http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en547034#1

dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

2.0 APPLICATION DESIGN EXAMPLES

This chapter provides circuit diagrams of ap plicationdesign examples using the dsPIC33FJXXXGSXXXfamily of devices. The following diagrams are included:

• FIGURE 2-1: “AC Power Line Data Transceiver (600-1200 Baud, Half-Duplex, ASK)”

• FIGURE 2-2: “Complete GPS with Tilt Compensated Digital Compass”

• FIGURE 2-3: “Wireless Wi-Fi Ethernet”• FIGURE 2-4: “External Data Storage”• FIGURE 2-5: “Electrically Isolated 1 Mbps,

Full-Duplex, RS-485/RS-422 Communication Circuit”

• FIGURE 2-6: “J-Type or K-Type Thermocouple Circuit”

• FIGURE 2-7: “USB UART, USB IrDA® Circuit”

• FIGURE 2-8: “CAN and LIN Transceiver Circuits”

• FIGURE 2-9: “Battery Backup Circuit”• FIGURE 2-10: “Alternate Battery Backup

Circuit”

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not inten ded to b e acomprehensive reference source. Tocomplement the information in this datasheet, refer to the “dsPIC33F/PIC24HFamily Reference Manual”. Please seethe Microchip web site(www.microchip.com) for the latestdsPIC33F/PIC24H Family ReferenceManual sections.

2: Some registers and associated bitsdescribed in this section may not beavailable on all d evices. Refer toSection 5.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.


dsPIC33FJXXXG

SXXX

DS

00000A-page 22

Data Sheet M

ock-up

2011 Microchip Technology Inc.

PANASONIC�ECQU2A473ML0.047 µF x2 250 VAC

Newport/Murata78250

100

22 µH

0.1 µF 100V 5%

1 µF

16V

5%

2 5

1 6

SA5.0A

Newport 22R47347 µH Low Rs

150k10k

0.01 µF

0.01 µF

1k 33k

BC547B

03T-CB

0.1 µF0.047 µF

+5.0V

NOTE: AGND and DGND should be separate and connected as close as possible to minus terminal of “MB110S-TP“ bridge rectifier.

FIGURE 2-1: AC POWER LINE DATA TRANSCEIVER (600-1200 BAUD, HALF-DUPLEX, ASK)

TDA5051A

7.3728MHz

27 p

F

27 p

F

2.2M

101uf

0.1uf

1uf

0.1uf

1uf

0.1uf

14

7 8

3

11

13

5912

15 1 2

CLKOUT

4

2

8 1

7

54

4 5

8

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7

3.3v

74LVC2

T45

1 µF

0.1 µF

For ea.VDD pin

dsPIC

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10�μF

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0.1 µF

10k 680

3.3v

U1RXOSC1

U1TXI/O

1 µF

0.1 µF

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2

3 6

6 3

10k

10k

IC1

20k Zero-Crossing Detection

115V

3.3V

2 11

MCP175002E/

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630 ma SLO BLOW

USES:• Appliance�control• Air�conditioning• Energy�Management• Lighting�Control• Home�Automation

2011 M

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DS

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dsPIC33FJXXXG

SXXX

FIG

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0.024�μF

0.024�μF

0.024�μF

n��SensorVDD�3.3V

10k

dsPIC

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U1RX

U1TX

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SCL1SDA1

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0�μF�Tantalum

0.1 µF

0k 680

URE 2-2: COMPLETE GPS WITH TILT COMPENSATED DIGITAL COMPASS

AGND plane should be connected as close as possible to power supply Ground Input DGND

PowerSupplyGroundInput

AGND

10�μF�

Ceramic�

Only

10�μF�

Ceramic�

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ENVREF2

SCL2SDA2

VREF1

SCL1SDA1GND

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2.2k

1.2k

8

7

6

5

3

4

2

VDD�(3.3V

10�μF�

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VOUTVINGNDGND

MCP1824ST-18021.8V31

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MCP1824ST-25022.5V31

24

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SETP

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13

170.1�μF

0.1�μF

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0.01�μF

Ferrite BeadMLB-100505-0600A-N2

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VCC

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GND

GND

TX

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ENB

1

2

5

3

8

9

10

VDD�3.3V

GPS with built-in antenna

Global Positioning System (GPS)

10k

126SEL1

SEL0

10k

711

12 VDD1

VDD2TESTAMUXGND2GND1

Tilt�/�Motion�/�Shock�/�Vibratio(±4g,�300mv/g��3�Axis�Accelerometer)

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dsPIC33FJXXXG

SXXX

DS

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Data Sheet M

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23

4

5

108

08B0�1X1T�36�F

49.9

49.9

49.9

49.9

0.1 µF

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6.8 nF

6.8 nF

49.9

49.9

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EthernetInterfaceConnector

J1J2J3J4J5J6J7J8

AD<15:0>A<14:0>

FIGURE 2-3: WIRELESS WI-FI ETHERNET

(JTAG_EN) 211

101819

Wi�Fi��802.11IEEE, 2.4�GHz

Micro

chip

MRF24W

B0MA

23 (CS#)35 (SDI)32 (SDO)34 (SCK)

33 (INT#)20 (Hibernate)16 (WP#)7 (Reset#)

3.3V(VDD)

47k

746X101473JP

25 28 30 36

17 29

I/OSDO1SDI1SCK1

INT1I/OI/OI/O

dsPIC3X�/�PIC24�/�PIC32

I/OSDO2SDI2

SCK2INT2

68010k

3.3v

0.1uf

MCLR#

VCAP

10 µFTantalum

25 MHz

27 pF27 pF

100

3.(V

3031

26

27

1514

4951505234164517184764212228

463

2 3

10 µ

F

1 µF

0.1 µ

F

CS#SDISDOSCKSPISEL / INT#RBIASPSPCFG1PSPCFG2PSPCFG3

TPOUT+TPOUT-

TPIN+

TPIN-

LEDALEDB

AD<15:0>A<14:0>

ENC624J600

Ethernet�Controller

OSC2 OSC1

1 µF

0.1 µ

F3.3V 1 62 46 29 32 23 24

VDDOSCVCAPX6

Ethernet�10/100�Mbps

3.3V(VDD)

100k

12.4k 1%

CeramicCaps

3.3V(VDD)

100k

dsPIC33FJXXXGSXXX

FIGURE 2-4: EXTERNAL DATA STORAGE

FIGURE 2-5: ELECTRICALLY ISOLATED 1 MBPS, FULL-DUPLEX, RS-485/RS-422 COMMUNICATION CIRCUIT

10k 10k 10k 10k 10k

VDD

123456789

101112

SD�or�MMC�Memory�CardDM

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SF-P

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SCK��VDDSO HOLD#SI

CS# VSS

625

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32 KbyteSRAM

23K256VDD


CS# VSS

625

1

32 KbyteSRAM

23K25687

4

87

4

64�Kbytes�SRAM

MM 10k10k

VDD VDD

dsPIC33F / PIC24H / PIC32VDD VDD

SDO2SDI2SCK2

I/OI/OI/OI/OI/O

I/O

I/OSDO1SCK1SDI1INT1I/O MCLR#


WP#CS# VSS

625

1

128 KbyteEEPROM

25LC1024VDD


WP#CS# VSS

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25LC1024

128 KbyteEEPROM

87

4

87

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256�Kbytes�EEPROM

MM 10k10k

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0.1 µF

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VDD(3.3V)

10 µFTantalum

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RO1�(Rx)RE#DEDI�(TX)

VCC1��ST1��ST2

10�uF 0.1�uF

RO2��SLO#

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10k

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Twisted�Pair�Cable

Shield

Gnd_2RS485

Gnd_1Control

TMG�240½ BAT54C

½ BAT54C

10�μF

0.1�μF

VCC2��GND2

0.1 µF

10k

680VDD (3.3V)

10 µFTantalum

VCAP�

MCLR#


dsPIC33FJXXXGSXXX

FIGURE 2-6: J-TYPE OR K-TYPE THERMOCOUPLE CIRCUIT

FIGURE 2-7: USB UART, USB IrDA® CIRCUIT

50k

50k

100

100

5.6k

5.6k

½ MCP6V07

�+

1 µF

½ MCP6V07

�+

510510

0.1 µF 0.1 µF

MAX6010A

TC1047A

MCP4161�502VDD

SDISCKCS#

321

AN0 AN1SDO1SCK1I/O

POW

POA

POB

6

5

7VREF+

AN2

VDD1 µF

dsPIC33/PIC24/PIC32

3.0V23

1VDD

123

VOUT

VOUT3.0V�Ref

3.3V

3.3V

3.3V

10 µFTantalum

MCLR/ VCAP

0.1 µF

10k 680VDD(3.3V)

IRED Anode

VCC1

TXRXSC Gnd

6.2

TFDU4100(IrDA Transceiver)

47

4.7 µF

1

6

347

0.1 µF

8

4.7 µF

3.3V(VDD)

IrDA Transceiver(Optional)

U2RX U2TX I/O

RST# VDDD- VUSBD+

OSC1

OSC2

MC

P2200

12 MHz

12345

VBUSD-D+

Ground

Shield

Mini-5-pin USB Conn

TXRXRTSCTS

U1RXU1TX

U1CTS#U1RTS# dsPIC33F / PIC24H / PIC32

3.3V(VDD)

0.1 µF

10k680MCLR#

MCLR#

10 µFTantalum

VCAP

The�MAX3232�RS232�connections�can�be�made�in�lieu�of:a)�To�MCP2200�instead�of�PICb)�To�PIC�instead�of�TFDU4100

54321

R2IN

T1OUTR1IN

T2OUTV+V- VCC

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F

0.33 µ

F

T2INR2OUTR1OUT

T1INC2+C1+

C1-C2-

UxRTS#UxCTS#UxTxUxRx

0.33 µF0.33 µF

9876

MAX3232Optional RS-232

3.3V(VDD)

GND

3.3V (VDD)


dsPIC33FJXXXGSXXX

FIGURE 2-8: CAN AND LIN TRANSCEIVER CIRCUITS

FIGURE 2-9: BATTERY BACKUP CIRCUIT

MCLR/I/O C1TX C1RX

U2TX

U2CT

S

U2RX

U2CT

S

U1TX

U1RXI/OI/O

10 µF tantalum

VCAPdsPIC33F / PIC24H / PIC32

TXERXD CS/WAKETXDVREG

VBAT

VSS

LIN

100k

VDD3.3V

1k

C = MasterNC = Slave23 µF 10 µF43V 0.1µF

10 µF

27v

9 to 12V

LINConn

MCP2021

LIN Circuit

1 µFCeramic

MCP1253

PGOOD

VIN

SHDN

C+

C-VDD (3.3V)10 µF

100k

Select

VOUT

10 µ

F

+5VVDDTXDRXDVSS

CANHCANLVREF

RS

MCP2551

12345

6789

120

CAN Circuit

10k

0.1 µF

10k

680VDD (3.3V)

+3.3VBattery-

Pwr_Fail#

33k1k

SDM40E20LC

AVSSVSS

AVDDVDD

MBRA210LT3G

CNx

dsPIC333F / PIC24H

Power Supply In3.6V

VDD Out To Board

Logic

10 µF Tantalum

VCAP


dsPIC33FJXXXG

SXXX

DS

00000A-page 28

Data Sheet M

ock-up


dsPIC33F / PIC24H

1μF

0.1μF

��

��

(��

1μF

0.1μF

�-,�-�)

"

10 µFTantalum

VCAP

FIGURE 2-10: ALTERNATE BATTERY BACKUP CIRCUIT

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dsPIC33FJXXXGSXXX

3.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS

3.1 Basic Connection RequirementsGetting started with the dsPIC33FJXXXGSXXX familyof 16-bit Digital Signal Controllers (DSCs) requiresattention to a minimal set of device pin connectionsbefore proceeding with development. The following is alist of pin names, which must always be connected:

• All VDD and VSS pins (see Section 3.2 “Decoupling Capacitors”)

• All AVDD and AVSS pins, if present on the device (regardless if ADC module is not used) (see Section 3.2 “Decoupling Capacitors”)

• VCAP (see Section 3.3 “CPU Logic Filter Capacitor Connection (VCAP)”)

• MCLR pin (see Section 3.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 3.5 “ICSP Pins”)

• OSC1 and OSC2 pins when external oscillator source is used (see Section 3.6 “External Oscillator Pins”)

3.2 Decoupling CapacitorsThe use of de coupling capacitors on every p air ofpower supply pins, such as VDD, VSS, AVDD, andAVSS is required.

Consider the following criteria when using decouplingcapacitors:

• Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used.

• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.

• Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF.

• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not inten ded to b e acomprehensive reference source. Tocomplement the information in this datasheet, refer to the “dsPIC33F/PIC24HFamily Reference Manual”. Please seethe Microchip web site(www.microchip.com) for the latestdsPIC33F/PIC24H Family ReferenceManual sections.



dsPIC33FJXXXGSXXX

FIGURE 3-1: RECOMMENDED MINIMUM CONNECTION

3.2.1 TANK CAPACITORSOn boards with power traces running longer than sixinches in length, it is suggested to use a tank capacitorfor integrated circuits including DSCs to supply a localpower source. The value of the tank capacitor shouldbe determined based on the trace resistance that con-nects the power supply source to the device, and themaximum current drawn by the device in the applica-tion. In other words, select the tank capacitor so that itmeets the acceptable voltage sag at the device. Typicalvalues range from 4.7 µF to 47 µF.

3.3 CPU Logic Filter Capacitor Connection (VCAP)

A low-ESR (< 5 Ohm s) capacitor is required on theVCAP pin, which is used to stabilize the voltageregulator output volt age. The VCAP pin must not beconnected to VDD, and must have a capacitor between4.7 µF and 10 µF, 16V connected to ground. The typecan be ceramic or t antalum. Refer to Section 18.0“Electrical Characteristics” for additionalinformation.

The placement of this capacitor should be close to theVCAP. It is reco mmended that the trace length notexceed one-quarter inch (6 mm). Refer to Section 15.2“On-Chip Voltage Regulator” for details.

3.4 Master Clear (MCLR) PinThe MCLR pin provides for tw o specific de vicefunctions:

• Device Reset• Device programming and debugging

During device programming and debugging, theresistance and capacitance that can be added to thepin must be considered. Device programmers anddebuggers drive the MCLR pin. Consequently,specific voltage levels (VIH and VIL) and fast sign altransitions must not be adversely affected. Therefore,specific values of R and C wi ll need to be adj ustedbased on the application and PCB requirements.

For example, as shown in Figure 3-2, it isrecommended that the cap acitor C, be isolated fromthe MCLR pin during programming and debuggingoperations.

Place the components shown in Figure 3-2 withinone-quarter inch (6 mm) from the MCLR pin.

FIGURE 3-2: EXAMPLE OF MCLR PIN CONNECTIONS

dsPIC33FV

DD

VS

SVDD

VSS

VSS

VDD

AVD

D

AVS

S

VD

D

VS

S

0.1 µFCeramic

0.1 µFCeramic

0.1 µFCeramic

0.1 µFCeramic

C

R

VDD

MCLR

0.1 µFCeramic

VC

AP

10

R1

10 µFTantalum

Note 1: R 10 k is recommended. A suggestedstarting value is 10 k. Ensure that the MCLRpin VIH and VIL specifications are met.

2: R1 470 will limit any current flowing intoMCLR from the exte rnal capacitor C, in theevent of MCLR pin br eakdown, due toElectrostatic Discharge (ESD) or ElectricalOverstress (EOS). Ensure that the MCLR pinVIH and VIL specifications are met.

C

R1R

VDD

MCLR

dsPIC33FJP


dsPIC33FJXXXGSXXX

3.5 ICSP PinsThe PGECx an d PGEDx p ins are u sed for In -CircuitSerial Programming™ (ICSP™) and debugging pur-poses. It is recommended to keep the trace lengthbetween the ICSP connector and the ICSP pins on thedevice as short as possible. If the ICSP connector isexpected to experience an ESD event, a series resistoris recommended, with the value in the range of a fewtens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes, and capacitors on thePGECx and PGEDx pins are not recommended as theywill interfere with the programmer/debugger communi-cations to the device. If such discrete components arean application requirement, they should be removedfrom the circuit durin g programming and debugging.Alternately, refer to the AC/DC characteristics and tim-ing requirements information in the “Flash Program-ming Specification for dsPIC33F Families with VolatileConfiguration Bits” for information on capacitive load-ing limits and pin input voltage high (VIH) and input low(VIL) requirements.

Ensure that the “Communication Channel Select” (i.e.,PGECx/PGEDx pins) programmed into the de vicematches the physical con nections for the ICSP toMPLAB® ICD 2, MPLAB ICD 3, or MPLAB REALICE™.

For more information on ICD 2, ICD 3, and REAL ICEconnection requirements, refer to the followingdocuments that are available on the Microchip website.

• “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” DS51331

• “Using MPLAB® ICD 2” (poster) DS51265• “MPLAB® ICD 2 Design Advisory” DS51566• “Using MPLAB® ICD 3” (poster) DS51765• “MPLAB® ICD 3 Design Advisory” DS51764• “MPLAB® REAL ICE™ In-Circuit Debugger

User’s Guide” DS51616• “Using MPLAB® REAL ICE™” (poster) DS51749

3.6 External Oscillator PinsMany DSCs have options for at least two oscillators: ahigh-frequency primary oscillator and a low-frequencysecondary oscillator (refer to Section 9.0 “OscillatorConfiguration” for details).

The oscillator circuit should be placed on the sameside of the board as the device . Also, place theoscillator circuit close to the respective oscillator pins,not exceeding one-half inch (12 mm) distancebetween them. The load capacitors should be placednext to the oscillator itself, on the same side of theboard. Use a grounded copper pour around theoscillator circuit to i solate them from surrou ndingcircuits. The grounded copper pour should be routeddirectly to the MCU g round. Do not run any signaltraces or power traces inside the ground pour. Also, ifusing a two-side d board, avoid any traces on theother side of the b oard where the crystal is placed. Asuggested layout is shown in Figure 3-3.

FIGURE 3-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT

13Main Oscillator

Guard Ring

Guard Trace

SecondaryOscillator

14

15

16

17

18

19

20


dsPIC33FJXXXGSXXX

3.7 Oscillator Value Conditions on Device Start-up

If the PLL of the t arget device is enab led andconfigured for the device start-up oscillator, themaximum oscillator source frequency must be limitedto 4 MHz < FIN < 8 MHz (for MSPLL mode) or 3 MHz <FIN < 8 MHz (fo r ECPLL mode) to comply with de vicePLL start-up conditions. HSPLL mode is not supported.This means that if the external oscillator frequency isoutside this range, the application must start-up in theFRC mode first. The fixed PLL settings of 4x after aPOR with an oscillator frequency outside this range willviolate the device operating speed.

Once the device powers up, the application firmwarecan enable the PLL, and then perform a clock switch tothe Oscillator + PLL clock source. Note that clockswitching must be enabled in the device Configurationword.

3.8 Configuration of Analog and Digital Pins During ICSP Operations

If MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICEin-circuit emulator is sele cted as a deb ugger, itautomatically initializes all of the A/D input pins (ANx)as “digital” pins, by setting all bits in the AD1PCFGLregister.

The bits in the register that correspond to the A/D pinsthat are initialized by MPLAB ICD 2, MPLAB ICD 3, orMPLAB REAL ICE in-circuit emulator, must not becleared by th e user app lication firmware; otherwise,communication errors will result between the debuggerand the device.

If your application needs to use certain A/D pins asanalog input pins during the debug session, the userapplication must clear the corresponding bits in th eAD1PCFGL register during initialization of the ADCmodule.

When MPLAB ICD 2, MPLAB ICD 3, or MPLAB REALICE in-circuit emulator is used as a prog rammer, theuser application firmware must correctly configure theAD1PCFGL register. Automatic initialization of thisregister is only done during debugger operation.Failure to correctly configure the register(s) will result inall A/D pins being recognized as analog input pins,resulting in the port va lue being read as a lo gic ‘0’,which may affect user application functionality.

3.9 Unused I/OsUnused I/O pins should be configured as outputs anddriven to a logic-low state.

Alternately, connect a 1k to 10k resistor between VSSand unused pins.


dsPIC33FJXXXGSXXX

4.0 CPU

The dsPIC33FJXXXGSXXX CPU module has a 16-bit(data) modified Harvard architecture with an enhancedinstruction set, including significant support for DSP.The CPU has a 24-bit instruction word with a variablelength opcode field. The Program Counter (PC) is23 bits wide and addresses up to 4M x 24 bits of userprogram memory space. The actual amount of programmemory implemented varies by device. A single-cycleinstruction prefetch mechanism is used to help main-tain throughput and provides predictable execution. Allinstructions execute in a single cycle, with the excep-tion of instructions that change the program flow, thedouble-word move (MOV.D) instruction and the t ableinstructions. Overhead-free program loop constructsare supported using the DO and REPEAT instructions,both of which are interruptible at any point.The dsPIC33FJXXXGSXXX devices have sixteen, 16-bit working registers in the programmer’s model. Eachof the working registers can serve as a data, address,or address offset register. The 16th working register(W15) operates as a sof tware Stack Pointer (SP) forinterrupts and calls.There are two classes o f instruction in thedsPIC33FJXXXGSXXX devices: MCU and DSP. Thesetwo instruction classes are seamlessly integrated into asingle CPU. Th e instruction set includes manyaddressing modes and is designed for optimum C com-piler efficiency. For most instructions,dsPIC33FJXXXGSXXX devices are capable of execut-ing a data (or program data) memory read, a workin gregister (data) read, a data memory write , and aprogram (instruction) memory read per i nstructioncycle. As a result, three parameter instructions can besupported, allowing A + B = C operations to beexecuted in a single cycle.A block diagram of the CPU is shown in Figure 4-1, andthe programmer’s model for thedsPIC33FJXXXGSXXX is shown in Figure 4-2.

4.1 Data Addressing OverviewThe data space can be ad dressed as 32K words or64 Kbytes and is split into two blocks, referred to as Xand Y data memory. Each memory block has it s ownindependent Address Generation Unit (AGU ). TheMCU class of instructions operates solely through theX memory AGU, which accesses the entire memorymap as one linear data space. Certain DSP instructionsoperate through the X a nd Y AGUs to suppo rt dualoperand reads, wh ich splits the data address spaceinto two parts. The X and Y data space boundary isdevice-specific.Overhead-free circular buffers (Modulo Addressingmode) are supported in both X and Y address spaces.The Modulo Addressing removes the sof twareboundary checking overhead for DSP algo rithms.Furthermore, the X AGU circula r addressing can beused with any of the MCU class of instructions. The XAGU also supports Bit-Reversed Addressing to greatlysimplify input or output data reordering for radix-2 FFTalgorithms.The upper 32 Kbytes of the data space memory mapcan optionally be mapped into program space at any16K program word b oundary defined by th e 8-bitProgram Space Visibility Page (PSVPAG) register. Theprogram-to-data-space mapping feature lets anyinstruction access program space as if it were dataspace.

4.2 DSP Engine OverviewThe DSP engine features a high-speed 17-bit by 17-bitmultiplier, a 40-bit ALU, two 40-b it saturatingaccumulators, and a 40-bit bidirectional barrel shif ter.The barrel shifter is capable of shifting a 40-bit value upto 16 bits right or left, in a single cycle. The DSP instruc-tions operate seamlessly with all other instructions andhave been designed for optimal real-time performance.The MAC instruction and other associated instructionscan concurrently fetch two data operands from mem-ory, while multiplying two W registers and accumulatingand optionally saturating the result in the same cycle.This instruction functionality requires that the RAM dataspace be split for these in structions and linear for allothers. Data space partitioning is achieved in a trans-parent and flexible manner through dedicating certainworking registers to each address space.

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not inten ded to b e acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 2. “CPU”(DS70204) in the “dsPIC33F/PIC24HFamily Reference Manual”, which isavailable from the Microch ip web site(www.microchip.com).



dsPIC33FJXXXGSXXX

4.3 Special MCU FeaturesThe dsPIC33FJXXXGSXXX features a 17-bit by 17-bitsingle-cycle multiplier that is shared by both the MCUALU and DSP e ngine. The multiplier can performsigned, unsigned and mixed-sign multiplication. Usinga 17-bit by 17-b it multiplier for 16-bit by 1 6-bitmultiplication not only allows you to perform mixed-signmultiplication, it also achieves accurate result s forspecial operations, such as (-1.0) x (-1.0).

The dsPIC33FJXXXGSXXX supports 16/16 and 32/16divide operations, both fractional and integer. All divideinstructions are iterativ e operations. They must beexecuted within a REPEAT loop, resulting in a tot alexecution time of 19 inst ruction cycles. The divideoperation can be interrupt ed during any of those19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bitleft or right shift in a single cycle. The barrel shifter canbe used by both MCU and DSP instructions.

FIGURE 4-1: dsPIC33FJXXXGSXXX CPU CORE BLOCK DIAGRAM

InstructionDecode and

Control

PCH PCLProgram Counter

16-bit ALU

24

23

Instruction Reg

PCU

16 x 16W Register Array

ROM Latch

EA MUX

InterruptController

StackControlLogic

LoopControlLogic

Data Latch

AddressLatch

Control Signalsto Various Blocks

L

itera

l Dat

a

16 16

16

To Peripheral Modules

Data Latch

AddressLatch

16

X RAM Y RAM

Address Generator Units

16

Y Data Bus

X Data Bus

DSP Engine

Divide Support

16

16

23

23

168

PSV and TableData AccessControl Block

16

16

16

16

Program Memory

Data Latch

Address Latch


dsPIC33FJXXXGSXXX

FIGURE 4-2: dsPIC33FJXXXGSXXX PROGRAMMER’S MODEL

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP OperandRegisters

W1

W2

W3

W4

W5

W6W7

W8

W9

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP AddressRegisters

AD39 AD0AD31

DSPAccumulators

ACCA

ACCB

7 0Program Space Visibility Page Address

Z

0

OA OB SA SB

RCOUNT15 0

REPEAT Loop Counter

DCOUNT15 0

DO Loop Counter

DOSTART 22 0

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End AddressDOEND 22

C


dsPIC33FJXXXGSXXX

4.4 CPU Control Registers

REGISTER 4-1: SR: CPU STATUS REGISTER

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0OA OB SA(1) SB(1) OAB SAB DA DC

bit 15 bit 8

R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL<2:0>(2) RA N OV Z C

bit 7 bit 0

Legend:C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’S = Set only bit W = Writable bit -n = Value at POR‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow Status bit1 = Accumulator A overflowed0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow Status bit1 = Accumulator B overflowed0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1)

1 = Accumulator A is saturated or has been saturated at some time0 = Accumulator A is not saturated

bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1)

1 = Accumulator B is saturated or has been saturated at some time0 = Accumulator B is not saturated

bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit1 = Accumulators A or B have overflowed0 = Neither Accumulators A or B have overflowed

bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit1 = Accumulators A or B are saturated or have been saturated at some time in the past0 = Neither Accumulator A or B are saturatedThis bit may be read or cleared (not set). Clearing this bit will clear SA and SB.

bit 9 DA: DO Loop Active bit1 = DO loop in progress0 = DO loop not in progress

bit 8 DC: MCU ALU Half Carry/Borrow bit1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

Note 1: This bit can be read or cleared (not set).2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).


dsPIC33FJXXXGSXXX

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled110 = CPU Interrupt Priority Level is 6 (14)101 = CPU Interrupt Priority Level is 5 (13)100 = CPU Interrupt Priority Level is 4 (12)011 = CPU Interrupt Priority Level is 3 (11)010 = CPU Interrupt Priority Level is 2 (10)001 = CPU Interrupt Priority Level is 1 (9)000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit1 = REPEAT loop in progress0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit1 = Result was negative0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bitThis bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude thatcauses the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation)0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit1 = An operation that affects the Z bit has set it at some time in the past0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow bit1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

REGISTER 4-1: SR: CPU STATUS REGISTER (CONTINUED)

Note 1: This bit can be read or cleared (not set).2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).


dsPIC33FJXXXGSXXX

REGISTER 4-2: CORCON: CORE CONTROL REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0— — — US EDT(1) DL<2:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF

bit 7 bit 0

Legend: C = Clear only bitR = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-13 Unimplemented: Read as ‘0’bit 12 US: DSP Multiply Unsigned/Signed Control bit

1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed

bit 11 EDT: Early DO Loop Termination Control bit(1)

1 = Terminate executing DO loop at end of current loop iteration0 = No effect

bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits111 = 7 DO loops active•••001 = 1 DO loop active000 = 0 DO loops active

bit 7 SATA: ACCA Saturation Enable bit1 = Accumulator A saturation enabled0 = Accumulator A saturation disabled

bit 6 SATB: ACCB Saturation Enable bit1 = Accumulator B saturation enabled0 = Accumulator B saturation disabled

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit1 = Data space write saturation enabled0 = Data space write saturation disabled

bit 4 ACCSAT: Accumulator Saturation Mode Select bit1 = 9.31 saturation (super saturation)0 = 1.31 saturation (normal saturation)

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)

1 = CPU interrupt priority level is greater than 70 = CPU interrupt priority level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit1 = Program space visible in data space0 = Program space not visible in data space

bit 1 RND: Rounding Mode Select bit1 = Biased (conventional) rounding enabled0 = Unbiased (convergent) rounding enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit1 = Integer mode enabled for DSP multiply ops0 = Fractional mode enabled for DSP multiply ops

Note 1: This bit will always read as ‘0’.2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.


dsPIC33FJXXXGSXXX

4.5 Arithmetic Logic Unit (ALU)The dsPIC33FJXXXGSXXX ALU is 16 bits wide and iscapable of add ition, subtraction, bit sh ifts, and logicoperations. Unless otherwise mentioned, arithmeticoperations are 2’s complement in nature. Dependingon the operation, the ALU can affect the values of theCarry (C), Zero (Z), Negative (N), Overflow (OV), andDigit Carry (DC) Status bits in the SR register. The Cand DC Status bits operate as Borrow and Digit Borrowbits, respectively, for subtraction operations.

The ALU can perform 8-bit or 16-bi t operations,depending on the mode of the instruction that is used.Data for the AL U operation can come from the Wregister array or dat a memory, depending on theaddressing mode of the instruction. Likewise, outputdata from the ALU can be written to the W register arrayor a data memory location.

Refer to the “16-bit MCU and DSC Programmer’s Ref-erence Manual” (DS70157) for information on the SRbits affected by each instruction.

The dsPIC33FJXXXGSXXX CPU incorporates hard-ware support for both multiplication and division. Thisincludes a dedicated hardware multiplier and supporthardware for 16-bit-divisor division.

4.5.1 MULTIPLIERUsing the high-speed 17-bit x 17-bit multiplier of th eDSP engine, the ALU sup ports unsigned, signed ormixed-sign operation in seve ral MCU mul tiplicationmodes:

• 16-bit x 16-bit signed• 16-bit x 16-bit unsigned• 16-bit signed x 5-bit (literal) unsigned• 16-bit unsigned x 16-bit unsigned• 16-bit unsigned x 5-bit (literal) unsigned• 16-bit unsigned x 16-bit signed• 8-bit unsigned x 8-bit unsigned

4.5.2 DIVIDERThe divide block supports 32-bit/16-bit and 16-bit/16-bitsigned and unsigned integer divide operations with thefollowing data sizes:

1. 32-bit signed/16-bit signed divide2. 32-bit unsigned/16-bit unsigned divide3. 16-bit signed/16-bit signed divide4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0and the remainder in W1. The 16-bit signed andunsigned DIV instructions can specify any W registerfor both the 16-bit divisor (Wn) and any W register(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.The divide algorithm takes one cycle per bit of divisor,so both 32-bit/16-bit and 16-bit/16-bit instructions takethe same number of cycles to execute.

4.6 DSP EngineThe DSP eng ine consists of a hig h-speed 17-bit x17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round andsaturation logic).

The dsPIC33FJXXXGSXXX is a single-cycle instruc-tion flow architecture; therefore, concurrent operationof the DSP engine with MCU instruction flow is not pos-sible. However, some MCU ALU and DSP engineresources can be used concurrently by the sameinstruction (e.g., ED, EDAC).

The DSP engine can also perform inherent accumula-tor-to-accumulator operations that require no additionaldata. These instructions are ADD, SUB, and NEG.

The DSP engine has options selected through bits inthe CPU Co re Control reg ister (CORCON), as listedbelow:

• Fractional or integer DSP multiply (IF)• Signed or unsigned DSP multiply (US)• Conventional or convergent rounding (RND)• Automatic saturation on/off for ACCA (SATA)• Automatic saturation on/off for ACCB (SATB)• Automatic saturation on/off for writes to data

memory (SATDW)• Accumulator Saturation mode selection (ACC-

SAT)

A block dia gram of the DSP eng ine is show n inFigure 4-3.

TABLE 4-1: DSP INSTRUCTIONS SUMMARY

Instruction Algebraic Operation

ACC Write Back

CLR A = 0 YesED A = (x – y)2 NoEDAC A = A + (x – y)2 NoMAC A = A + (x * y) YesMAC A = A + x2 NoMOVSAC No change in A YesMPY A = x * y NoMPY A = x 2 NoMPY.N A = – x * y NoMSC A = A – x * y Yes


dsPIC33FJXXXGSXXX

FIGURE 4-3: DSP ENGINE BLOCK DIAGRAM

Zero Backfill

Sign-Extend

BarrelShifter

40-bit Accumulator A40-bit Accumulator B Round

Logic

X D

ata

Bus

To/From W Array

Adder

Saturate

Negate

32

3233

16

16 16

16

40 40

4040

Saturate

Y D

ata

Bus

40

Carry/Borrow Out

Carry/Borrow In

16

40

Multiplier/Scaler17-bit


dsPIC33FJXXXGSXXX

4.6.1 MULTIPLIERThe 17-bit x 17-bit multiplier is capable of signed orunsigned operation and can multiplex its output using ascaler to support either 1.31 fractional (Q31) or 32-bitinteger results. Unsigned operands are zero-extendedinto the 17th bit of the mu ltiplier input value. Signedoperands are sign-extended into the 1 7th bit of themultiplier input value. The output of the 17-bit x 17-bitmultiplier/scaler is a 33-bit value that is sign-extendedto 40 bits. Integer data is inherently represented as asigned 2’s complement value, where the Most Signifi-cant bit (MSb) is defined as a sign bit. The range of anN-bit 2’s complement integer is -2N-1 to 2N-1 – 1.

• For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0.

• For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF).

When the multiplier is configured for fractiona lmultiplication, the data is represented as a 2’scomplement fraction, where the MSb is defined as asign bit and the radix point is implied to lie just after thesign bit (QX fo rmat). The range of an N-bit 2’scomplement fraction with this implied radix point is -1.0to (1 – 21-N). For a 16-bit fraction, the Q15 data rangeis -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0and has a p recision of 3.0 1518x10-5. In F ractionalmode, the 16 x 16 multiply operation generates a 1.31product that has a precision of 4.65661 x 10-10.

The same multiplier is u sed to support the MCUmultiply instructions, which include integer 16-bitsigned, unsigned and mixed sign multiply operations.

The MUL instruction can be directed to use byte- orword-sized operands. Byte operands will direct a 16-bitresult, and word operands will direct a 32-bit result tothe specified register(s) in the W array.

4.6.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER

The data accumulator consists of a 40 -bit adder/subtracter with automatic sign extension logic. It canselect one of two accumulators (A or B) as its pre-accumulation source an d post-accumulationdestination. For the ADD and LAC instructions, the datato be accumulated or loaded can be optionally scaledusing the barrel shifter prior to accumulation.

4.6.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optionalzero input into one side, and either true or complementdata into the other input.

• In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented).

• In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented.

The adder/subtracter generates Overflow Status bits,SA/SB and OA/OB, which are latched and reflected inthe STATUS register:

• Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block thatcontrols accumulator data saturation, if selected. Ituses the result of the adder, the Overflow Status bitsdescribed previously and the SAT<A:B>(CORCON<7:6>) and ACCSAT (CORCON<4>) modecontrol bits to determine when and to what value, tosaturate.

Six STATUS register bits support saturation andoverflow:

• OA: ACCA overflowed into guard bits • OB: ACCB overflowed into guard bits• SA: ACCA saturated (bit 31 overflow and

saturation)or

ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation)

• SB: ACCB saturated (bit 31 overflow and saturation)

orACCB overflowed into guard bits and saturated (bit 39 overflow and saturation)

• OAB: Logical OR of OA and OB• SAB: Logical OR of SA and SB

The OA and OB bits are mod ified each time datapasses through the a dder/subtracter. When set, theyindicate that the most recent operation has overflowedinto the accumula tor guard bits (bits 32 through 39).The OA and OB bits can also optionally generate anarithmetic warning trap when OA and OB are set andthe corresponding Overflow Trap Flag Enable bits(OVATE, OVBTE) in the INTCON1 register are set(refer to Section 8.0 “Interrupt Controller”). Thisallows the user application to take immediate action; forexample, to correct system gain.


dsPIC33FJXXXGSXXX

The SA and SB bit s are modi fied each time datapasses through the adder/subtracter, but can only becleared by the user application. When set, they indicatethat the accumulator has overflo wed its maximumrange (bit 31 for 32-bit saturation or bi t 39 for 40-bitsaturation) and will be saturated (if saturation isenabled). When saturation is not enabled, SA and SBdefault to bit 39 overflow, and therefore, indicate that acatastrophic overflow has occurred. If the COVTE bit inthe INTCON1 reg ister is se t, the SA and SB bits willgenerate an arithmetic warning trap when saturation isdisabled.

The Overflow and Saturation Status bits can optionallybe viewed in the STATUS Register (SR) as the logicalOR of OA and OB (in bit OAB) and the logical OR of SAand SB (in bit SAB). Programmers can check one bit inthe STATUS register to de termine whether eitheraccumulator has overflowed, or one bit to determinewhether either accumulator has saturated. T his isuseful for complex number arithmetic, which typicallyuses both accumulators.

The device sup ports three Saturatio n and Overflowmodes:

• Bit 39 Overflow and Saturation:When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 value (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides pro-tection against erroneous data or unexpected algorithm problems (such as gain calculations).

• Bit 31 Overflow and Saturation:When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally nega-tive 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set.

• Bit 39 Catastrophic Overflow:The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.

4.6.3 ACCUMULATOR ‘WRITE BACK’The MAC class of instructions (with the e xception ofMPY, MPY.N, ED, and EDAC) can optionally write arounded version of the high word (bits 31 through 16)of the accumulator which is not targeted by the instruc-tion into data space memory. The write is performedacross the X bus into combi ned X an d Y a ddressspace. The following addressing modes are supported:

• W13, Register Direct:The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction.

• [W13] + = 2, Register Indirect with Post-Increment:The rounded contents of the non-target accumu-lator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).


dsPIC33FJXXXGSXXX

4.6.3.1 Round LogicThe round logic is a combinational block that performsa conventional (biased) or convergent (unbiased)round function during an accumulator write (store). TheRound mode is determined by the state of the RND bitin the CORCON register. It gene rates a 16 -bit, 1.15data value that i s passed to the data space writesaturation logic. If rou nding is not indicated by theinstruction, a truncated 1.15 data value is stored andthe least significant word (lsw) is simply discarded.

Conventional rounding will zero-extend bit 15 of theaccumulator and will add it to the ACCxH word (bits 16through 31 of the accumulator).

• If the ACCxL word (bits 0 through 15 of the accu-mulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented.

• If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged.

A consequence of this algorithm is that over a succes-sion of random rounding operations, the value tends tobe biased slightly positive.

Convergent (or unbiased) rounding operates in thesame manner as conventional rounding, except whenACCxL equals 0x8000. In this ca se, the LeastSignificant bit (LSb), bit 16 of the accumulator, ofACCxH is examined:

• If it is ‘1’, ACCxH is incremented.• If it is ‘0’, ACCxH is not modified.

Assuming that bit 16 is e ffectively random in nature,this scheme remove s any rounding bias that mayaccumulate.

The SAC and SAC.R instructions store either atruncated (SAC), or roun ded (SAC.R) version of th econtents of the target accumulator to data memory viathe X b us, subject to data saturation (seeSection 4.6.3.2 “Data Space Write Saturation”). Forthe MAC class of instructions , the acc umulator write-back operation functions in the same manner,addressing combined MCU (X and Y) d ata spacethough the X bus. For this class of instructions, the datais always subject to rounding.

4.6.3.2 Data Space Write SaturationIn addition to adder/subtracter saturation, writes to dataspace can also be saturated, but without affecting thecontents of the source accumulator. The data spacewrite saturation logic block accepts a 16-bi t, 1.15fractional value from the round logic block as its input,together with overflow status from the original source(accumulator) and the 16-bit round adder. These inputsare combined and used to select the appropriate 1.15fractional value as output to write to d ata spacememory.

If the SATDW bit in the CORCON register is set, data(after rounding or truncation) is tested for overflow andadjusted accordingly:

• For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF.

• For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000.

The MSb of the source (bit 39) is used to determine thesign of the operand being tested.

If the SATDW bit in the CORCON register is not set, theinput data is always passed through unmodified underall conditions.

4.6.4 BARREL SHIFTERThe barrel shifter can perform up to 16-bit arithmetic orlogic right shifts, or up to 1 6-bit left shifts, in a singlecycle. The source can be either of the two DSPaccumulators or the X bus (to support multi-bit shifts ofregister or memory data).

The shifter requires a signed binary value to determineboth the magnitude (number of bits) and direction of theshift operation. A positive value shifts the operand right.A negative value shifts the operand left. A value of ‘0’does not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a40-bit result for DSP shift operations and a 16-bit resultfor MCU shift operations. Data from the X bus ispresented to the barrel shifter between bit positions 16and 31 for right shifts, and between bit positions 0 and16 for left shifts.


dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

5.0 MEMORY ORGANIZATION The dsPIC33FJXXXGSXXX architecture features sep-arate program and data memory spaces and buse s.This architecture also allows the direct access of pro-gram memory from the data space during code execu-tion.

5.1 Program Address SpaceThe program address memory space of thedsPIC33FJXXXGSXXX devices is 4M instructions. Thespace is addressable by a 24 -bit value derived eitherfrom the 23-bit Program Counter (PC) during programexecution, or from table operation or data spaceremapping as described in Section 5.6 “Interfacing

FIGURE 5-1: PROGRAM MEMORY MAP FOR dsPIC33FJXXXGSXXX DEVICES

Note: This data sheet summarizes the featuresof the dsPIC33FJX XXGSXXX family ofdevices. However, it is not intended to bea comprehensive reference source. T ocomplement the information in this dat asheet, refer to Section 3. “Data Memory”(DS70202) and Section 4. “Pro gramMemory” (DS70203) in the “dsPIC33F/PIC24H Family Reference Manual”, whichare available from the Microchip web site(www.microchip.com).

Reset Address0x000000

0x0000FE

0x000002

0x000100

Device Configuration

User ProgramFlash Memory

0x002BFC0x002BFA

(5.6K instructions)

0x800000

0xF80000Shadow Registers 0xF80017

0xF80018

DEVID (2)0xFEFFFE0xFF00000xFFFFFE

0xF7FFFE

Unimplemented(Read ‘0’s)

GOTO Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x0002000x0001FE0x000104Alternate Vector Table

ReservedInterrupt Vector Table

Con

figur

atio

n M

emor

y Sp

ace

Use

r Mem

ory

Spac

e

Flash ConfigurationWords(1)

0x002COO0x002BFE

Note 1: On reset, these bits are automatically copied into the device configuration shadow registers.


dsPIC33FJXXXGSXXX

5.1.1 PROGRAM MEMORY ORGANIZATION

The program memory sp ace is organized in w ord-addressable blocks. Although it is treated as 24 bitswide, it is more appropriate to think of each address ofthe program memory as a lower and upper word, withthe upper byte of the upper word being unimplemented.The lower word always has an even address, while theupper word has an odd address (Figure 5-2).

Program memory addresses are always word-alignedon the lower word, and addresses are incremented ordecremented by two during code execution. Thisarrangement provides compatibility with data memoryspace addressing and makes dat a in the programmemory space accessible.

5.1.2 INTERRUPT AND TRAP VECTORSAll dsPIC33FJXXXGSXXX devices reserve theaddresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Resetvector is provided to redirect code execution from thedefault value of the PC on de vice Reset to the actualstart of code. A GOTO instruction is programmed by theuser application at 0x000000, with the actual addressfor the start of code at 0x000002.

dsPIC33FJXXXGSXXX devices also have twointerrupt vector tables, located from 0x000004 to0x0000FF and 0x000100 to 0x0001FF. These vectortables allow each of the device interrupt sources to behandled by separate Interrupt Service Routines (ISRs).A more detailed discussion of the interrupt vectortables is provided in Section 8.1 “Interrupt VectorTable”.

FIGURE 5-2: PROGRAM MEMORY ORGANIZATION

0816

PC Address

0x0000000x0000020x0000040x000006

230000000000000000

00000000

00000000

Program Memory‘Phantom’ Byte

(read as ‘0’)

least significant word (lsw)most significant word (msw)

Instruction Width

0x0000010x0000030x0000050x000007

mswAddress (lsw Address)


dsPIC33FJXXXGSXXX

5.2 Data Address SpaceThe dsPIC33FJXXXGSXXX CPU has a separate 16-bit-wide data memory space. The data space isaccessed using separate Address Genera tion Units(AGUs) for re ad and write operations. The datamemory maps is shown in Figure 5-3.

All Effective Addresses (EAs) in the data memory spaceare 16 bits wide and point to bytes within the data space.This arrangement gives a data space address range of64 Kbytes or 32K words. The lower half of the datamemory space (that is, when EA<15> = 0) is used forimplemented memory addresses, while the upper half(EA<15> = 1) is rese rved for the Program S paceVisibility area (see Section 5.6.3 “Reading Data fromProgram Memory Using Program Space Visibility”).

Microchip dsPIC33FJXXXGSXXX devices implementup to 1 Kbyte of data memory. Should an EA point to alocation outside of this a rea, an all-zero word or bytewill be returned.

5.2.1 DATA SPACE WIDTHThe data memory space is organ ized in byteaddressable, 16-bit wide blocks. Data is aligned in datamemory and registers as 16-b it words, but all dataspace EAs resolve to bytes. The Least SignificantBytes (LSBs) of each word have even addresses, whilethe Most Significant Bytes (MSBs) have od daddresses.

5.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PIC ® MCUdevices and improve data space memory usageefficiency, the dsPIC33F JXXXGSXXX instruction setsupports both word and byte opera tions. As aconsequence of byte accessibility, all effective addresscalculations are internally scaled to step through word-aligned memory. For example, the core recognizes thatPost-Modified Register Indirect Addressing mode[Ws++] will result in a value of Ws + 1 for byteoperations and Ws + 2 for word operations.

Data byte reads will read the complete word thatcontains the byte, using the LSB of an y EA todetermine which byte to select. The selected byte isplaced onto the LSB o f the data path. That is, datamemory and reg isters are organized as two p arallelbyte-wide entities with shared (word) address decodingbut separate write lines. Data byte writes only write tothe corresponding side of the array or register thatmatches the byte address.

All word accesses must be aligned to an even address.Misaligned word d ata fetches are no t supported, socare must be taken when mixing byte and wordoperations, or translating from 8-bit MCU code. If amisaligned read or write is attempted, an address errortrap is generated. If the error occurred on a read, theinstruction in pro gress is comple ted. If the erroroccurred on a write, the instruction is executed but thewrite does not occur. In either case, a trap is then exe-cuted, allowing the system and/or user application toexamine the machine state prior to e xecution of theaddress Fault.

All byte loads into any W register are loaded into theLSB. The MSB is not modified.

A sign-extend instruction (SE) is provided to allow userapplications to tra nslate 8-bit signed data to 16-bitsigned values. Alternately, for 16 -bit unsigned data,user applications can clear the MSB of any W registerby executing a zero -extend (ZE) instruction on theappropriate address.

5.2.3 SFR SPACEThe first 2 Kbytes of the Near Data Space, from 0x0000to 0x07FF, is primaril y occupied by Special FunctionRegisters (SFRs). These are use d by thedsPIC33FJXXXGSXXX core and peripheral modulesfor controlling the operation of the device.

SFRs are distributed among the modules that theycontrol, and are generally grouped together by module.Much of the SFR space contains unused addresses;these are read as ‘0’.

5.2.4 NEAR DATA SPACE The 8-Kbyte are a between 0x0000 and 0x1FFF isreferred to as the ne ar data space. Locations in thisspace are directly addressable via a 13-bi t absoluteaddress field within all memory d irect instructions.Additionally, the whole data space is addressable usingMOV class of instructions, which support Memory DirectAddressing mode with a 16-bit address field, or byusing Indirect Addressing mode with a working registeras an address pointer.

Note: The actual set of peripheral features andinterrupts varies by th e device. Refer tothe corresponding device tables and pin-out diagrams for device-spec ificinformation.


dsPIC33FJXXXGSXXX

FIGURE 5-3: DATA MEMORY MAP FOR dsPIC33FJXXXGSXXX DEVICES WITH 1 KB RAM

0x0000

0x07FE

0x0BFE

0xFFFE

LSBAddress16 bits

LSbMSb

MSBAddress

0x0001

0x07FF

0xFFFF

OptionallyMappedinto ProgramMemory

0x0801 0x0800

0x0C00

2 KbyteSFR Space

1 Kbyte

SRAM Space

0x8001 0x8000

SFR Space

X Data RAM (X)

X DataUnimplemented (X)

Y Data RAM (Y)

0x09FE0x0A00

0x09FF0x0A01

0x0BFF0x0C01

0x1FFF 0x1FFE0x2001 0x2000

8 KbyteNear DataSpace


dsPIC33FJXXXGSXXX

5.2.5 X AND Y DATA SPACESThe core has two data spaces, X and Y. These dataspaces can be considered either separate (for someDSP instructions), or as one unified linear addressrange (for MCU in structions). The data spaces areaccessed using two Address Generation Units (AGUs)and separate data paths. This feature allows certaininstructions to concurrently fetch two words from RAM,thereby enabling efficient execution of DSP algorithmssuch as Finite Impulse Response (FIR) filtering andFast Fourier transform (FFT).

The X da ta space is used by all instructions andsupports all add ressing modes. X data space hasseparate read and write data buses. The X read databus is the read data path for all instructions that viewdata space as combined X and Y address space. It isalso the X data prefetch path for the dual operand DSPinstructions (MAC class).

The Y data space is used in concert with the X dataspace by th e MAC class of ins tructions (CLR, ED,EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to providetwo concurrent data read paths.

Both the X and Y da ta spaces support ModuloAddressing mode for all instructions, su bject toaddressing mode restrictions. Bit-Reversed Addressingmode is only supported for writes to X data space.

All data memory writes, including in DSP instructions,view data space as combined X and Y address space.The boundary between the X a nd Y data spaces isdevice-dependent and is not user-programmable.

All effective addresses are 16 bi ts wide and point tobytes within the data space. Therefore, the data spaceaddress range is 64 Kbytes, or 32K words, although theimplemented memory locations vary by device.


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Bit 3 Bit 2 Bit 1 Bit 0 All Resets

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

0800

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

0000

ter High Byte Register 0000

dress Pointer Register 0000

y Page Address Pointer Register 0000

xxxx

xxxx

0 xxxx

DOSTARTH<5:0> 00xx

0 xxxx

DOENDH 00xx

N OV Z C 0000

AT IPL3 PSV RND IF 0020

XWM<3:0> 0000

TABLE 5-1: CPU CORE REGISTERS MAP

SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

WREG0 0000 Working Register 0WREG1 0002 Working Register 1WREG2 0004 Working Register 2WREG3 0006 Working Register 3WREG4 0008 Working Register 4WREG5 000A Working Register 5WREG6 000C Working Register 6WREG7 000E Working Register 7WREG8 0010 Working Register 8WREG9 0012 Working Register 9WREG10 0014 Working Register 10WREG11 0016 Working Register 11WREG12 0018 Working Register 12WREG13 001A Working Register 13WREG14 001C Working Register 14WREG15 001E Working Register 15SPLIM 0020 Stack Pointer Limit RegisterACCAL 0022 Accumulator A Low Word RegisterACCAH 0024 Accumulator A High Word RegisterACCAU 0026 Accumulator A Upper Word RegisterACCBL 0028 Accumulator B Low Word RegisterACCBH 002A Accumulator B High Word RegisterACCBU 002C Accumulator B Upper Word RegisterPCL 002E Program Counter Low Word RegisterPCH 0030 — — — — — — — — Program CounTBLPAG 0032 — — — — — — — — Table Page AdPSVPAG 0034 — — — — — — — — Program Memory VisibilitRCOUNT 0036 Repeat Loop Counter RegisterDCOUNT 0038 DCOUNT<15:0>DOSTARTL 003A DOSTARTL<15:1>DOSTARTH 003C — — — — — — — — — —DOENDL 003E DOENDL<15:1>DOENDH 0040 — — — — — — — — — —SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RACORCON 0044 — — — US EDT DL<2:0> SATA SATB SATDW ACCSMODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0>Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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XM 0 xxxx

XM 1 xxxx

YM 0 xxxx

YM 1 xxxx

XB xxxx

DI 0000

TA

S Bit 3 Bit 2 Bit 1 Bit 0 All Resets

Le

ODSRT 0048 XS<15:1>ODEND 004A XE<15:1>ODSRT 004C YS<15:1>ODEND 004E YE<15:1>REV 0050 BREN XB<14:0>

SICNT 0052 — — Disable Interrupts Counter Register

BLE 5-1: CPU CORE REGISTERS MAP (CONTINUED)

FR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

gend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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MC102 DEVICES


CN3IE CN2IE CN1IE CN0IE 0000

— — — CN16IE 0000

CN3PUE CN2PUE CN1PUE CN0PUE 0000

— — — CN16PUE 0000



— — — — 0000


— — — — 0000



— — — — 0000


— — — — 0000

TABLE 5-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16SFR

NameSFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE — — — CN7IE CN6IE CN5IE CN4IE

CNEN2 0062 — CN30IE CN29IE — CN27IE — — CN24IE CN23IE CN22IE CN21IE —

CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — — — CN7PUE CN6PUE CN5PUE CN4PUE

CNPU2 006A — CN30PUE CN29PUE — CN27PUE — — CN24PUE CN23PUE CN22PUE CN21PUE —

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 5-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GP101 DEVICESSFR


CNEN1 0060 — — — CN12IE CN11IE — — — — — CN5IE CN4IE

CNEN2 0062 — CN30IE CN29IE — — — — — CN23IE CN22IE CN21IE —

CNPU1 0068 — — — CN12PUE CN11PUE — — — — — CN5PUE CN4PUE

CNPU2 006A — CN30PUE CN29PUE — — — — — CN23PUE CN22PUE CN21PUE —


TABLE 5-4: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16MC101 DEVICESSFR


CNEN1 0060 — CN14IE CN13IE CN12IE CN11IE — — — — — CN5IE CN4IE

CNEN2 0062 — CN30IE CN29IE — — — — — CN23IE CN22IE CN21IE —

CNPU1 0068 — CN14PUE CN13PUE CN12PUE CN11PUE — — — — — CN5PUE CN4PUE

CNPU2 006A — CN30PUE CN29PUE — — — — — CN23PUE CN22PUE CN21PUE —


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N Bit 3 Bit 2 Bit 1 Bit 0 AllResets

IN ADDRERR STKERR OSCFAIL — 0000

INT — INT2EP INT1EP INT0EP 0000

IFS T1IF OC1IF IC1IF INT0IF 0000

IFS CNIF CMPIF MI2C1IF SI2C1IF 0000

IFS — — — — 0000

IFS — — — — 0000

IFS — — U1EIF FLTBIF(1) 0000

IEC T1IE OC1IE IC1IE INT0IE 0000

IEC CNIE CMPIE MI2C1IE SI2C1IE 0000

IEC — — — — 0000

IEC — — — — 0000

IEC — — U1EIE FLTBIE(1) 0000

IPC — INT0IP<2:0> 4444

IPC — — — — 4440

IPC — T3IP<2:0> 4444

IPC — U1TXIP<2:0> 0044

IPC — SI2C1IP<2:0> 4444

IPC — INT1IP<2:0> 0004

IPC — — — — 0040

IPC — — — — 0040

IPC — — — — 0040

IPC — — — — 4400

IPC — FLTB1IP<2:0>(1) 0040

IPC — — — — 0040

IN NUM<6:0> 0000

LeNo

BLE 5-5: INTERRUPT CONTROLLER REGISTER MAPSFR ame

SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

TCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR

CON2 0082 ALTIVT DISI — — — — — — — — — —

0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF —

1 0086 — — INT2IF — — — — — — — — INT1IF

2 0088 — — — — — — — — — — IC3IF —

3 008A FLTA1IF RTCCIF — — — — PWM1IF(1) — — — — —

4 008C — — CTMUIF — — — — — — — — —

0 0094 — — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE —

1 0096 — — INT2IE — — — — — — — — INT1IE

2 0098 — — — — — — — — — — IC3IE —

3 009A FLTA1IE RTCCIE — — — — PWM1IE(1) — — — — —

4 009C — — CTMUIE — — — — — — — — —

0 00A4 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0>

1 00A6 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0>

2 00A8 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0>

3 00AA — — — — — — — — — AD1IP<2:0>

4 00AC — CNIP<2:0> — CMPIP<2:0> — MI2C1IP<2:0>

5 00AE — — — — — — — — — — — —

7 00B2 — — — — — — — — — INT2IP<2:0>

9 00B6 — — — — — — — — — IC3IP<2:0>

14 00C0 — — — — — — — — — PWM1IP<2:0>

15 00C2 — FLTA1IP<2:0>(1) — RTCCIP<2:0> — — — —

16 00C4 — — — — — — — — — U1EIP<2:0>

19 00CA — — — — — — — — — CTMUIP<2:0>

TTREG 00E0 — — — — ILR<3:0> — VEC

gend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.te 1: These bits are available on the dsPIC33FJ16MC101 and dsPIC33FJ16MC102 devices only.

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0000

FFFF

— TSYNC TCS — 0000

0000

xxxx

0000

FFFF

FFFF

T32 — TCS — 0000

— — TCS — 0000


xxxx

ICBNE ICM<2:0> 0000

xxxx

ICBNE ICM<2:0> 0000

xxxx

ICBNE ICM<2:0> 0000


xxxx

xxxx

OCTSEL OCM<2:0> 0000

xxxx

xxxx

OCTSEL OCM<2:0> 0000

TABLE 5-6: TIMER REGISTER MAPSFR


TMR1 0100 Timer1 Register

PR1 0102 Period Register 1

T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS<1:0>

TMR2 0106 Timer2 Register

TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only)

TMR3 010A Timer3 Register

PR2 010C Period Register 2

PR3 010E Period Register 3




TABLE 5-7: INPUT CAPTURE REGISTER MAP


IC1BUF 0140 Input 1 Capture Register

IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV

IC2BUF 0144 Input 2 Capture Register

IC2CON 0148 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV

IC3BUF 014A Input 3 Capture Register

IC3CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV


TABLE 5-8: OUTPUT COMPARE REGISTER MAP


OC1RS 0180 Output Compare 1 Secondary Register

OC1R 0182 Output Compare 1 Register

OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT

OC2RS 0186 Output Compare 2 Secondary Register

OC2R 0188 Output Compare 2 Register

OC2CON 018A — — OCSIDL — — — — — — — — OCFLT


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TAS it 2 Bit 1 Bit 0 Reset State

P1T :0> PTMOD<1:0> 0000 0000 0000 0000

P1T 0000 0000 0000 0000

P1T 0111 1111 1111 1111

P1S 0000 0000 0000 0000

PW N3L PEN2L PEN1L 0000 0000 0000 0000

PW IUE OSYNC UDIS 0000 0000 0000 0000

P1D > 0000 0000 0000 0000

P1D TS2I DTS1A DTS1I 0000 0000 0000 0000

P1F EN3 FAEN2 FAEN1 0000 0000 0000 0111

P1F EN3 FBEN2 FBEN1 0000 0000 0000 0111

P1O UT2L POUT1H POUT1L 0011 1111 0000 0000

P1D 0000 0000 0000 0000

P1D 0000 0000 0000 0000

P1D 0000 0000 0000 0000

PW 0000 0000 0000 0000

Leg

TA

SF Bit 3 Bit 2 Bit 1 Bit 0 All Resets

I2C egister 0000

I2C egister 00FF

I2C egister 0000

I2C RCEN PEN RSEN SEN 1000

I2C S R_W RBF TBF 0000

I2C 0000

I2C 0000

Leg

BLE 5-9: 6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ116MC10X DEVICESFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B

CON 01C0 PTEN — PTSIDL — — — — — PTOPS<3:0> PTCKPS<1

MR 01C2 PTDIR PWM Timer Count Value Register

PER 01C4 — PWM Time Base Period Register

ECMP 01C6 SEVTDIR PWM Special Event Compare Register

M1CON1 01C8 — — — — — PMOD3 PMOD2 PMOD1 — PEN3H PEN2H PEN1H — PE

M1CON2 01CA — — — — SEVOPS<3:0> — — — — —

TCON1 01CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0

TCON2 01CE — — — — — — — — — — DTS3A DTS3I DTS2A D

LTACON 01D0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FA

LTBCON 0120 — — FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM — — — — FB

VDCON 01D4 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L — — POUT3H POUT3L POUT2H PO

C1 01D6 PWM Duty Cycle 1 Register

C2 01D8 PWM Duty Cycle 2 Register

C3 01DA PWM Duty Cycle 3 Register

M1KEY 01DE PWM UNLOCK KEY <15:0>

end: — = unimplemented, read as ‘0’

BLE 5-10: I2C1 REGISTER MAP

R Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

1RCV 0200 — — — — — — — — Receive R

1TRN 0202 — — — — — — — — Transmit R

1BRG 0204 — — — — — — — Baud Rate Generator R

1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN

1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P

1ADD 020A — — — — — — Address Register

1MSK 020C — — — — — — Address Mask Register

end: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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BRGH PDSEL<1:0> STSEL 0000

PERR FERR OERR URXDA 0110

egister xxxx

egister 0000

0000


— — SPITBF SPIRBF 0000

SPRE<2:0> PPRE<1:0> 0000

— — FRMDLY — 0000

0000

TABLE 5-11: UART1 REGISTER MAP


U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV

U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE

U1TXREG 0224 — — — — — — — UART Transmit R

U1RXREG 0226 — — — — — — — UART Receive R

U1BRG 0228 Baud Rate Generator Prescaler


TABLE 5-12: SPI1 REGISTER MAPSFR


SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — —

SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN

SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — —

SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register


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F Bit 3 Bit 2 Bit 1 Bit 0 All Resets

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD xxxx

AD IMSAM ASAM SAMP DONE 0000

AD :0> BUFM ALTS 0000

AD :0> 0000

AD — CH123NA<1:0> CH123SA 0000

AD CH0SA<4:0> 0000

AD PCFG3 PCFG2 PCFG1 PCFG0 0000

AD CSS3 CSS2 CSS1 CSS0 0000

Leg

BLE 5-13: ADC1 REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICES

ile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

C1BUF0 0300 ADC Data Buffer 0





C1BUF5 030A ADC Data Buffer 5

C1BUF6 030C ADC Data Buffer 6

C1BUF7 030E ADC Data Buffer 7



C1BUFA 0314 ADC Data Buffer 10

C1BUFB 0316 ADC Data Buffer 11

C1BUFC 0318 ADC Data Buffer 12

C1BUFD 031A ADC Data Buffer 13

C1BUFE 031C ADC Data Buffer 14

C1BUFF 031E ADC Data Buffer 15

1CON1 0320 ADON — ADSIDL — — — FORM<1:0> SSRC<2:0> — S

1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3

1CON3 0324 ADRC — — SAMC<4:0> ADCS<7

1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — —

1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — —

1PCFGL 032C — — — — — — — — — — PCFG5 PCFG4

1CSSL 0330 — — — — — — — — — — CSS5 CSS4

end: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

xxxx

SIMSAM ASAM SAMP DONE 0000

PI<3:0> BUFM ALTS 0000

CS<7:0> 0000

— CH123NA<1:0> CH123SA 0000

CH0SA<4:0> 0000

PCFG3 PCFG2 PCFG1 PCFG0 0000

CSS3 CSS2 CSS1 CSS0 0000

TABLE 5-14: ADC1 REGISTER MAP FOR dsPIC33FJ16GP101 AND dsPIC33FJ16MC101 DEVICES

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

ADC1BUF0 0300 ADC Data Buffer 0





ADC1BUF5 030A ADC Data Buffer 5

ADC1BUF6 030C ADC Data Buffer 6

ADC1BUF7 030E ADC Data Buffer 7



ADC1BUFA 0314 ADC Data Buffer 10

ADC1BUFB 0316 ADC Data Buffer 11

ADC1BUFC 0318 ADC Data Buffer 12

ADC1BUFD 031A ADC Data Buffer 13

ADC1BUFE 031C ADC Data Buffer 14

ADC1BUFF 031E ADC Data Buffer 15

AD1CON1 0320 ADON — ADSIDL — — — FORM<1:0> SSRC<2:0> —

AD1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SM

AD1CON3 0324 ADRC — — SAMC<4:0> AD

AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — —

AD1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — —

AD1PCFGL 032C — — — — — — — — — — — —

AD1CSSL 0330 — — — — — — — — — — — —


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T


C — — — — 0000

C SEL<3:0> — — 0000

C — — — — 0000

L

T


A xxxx

A T<7:0> 0000

R xxxx

R L<7:0> 0000

L

T


P — — RTSECSEL — 0000

L

ABLE 5-15: CTMU REGISTER MAP


TMUCON1 033A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — —

TMUCON2 033C EDG1EDGE EDG1POL EDG1SEL<3:0> EDG2 EDG1 EDG2EDGE EDG2POL EDG2

TMUICON 033E ITRIM<5:0> IRNG<1:0> — — — —

egend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

ABLE 5-16: REAL-TIME CLOCK AND CALENDAR REGISTER MAP


LRMVAL 0620 Alarm Value Register Window based on APTR<1:0>

LCFGRPT 0622 ALRMEN CHIME AMASK<3:0> ALRMPTR<1:0> ARP

TCVAL 0624 RTCC Value Register Window based on RTCPTR<1:0>

CFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR<1:0> CA


ABLE 5-17: PAD CONFIGURATION REGISTER MAP


ADCFG1 02FC — — — — — — — — — — — —


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it 4 Bit 3 Bit 2 Bit 1 Bit 0 AllResets

— — C3OUT C2OUT C1OUT 0000

— CVR<3:0> 0000

REF — — CCH<1:0> 0000

SELSRCA<3:0> 0000

NEN ABEN ABNEN AAEN AANEN 0000

CFLTREN CFDIV<2:0> 0000

REF — — CCH<1:0> 0000

SELSRCA<3:0> 0000



REF — — CCH<1:0> 0000

SELSRCA<3:0> 0000




— — — — 1F00

INT2R<4:0> 001F

T2CKR<4:0> 1F1F

IC1R<4:0> 1F1F

IC3R<4:0> 001F

OCFAR<4:0> 001F

U1RXR<4:0> 1F1F

SS1R<4:0> 001F

TABLE 5-18: COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 B

CMSTAT 0650 CMSIDL — — — — C3EVT C2EVT C1EVT — — —

CVRCON 0652 — — — — — VREFSEL BGSEL<1:0> CVREN CVROE CVRR

CM1CON 0654 CON COE CPOL — — — CEVT COUT EVPOL<1:0> — C

CM1MSKSRC 0656 — — — — SELSRCC<3:0> SELSRCB<3:0>

CM1MSKCON 0658 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN AC

CM1FLTR 065A — — — — — — — — — CFSEL<2:0>

CM2CON 065C CON COE CPOL — — — CEVT COUT EVPOL<1:0> — C

CM2MSKSRC 065E — — — — SELSRCC<3:0> SELSRCB<3:0>


CM2FLTR 0662 — — — — — — — — — CFSEL<2:0>

CM3CON 0664 CON COE CPOL — — — CEVT COUT EVPOL<1:0> — C

CM3MSKSRC 0666 — — — — SELSRCC<3:0> SELSRCB<3:0>


CM3FLTR 066A — — — — — — — — — CFSEL<2:0>


TABLE 5-19: PERIPHERAL PIN SELECT INPUT REGISTER MAPFile

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

RPINR0 0680 — — — INT1R<4:0> — — — —

RPINR1 0682 — — — — — — — — — — —

RPINR3 0686 — — — T3CKR<4:0> — — —

RPINR7 068E — — — IC2R<4:0> — — —

RPINR8 0690 — — — — — — — — — — —

RPINR11 0696 — — — — — — — — — — —

RPINR18 06A4 — — — U1CTSR<4:0> — — —

RPINR21 06AA — — — — — — — — — — —


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TA 33FJ16MC102 DEVICES

N Bit 3 Bit 2 Bit 1 Bit 0 All Resets

RP RP0R<4:0> 0000

RP RP2R<4:0> 0000

RP RP4R<4:0> 0000

RP RP6R<4:0> 0000

RP RP8R<4:0> 0000

RP RP10R<4:0> 0000

RP RP12R<4:0> 0000

RP RP14R<4:0> 0000

Le

TA

N it 3 Bit 2 Bit 1 Bit 0 All Resets

RP RP0R<4:0> 0000

RP RP4R<4:0> 0000

RP — — — — 0000

RP RP8R<4:0> 0000

RP RP14R<4:0> 0000

Le

TA

N it 3 Bit 2 Bit 1 Bit 0 All Resets

RP RP0R<4:0> 0000

RP RP4R<4:0> 0000

RP — — — — 0000

RP RP8R<4:0> 0000

RP RP12R<4:0> 0000

RP RP14R<4:0> 0000

Le

BLE 5-20: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPICFile ame Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

OR0 06C0 — — — RP1R<4:0> — — —OR1 06C2 — — — RP3R<4:0> — — —OR2 06C4 — — — RP5R<4:0> — — —OR3 06C6 — — — RP7R<4:0> — — —OR4 06C8 — — — RP9R<4:0> — — —OR5 06CA — — — RP11R<4:0> — — —OR6 06CC — — — RP13R<4:0> — — —OR7 06CE — — — RP15R<4:0> — — —gend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

BLE 5-21: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GP101 DEVICESFile ame Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 B

OR0 06C0 — — — RP1R<4:0> — — —OR2 06C4 — — — — — — — — — — —OR3 06C6 — — — RP7R<4:0> — — — —OR4 06C8 — — — RP9R<4:0> — — —OR7 06CE — — — RP15R<4:0> — — —gend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

BLE 5-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16MC101 DEVICESFile ame Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 B

OR0 06C0 — — — RP1R<4:0> — — —OR2 06C4 — — — — — — — — — — —OR3 06C6 — — — RP7R<4:0> — — — —OR4 06C8 — — — RP9R<4:0> — — —OR6 06CC — — — RP13R<4:0> — — —OR7 06CE — — — RP15R<4:0> — — —gend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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TRISA3 TRISA2 TRISA1 TRISA0 001F

RA3 RA2 RA1 RA0 xxxx

LATA3 LATA2 LATA1 LATA0 xxxx

ODCA3 ODCA2 ODCA1 ODCA0 0000


4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF

RB3 RB2 RB1 RB0 xxxx

LATB3 LATB2 LATB1 LATB0 xxxx

ODCB3 ODCB2 ODCB1 ODCB0 0000


4 — — TRISB1 TRISB0 F393

— — RB1 RB0 xxxx

4 — — LATB1 LATB0 xxxx

4 — — ODCB1 ODCB0 0000


4 — — TRISB1 TRISB0 C393

— — RB1 RB0 xxxx

4 — — LATB1 LATB0 xxxx

4 — — ODCB1 ODCB0 0000

TABLE 5-23: PORTA REGISTER MAPFile


TRISA 02C0 — — — — — — — — — — — TRISA4

PORTA 02C2 — — — — — — — — — — — RA4

LATA 02C4 — — — — — — — — — — — LATA4

ODCA 02C6 — — — — — — — — — — — ODCA4


TABLE 5-24: PORTB REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICESFile


TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB

PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4

LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4

ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4


TABLE 5-25: PORTB REGISTER MAP FOR dsPIC33FJ16MC101 DEVICESFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 — — TRISB9 TRISB8 TRISB7 — — TRISBPORTB 02CA RB15 RB14 RB13 RB12 — — RB9 RB8 RB7 — — RB4LATB 02CC LATB15 LATB14 LATB13 LATB12 — — LATB9 LATB8 LATB7 — — LATBODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 — — ODCB9 ODCB8 ODCB7 — — ODCBLegend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal

TABLE 5-26: PORTB REGISTER MAP FOR dsPIC33FJ16GP101 DEVICESFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

TRISB 02C8 TRISB15 TRISB14 — — — — TRISB9 TRISB8 TRISB7 — — TRISBPORTB 02CA RB15 RB14 — — — — RB9 RB8 RB7 — — RB4LATB 02CC LATB15 LATB14 — — — — LATB9 LATB8 LATB7 — — LATBODCB 02CE ODCB15 ODCB14 — — — — ODCB9 ODCB8 ODCB7 — — ODCBLegend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal

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Fil t 3 Bit 2 Bit 1 Bit 0 All Resets

RC EP IDLE BOR POR xxxx(1)

OS F — LPOSCEN OSWEN 0300(2)

CL — — — 3040

OS TUN<5:0> 0000

LeNo

TA

Fi Bit 3 Bit 2 Bit 1 Bit 0 All Resets

NV NVMOP<3:0> 0000(1)

NV 7:0> 0000

LeNo t.

TA

Fi Bit 3 Bit 2 Bit 1 Bit 0 All Resets

PM PI1MD — — AD1MD 0000

PM — — OC2MD OC1MD 0000

PM — — — — 0000

PM — CTMUMD — — 0000

LeNo

BLE 5-27: SYSTEM CONTROL REGISTER MAP

e Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bi

ON 0740 TRAPR IOPUWR — — — — CM — EXTR SWR SWDTEN WDTO SLE

CCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK — C

KDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> — — — — —

CTUN 0748 — — — — — — — — — —

gend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.te 1: RCON register Reset values dependent on type of Reset.

2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.

BLE 5-28: NVM REGISTER MAP

le Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

MCON 0760 WR WREN WRERR — — — — — — ERASE — —

MKEY 0766 — — — — — — — — NVMKEY<

gend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.te 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Rese

BLE 5-29: PMD REGISTER MAP

le Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

D1 0770 — — T3MD T2MD T1MD — PWM1MD(1) — I2C1MD — U1MD — S

D2 0772 — — — — — IC3MD IC2MD IC1MD — — — —

D3 0774 — — — — — CMPMD RTCCMD — — — — —

D4 0776 — — — — — — — — — — — —

gend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.te 1: This bit is available on dsPIC33FJ16MC101 and dsPIC33FJ16MC102 devices only.

dsPIC33FJXXXGSXXX

5.2.6 SOFTWARE STACK

In addition to it s use a s a workin g register, the W15register in the dsPIC33FJXXXGSXXX devices is alsoused as a software Stack Pointer. The Stack Pointeralways points to the first available free word and growsfrom lower to higher addresses. It pre-decrements forstack pops and post-increments for stack pushes, asshown in Figure 5-4. For a PC push during any CALLinstruction, the MSb of the PC is zero-extended beforethe push, ensuring that the MSb is always clear.

The Stack Pointer Limit r egister (SPLIM) associa tedwith the Stack Pointer sets an upper address boundaryfor the stack. SPLIM is uninitialized at Reset. As is thecase for the S tack Pointer, SPLIM<0> is forced to ‘0’because all stack operations must be word aligned.

Whenever an EA is generated using W15 as a sourceor destination pointer, the resulting address iscompared with the value in SPLIM. If the contents ofthe Stack Pointer (W15) and the SPLIM regi ster areequal and a push operation is performed, a stack errortrap will not occur. However, the stack error trap willoccur on a subsequent push operation. For example, tocause a stack error trap when the stack grows beyondaddress 0x0C00 in RAM, initialize the SPLIM with thevalue 0x0BFE.

Similarly, a Stack Pointer underflow (stack error) trap isgenerated when the Stack Pointer address is found tobe less than 0x0800. This prevents the stack frominterfering with the SFR space.

A write to the SPLIM register should not be immediatelyfollowed by an indirect read operation using W15.

FIGURE 5-4: CALL STACK FRAME

5.2.7 DATA RAM PROTECTION FEATUREThe dsPIC33F product family supports Data RAMprotection features that enable segments of RAM to beprotected when used in co njunction with Boo t andSecure Code Segment Security. BSRAM (Secure RAMsegment for BS) is accessibl e only from the BootSegment Flash code, when enabled. SSRAM (SecureRAM segment for RAM) is accessible only from theSecure Segment Flash code, when enabled. SeeTable 5-1 for an overview of the BSRAM and SSRAMSFRs.

5.3 Instruction Addressing ModesThe addressing modes shown in Table 5-30 form thebasis of the a ddressing modes that are o ptimized tosupport the specific features of individual instructions.The addressing modes provided in the MAC class ofinstructions differ from those provided in otherinstruction types.

5.3.1 FILE REGISTER INSTRUCTIONSMost file register instructions use a 13-bit address field(f) to di rectly address data present in the first 8192bytes of data memory (near data space). Most fi leregister instructions employ a workin g register, W0,which is denoted as WREG in these instructions. Thedestination is typically either the same fi le register orWREG (with the exception of the MUL instruction),which writes the result to a register or register pair. TheMOV instruction allows additional flexibility and canaccess the entire data space.

5.3.2 MCU INSTRUCTIONSThe three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (that is,the addressing mode can only be register direct), whichis referred to as Wb. Operand 2 can be a W register,fetched from data memory, or a 5-bit literal. The resultlocation can be either a W register or a data memorylocation. The following addressing modes aresupported by MCU instructions:

• Register Direct• Register Indirect• Register Indirect Post-Modified• Register Indirect Pre-Modified• 5-bit or 10-bit Literal

Note: A PC push during exception processingconcatenates the SRL register to the MSbof the PC prior to the push.

<Free Word>

PC<15:0>000000000

015

W15 (before CALL)

W15 (after CALL)

Stac

k G

row

s To

war

dH

ighe

r Add

ress

0x0000

PC<22:16>

POP : [--W15]PUSH : [W15++]

Note: Not all instructions support all of theaddressing modes given above.Individual instructions can supportdifferent subsets of these addressingmodes.


dsPIC33FJXXXGSXXX

TABLE 5-30: FUNDAMENTAL ADDRESSING MODES SUPPORTED

5.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS

Move instructions and the DSP accumulator class ofinstructions provide a greater degree of a ddressingflexibility than other instructions. In addition to theaddressing modes supported by mo st MCUinstructions, move and accu mulator instructions alsosupport Register Indirect with Re gister OffsetAddressing mode, also referred to as Register Indexedmode.

In summary, the following addressing modes aresupported by move and accumulator instructions:

• Register Direct• Register Indirect• Register Indirect Post-modified• Register Indirect Pre-modified• Register Indirect with Register Offset (Indexed)• Register Indirect with Literal Offset• 8-bit Literal• 16-bit Literal

5.3.4 MAC INSTRUCTIONSThe dual source operand DSP instru ctions (CLR, ED,EDAC, MAC, MPY, MPY.N, MOVSAC, and MSC), alsoreferred to as MAC instructions, use a simplified set ofaddressing modes to allow the user applicatio n toeffectively manipulate the data pointers through registerindirect tables.

The two-source operand prefetch registers must bemembers of the set {W8, W9, W10, W11}. For datareads, W8 and W9 are always directed to the X RAGU,and W10 and W11 are always directed to the Y AGU.The effective addresses generated (before and aftermodification) must, therefore, be valid addresses withinX data space for W8 and W9 and Y data space for W10and W11.

In summary, the following addressing modes aresupported by the MAC class of instructions:

• Register Indirect• Register Indirect Post-Modified by 2• Register Indirect Post-Modified by 4• Register Indirect Post-Modified by 6• Register Indirect with Register Offset (Indexed)

5.3.5 OTHER INSTRUCTIONSIn addition to the addressing modes outlined previously,some instructions use literal constants of various sizes.For example, BRA (branch) instructions use 16-bit signedliterals to specify the branch destination directly, whereasthe DISI instruction uses a 14-bit unsigned literal field. Insome instructions, such as ADD Acc, the source of anoperand or result is implied by the opcode itself. Certainoperations, such as NOP, do not have any operands.

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.Register Direct The contents of a register are accessed directly.Register Indirect The contents of Wn forms the Effective Address (EA).Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented

or decremented) by a constant value.Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.Register Indirect with Register Offset (Register Indexed)

The sum of Wn and Wb forms the EA.

Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.

Note: For the MOV instructions, the addressingmode specified in the instruction can differfor the source a nd destination EA.However, the 4-bit Wb (Register Offset)field is sha red by both source anddestination (but typically only used byone).

Note: Not all instructions support all theaddressing modes given above. Individualinstructions may support different subsetsof these addressing modes.

Note: Register Indirect with Register OffsetAddressing mode is available only for W9(in X space) and W11 (in Y space).


dsPIC33FJXXXGSXXX
5.4 Modulo AddressingModulo Addressing mode is a method of providing anautomated means to support circular data buffers usinghardware. The objective is to remove th e need forsoftware to p erform data address boundary checkswhen executing tightly looped code, as is typical inmany DSP algorithms.
Modulo Addressing can operate in either data or programspace (since the data pointer mechanism is essentiallythe same for both). One circular buffer can be supportedin each of the X (which also pro vides the pointers intoprogram space) and Y data spaces. Modulo Addressingcan operate on any W register pointer. However, it is notadvisable to use W14 or W15 for Modulo Addressingsince these two registers are used as the Stack FramePointer and Stack Pointer, respectively.

In general, any particular circular buffer can be config-ured to operate in onl y one direction as there arecertain restrictions on the buffer start address (for incre-menting buffers), or end address (for decrementingbuffers), based upon the direction of the circular buffer.

The only excep tion to th e usage restrictions is forbuffers that ha ve a po wer-of-two length. As thesebuffers satisfy the start and end address criteria, theycan operate in a bidirectional mode (that is, addressboundary checks are performed on both the lower andupper address boundaries).

5.4.1 START AND END ADDRESSThe Modulo Addressing scheme requires that astarting and ending address be specified and loadedinto the 16 -bit Modulo Buffer Address registers:XMODSRT, XMODEND, YMODSRT, and YMODEND(see Table 5-1).

The length of a circular buffer is not directly specified. Itis determined by the difference between thecorresponding start and end addresses. The maximumpossible length of the circular buffer is 32 K words(64 Kbytes).

5.4.2 W ADDRESS REGISTER SELECTION

• The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select which registers will operate with Modulo Addressing.

• If XWM = 15, X RAGU and X WAGU Modulo addressing is disabled.

• If YWM = 15, Y AGU Modulo Addressing is disabled.

The X Ad dress Space Pointer W register (XWM), towhich Modulo Addressing is to be applied, is stored inMODCON<3:0> (see Table 5-1). Modulo Addressing isenabled for X data space when XWM is set to any valueother than ‘15’ and the XMODEN b it is set atMODCON<15>.

The Y Address Space Pointer W register (YWM) towhich Modulo Addressing is to be applied is stored inMODCON<7:4>. Modulo Addressing is enabled for Ydata space when YWM is set to any value other than‘15’ and the YMODEN bit is set at MODCON<14>.

FIGURE 5-5: MODULO ADDRESSING OPERATION EXAMPLE

Note: Y space Modulo Addressing EA calcula-tions assume word-sized data (LSb ofevery EA is always clear).

0x1100

0x1163

Start Addr = 0x1100End Addr = 0x1163Length = 0x0032 words

ByteAddress

MOV #0x1100, W0MOV W0, XMODSRT ;set modulo start addressMOV #0x1163, W0MOV W0, MODEND ;set modulo end addressMOV #0x8001, W0MOV W0, MODCON ;enable W1, X AGU for modulo

MOV #0x0000, W0 ;W0 holds buffer fill value

MOV #0x1110, W1 ;point W1 to buffer

DO AGAIN, #0x31 ;fill the 50 buffer locationsMOV W0, [W1++] ;fill the next locationAGAIN: INC W0, W0 ;increment the fill value


dsPIC33FJXXXGSXXX

5.4.3 MODULO ADDRESSING APPLICABILITY

Modulo Addressing can be applied to the EffectiveAddress (EA) calcu lation associated with an y Wregister. Address boundaries check for ad dressesequal to:

• The upper boundary addresses for incrementing buffers

• The lower boundary addresses for decrementing buffers

It is important to realize that the address boundariescheck for addresses less than or greater than the upper(for incrementing buffers) and lower (for decrementingbuffers) boundary addresses (not just equa l to).Address changes can, therefore, jump beyondboundaries and still be adjusted correctly.

5.5 Bit-Reversed AddressingBit-Reversed Addressing mode is intended to simplifydata reordering for rad ix-2 FFT algorithms. It issupported by the X AGU for data writes only.

The modifier, which can be a constant value or registercontents, is regarded as having its bit order reversed. Theaddress source and destination are kept in normal order.Thus, the only operand requiring reversal is the modifier.

5.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION

Bit-Reversed Addressing mode is enabled in any ofthese situations:

• BWM bits (W register selection) in the MODCON register are any value other than ‘15’ (the stack cannot be accessed using Bit-Reversed Addressing)

• The BREN bit is set in the XBREV register• The addressing mode used is Register Indirect

with Pre-Increment or Post-Increment

If the length of a bit-reversed buffer is M = 2N bytes,the last ‘N’ bits of the data buffer start address mustbe zeros.

XB<14:0> is the Bit-Reve rsed Address modi fier, or‘pivot point,’ which is typically a constant. In the case ofan FFT computation, its value is equal to half of the FFTdata buffer size.

When enabled, Bit-Reversed Addressing is executedonly for Register Indirect with Pre-Increment or Post-Increment Addressing, and word-sized data writes. Itwill not function for any other addressing mode or forbyte-sized data, and normal addresses are generatedinstead. When Bit-Reversed Addressing is active, theW Address Pointer is always added to th e addressmodifier (XB), and the offset associated with theRegister Indirect Addressing mode is ig nored. Inaddition, as word-sized data is a requirement, the LSbof the EA is ignored (and always clear).

If Bit-Reversed Addressing has already been enabledby setting the BREN (XBREV<15>) bit, a write to theXBREV register should not be immediately followed byan indirect read operation using the W register that hasbeen designated as the bit-reversed pointer.

Note: The modulo corrected effective address iswritten back to the register only when Pre-Modify or Post-Modify Addressing mode isused to compu te the e ffective address.When an address offset (such as [W7 +W2]) is used, Modulo Address correctionis performed, but the contents of theregister remain unchanged.

Note: All bit-reversed EA cal culations assumeword-sized data (LSb of eve ry EA i salways clear). The XB val ue is scaledaccordingly to generate compatible (byte)addresses.

Note: Modulo Addressing and Bit-ReversedAddressing should not be ena bledtogether. If an application attempts to doso, Bit-Reversed Addressing will assumepriority, when active, for the X WAGU, andX WAGU, Modulo Addressing will bedisabled. However, Modulo Addressing willcontinue to function in the X RAGU.


dsPIC33FJXXXGSXXX

FIGURE 5-6: BIT-REVERSED ADDRESS EXAMPLE

TABLE 5-31: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

b3 b2 b1 0

b2 b3 b4 0

Bit Locations Swapped Left-to-RightAround Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-Word, Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4b11 b10 b9 b8

b11 b10 b9 b8

b15 b14 b13 b12

b15 b14 b13 b12

Sequential Address

Pivot Point

Normal Address Bit-Reversed Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0 0 0 0 0 0 0 0 0 00 0 0 1 1 1 0 0 0 80 0 1 0 2 0 1 0 0 40 0 1 1 3 1 1 0 0 120 1 0 0 4 0 0 1 0 20 1 0 1 5 1 0 1 0 100 1 1 0 6 0 1 1 0 60 1 1 1 7 1 1 1 0 141 0 0 0 8 0 0 0 1 11 0 0 1 9 1 0 0 1 91 0 1 0 10 0 1 0 1 51 0 1 1 11 1 1 0 1 131 1 0 0 12 0 0 1 1 31 1 0 1 13 1 0 1 1 111 1 1 0 14 0 1 1 1 71 1 1 1 15 1 1 1 1 15


dsPIC33FJXXXGSXXX

5.6 Interfacing Program and Data Memory Spaces

The dsPIC33FJXXXGSXXX architecture uses a 24-bit-wide program space and a 16-bit-wide data space. Thearchitecture is also a modified Harvard scheme, mean-ing that data can also be present in the program space.To use this data successfully, it must be accessed in away that preserves the alignment of information in bothspaces.

Aside from normal executio n, thedsPIC33FJXXXGSXXX architecture provides twomethods by whi ch program space can be acce ssedduring operation:

• Using table instructions to access individual bytes, or words, anywhere in the program space

• Remapping a portion of the program space into the data space (Program Space Visibility)

Table instructions allow an application to read or writeto small areas of the program memory. This capabilitymakes the method ideal for accessing data tables thatneed to be updated periodically. It also allows accessto all bytes of th e program word. T he remappingmethod allows an application to access a large block ofdata on a read-only basis, which is ideal for lookupsfrom a large table of static data. The application canonly access the lsw of the program word.

5.6.1 ADDRESSING PROGRAM SPACESince the a ddress ranges for the data and programspaces are 16 and 24 bit s, respectively, a method isneeded to crea te a 23-bi t or 24-bit program addressfrom 16-bit data registers. The solution depends on theinterface method to be used.

For table operations, the 8-bit Table Page register(TBLPAG) is used to d efine a 32K word region withinthe program space. This is concatenated with a 16-bitEA to arrive at a full 24-bit program space address. Inthis format, the MSb of TBLPAG is used to determine ifthe operation occurs in the user memory (TBLPAG<7>= 0) or the configuration memory (TBLPAG<7> = 1).

For remapping operations, the 8 -bit Program SpaceVisibility register (PSVP AG) is used to define a16K word page in the program space. When the MSbof the EA is ‘1’, PSVPAG is concatenated with the lower15 bits of the EA to form a 23-bit program spaceaddress. Unlike table operations, this limits remappingoperations strictly to the user memory area.

Table 5-32 and Figure 5-7 show how the program EA iscreated for table operations and remapping accessesfrom the data EA.

TABLE 5-32: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type AccessSpace

Program Space Address<23> <22:16> <15> <14:1> <0>

Instruction Access(Code Execution)

User 0 PC<22:1> 0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT(Byte/Word Read/Write)

User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx

Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx

Program Space Visibility(Block Remap/Read)

User 0 PSVPAG<7:0> Data EA<14:0>(1)

0 xxxx xxxx xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>.


dsPIC33FJXXXGSXXX

FIGURE 5-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

0Program Counter

23 bits

1

PSVPAG

8 bits

EA

15 bits

Program Counter(1)

Select

TBLPAG

8 bits

EA

16 bits

Byte Select

0

0

1/0

User/Configuration

Table Operations(2)

Program Space Visibility(1)

Space Select

24 bits

23 bits

(Remapping)

1/0

0

Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces.

2: Table operations are not required to be word aligned. Table read operations are permittedin the configuration memory space.


dsPIC33FJXXXGSXXX

5.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a directmethod of reading or writing the lower word of anyaddress within the program space without goingthrough data space. The TBLRDH and TBLWTHinstructions are the only method to re ad or write theupper 8 bits of a program space word as data.

The PC is incremented by two for each succ essive24-bit program word. This allows program memoryaddresses to directly map to data space addresses.Program memory can thus be regarded as two 16-bit-wide word address spaces, residing side by side, eachwith the same addre ss range. TBLRDL and TBLWTLaccess the sp ace that contains the least sign ificantdata word. TBLRDH and TBLWTH access the space thatcontains the upper data byte.

Two table instructions are provided to move byte orword-sized (16-bit) data to and from pro gram space.Both function as either byte or word operations.

• TBLRDL (Table Read Low):- In Word mode, this instruction maps the

lower word of the program space location (P<15:0>) to a data address (D<15:0>).

- In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’.

• TBLRDH (Table Read High):- In Word mode, this instruction maps the entire

upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’.

- In Byte mode, this instruction maps the upper or lower byte of the program word to D<7:0> of the data address, in the TBLRDL instruc-tion. The data is always ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1).

In a similar fashion, two table instructions, TBLWTHand TBLWTL, are used to write indi vidual bytes orwords to a program space address. The details oftheir operation are explained in Section 6.0 “FlashProgram Memory”.

For all table operations, the area of program memoryspace to be accessed is determined by the Table Pageregister (TBLPAG). TBLPAG covers the entire programmemory space of th e device, including user a ndconfiguration spaces. When TBLPAG<7> = 0, the tablepage is located in the u ser memory sp ace. WhenTBLPAG<7> = 1, the page is located in configurationspace.

FIGURE 5-8: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

08162300000000

00000000

00000000

00000000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.W

TBLRDL.B (Wn<0> = 1)TBLRDL.B (Wn<0> = 0)

23 15 0

TBLPAG02

0x000000

0x800000

0x020000

0x030000

Program Space

The address for the table operation is determined by the data EAwithin the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid inthe user memory area.


dsPIC33FJXXXGSXXX

5.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally bemapped into any 16K word page of the program space.This option provides transparent access to store dconstant data from the data space without the need touse special instructions (such as TBLRDL andTBLRDH).

Program space access through the data space occursif the MSb o f the data space EA i s ‘1’ and programspace visibility is enabled by setting the PSV bit in theCore Control register (CORCON<2>). The location ofthe program memory space to be mapped into the dataspace is determined by the Program Space VisibilityPage register (PSVP AG). This 8-bit regi ster definesany one of 25 6 possible pages of 16K words inprogram space. In ef fect, PSVPAG functions as theupper 8 bits of the program memory address, with the15 bits of the EA function ing as the lower bits. Byincrementing the PC by 2 for each program memoryword, the lower 15 bits of data space addresses directlymap to the lower 15 bits in the corresponding programspace addresses.

Data reads to this area add a cycle to the instructionbeing executed, since two p rogram memory fetch esare required.

Although each data space address 0x8000 and highermaps directly into a corresponding program memoryaddress (see Figure 5-9), only the lower 16 bits of the

24-bit program word are used to contain the data. Theupper 8 bit s of any prog ram space location used asdata should be pro grammed with ‘1111 1111’ or‘0000 0000’ to force a NOP. This prevents possibleissues should the area of cod e ever be accidentallyexecuted.

For operations that use PSV and are executed outsidea REPEAT loop, the MOV and MOV.D instructionsrequire one instruction cycle in addition to the specifiedexecution time. All othe r instructions require twoinstruction cycles in addition to the specified executiontime.

For operations that use PSV, and are executed insidea REPEAT loop, these instances require two instructioncycles in addition to the specified execution time of theinstruction:

• Execution in the first iteration• Execution in the last iteration• Execution prior to exiting the loop due to an

interrupt• Execution upon re-entering the loop after an

interrupt is serviced

Any other iteration of the REPEAT loop will allow theinstruction using PSV to ac cess data, to execute in asingle cycle.

FIGURE 5-9: PROGRAM SPACE VISIBILITY OPERATION

Note: PSV access is temporarily disabled duringtable reads/writes.

23 15 0PSVPAGData SpaceProgram Space

0x0000

0x8000

0xFFFF

020x000000

0x800000

0x010000

0x018000

When CORCON<2> = 1 and EA<15> = 1:

The data in the page designated by PSVPAG is mapped into the upper half of the data memory space...

Data EA<14:0>

...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.

PSV Area


dsPIC33FJXXXGSXXX

6.0 FLASH PROGRAM MEMORY

The dsPIC33FJXXXGSXXX devices contain internalFlash program memory for storing and executin gapplication code. The memory is rea dable, writable,and erasable during normal operation over the entireVDD range.

Flash memory can be programmed in two ways:

• In-Circuit Serial Programming™ (ICSP™) programming capability

• Run-Time Self-Programming (RTSP)

ICSP allows a dsPIC33FJXXXGSXXX device to beserially programmed while in the end application circuit.This is done with two lines for programming clock andprogramming data (one of the alternate programmingpin pairs: PGECx/PGEDx), and three othe r lines for

power (VDD), ground (VSS) and Master Clear (MCLR).This allows users to manufacture boards with unpro-grammed devices, and then program the digital signalcontroller just before shipping the p roduct. This alsoallows the most recent firmware or a custom firmwareto be programmed.

RTSP is accomplished using TBLRD (table read) andTBLWT (table write) instructions. With RTSP, the userapplication can write program memory data in a singleprogram memory word, and erase program memory inblocks or ‘pages’ of 512 instructions (1536 bytes).

6.1 Table Instructions and Flash Programming

Regardless of the method used, all programming ofFlash memory is done with the table-read and table-write instructions. These allow direct read and writeaccess to the program memory space from the datamemory while the device is in normal operating mode.The 24-bit target address in the progr am memory isformed using bits <7:0> of the TBLPAG register and theEffective Address (EA) from a W register specified inthe table instruction, as shown in Figure 6-1.

The TBLRDL and the TBLWTL instructions are used toread or write to b its <15:0> of program memory.TBLRDL and TBLWTL can access program memory inboth Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to reador write to bits <23:16> of program memory. TBLRDHand TBLWTH can also access program memory in Wordor Byte mode.

FIGURE 6-1: ADDRESSING FOR TABLE REGISTERS

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It i s not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 5. “F lashProgramming” (DS70191) in the“dsPIC33F/PIC24H Family ReferenceManual”, which is ava ilable from theMicrochip web site (www.microchip.com).


0Program Counter

24 bits

Program Counter

TBLPAG Reg

8 bits

Working Reg EA

16 bits

Byte24-bit EA

0

1/0

Select

UsingTable Instruction

Using

User/ConfigurationSpace Select


dsPIC33FJXXXGSXXX

6.2 RTSP OperationThe dsPIC33FJXXXGSXXX Flash pr ogram memoryarray is organized into rows o f 64 instructions or 192bytes. RTSP allows the user application to erase apage of memory , which cons ists of eig ht rows (51 2instructions); and to program on e word. Table 18-12shows typical erase and programming times. The 8-row erase pages are edge-aligned from the beginningof program memory, on boundaries of 1536 bytes.

6.3 Programming OperationsA complete programming sequence is necessary forprogramming or erasing the internal Flash in RTSPmode. The processor stalls (waits) until the operation isfinished.

For erase and program times, refer to parametersDI37a and DI37b (Page Erase Time), and DI38a andDI38b (Word Write Cycle Time), in Table 18-12: “DCCharacteristics: Program Memory”.

Setting the WR bit (NVMCON<15>) starts the opera-tion, and the WR bit is automatically cleared when theoperation is finished.

6.3.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY

Programmers can program one word (24 bits) ofprogram Flash memory at a ti me. To do this, it isnecessary to erase the 8-row erase page that containsthe desired address of the location the user wants tochange.

For protection against accidental operations, the writeinitiate sequence for NVMKEY must be used to allowany erase or program operation to proceed. After theprogramming command has been executed, the userapplication must wait for the programming time un tilprogramming is complete. The two i nstructionsfollowing the start of the programming sequenceshould be NOPs.

Refer to Section 5. “Flash Programming” (DS70191)in the “dsPIC33F/PIC24H Family Reference Manual”for details and codes examples on programming usingRTSP.

6.4 Control RegistersTwo SFRs are used to read and write the programFlash memory: NVMCON and NVMKEY.

The NVMCON register (Register 6-1) controls whichblocks are to be erased, which memory type is to beprogrammed, and the start of the programming cycle.

NVMKEY is a write-only register that is used for writeprotection. To start a programming or erase sequence,the user application must consecutively write 0x55 and0xAA to the NVMKEY register . Refer to Section 6.3“Programming Operations” for further details.

Note: Performing a page erase operation on thelast page of program memory will clear theFlash Configuration words, therebyenabling code protection as a re sult.Therefore, users should avoid performingpage erase operations on the last page ofprogram memory.


dsPIC33FJXXXGSXXX

REGISTER 6-1: NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0WR WREN WRERR — — — — —

bit 15 bit 8

U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1)

— ERASE — — NVMOP<3:0>(2)

bit 7 bit 0

Legend: SO = Satiable only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control bit1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit1 = Enable Flash program/erase operations0 = Inhibit Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit1 = An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)0 = The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’bit 6 ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command0 = Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4 Unimplemented: Read as ‘0’bit 3-0 NVMOP<3:0>: NVM Operation Select bits(2)

If ERASE = 1:1111 = No operation1101 = Erase General Segment1100 = No operation0011 = No operation0010 = Memory page erase operation0001 = No operation0000 = No operation

If ERASE = 0:1111 = No operation1101 = No operation1100 = No operation0011 = Memory word program operation0010 = No operation0001 = No operation0000 = No operation

Note 1: These bits can only be reset on POR.2: All other combinations of NVMOP<3:0> are unimplemented.


dsPIC33FJXXXGSXXX

REGISTER 6-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0NVMKEY<7:0>

bit 7 bit 0

Legend: SO = Satiable only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits


dsPIC33FJXXXGSXXX

7.0 RESETS

The Reset modu le combines all Reset sources an dcontrols the device Master Reset Signal, SYSRST. Thefollowing is a list of device Reset sources:

• POR: Power-on Reset • BOR: Brown-out Reset• MCLR: Master Clear Pin Reset• SWR: RESET Instruction• WDTO: Watchdog Timer Reset• CM: Configuration Mismatch Reset • TRAPR: Trap Conflict Reset• IOPUWR: Illegal Condition Device Reset

- Illegal Opcode Reset- Uninitialized W Register Reset- Security Reset

A simplified block diagram of the Reset module isshown in Figure 7-1.

Any active source of Reset will make the SYSRST sig-nal active. On system Reset, some of the registersassociated with the CPU and peripherals are forced toa known Reset state, and some are unaffected.

All types of device Reset set a corresponding status bitin the RCON register to indicate the type of Reset (seeRegister 7-1).

All bits that are set, with the exception of the POR bit(RCON<0>), are cleared during a POR event. The userapplication can set or clear any bit at any time duringcode execution. The RCON bits only serve as statusbits. Setting a p articular Reset status bit in softwaredoes not cause a device Reset to occur.

The RCON register also has other bits associated withthe Watchdog Timer and device power-saving states.The function of these bits is discussed in other sectionsof this data sheet.

FIGURE 7-1: RESET SYSTEM BLOCK DIAGRAM

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not inten ded to b e acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 8. “R eset”(DS70192) in the “ dsPIC33F/PIC24HFamily Reference Manual”, which isavailable from the Microch ip web site(www.microchip.com).


Note: Refer to the specific peripheral section orSection 4.0 “CPU” of this data sheet forregister Reset states.

Note: The status bits in th e RCON registershould be cleared after they are read sothat the next RCON register value after adevice Reset is meaningful.

MCLR

VDD

InternalRegulator

BOR

Sleep or Idle

RESET Instruction

WDTModule

Glitch Filter

Trap ConflictIllegal Opcode

Uninitialized W Register

SYSRST

VDD RiseDetect

POR

Configuration Mismatch




dsPIC33FJXXXGSXXX

REGISTER 7-1: RCON: RESET CONTROL REGISTER(1)

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0TRAPR IOPUWR — — — — CM —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TRAPR: Trap Reset Flag bit1 = A Trap Conflict Reset has occurred0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset0 = An illegal opcode or uninitialized W Reset has not occurred

bit 13-10 Unimplemented: Read as ‘0’bit 9 CM: Configuration Mismatch Flag bit

1 = A configuration mismatch Reset has occurred0 = A configuration mismatch Reset has NOT occurred

bit 8 Unimplemented: Read as ‘0’bit 7 EXTR: External Reset (MCLR) Pin bit

1 = A Master Clear (pin) Reset has occurred0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset (Instruction) Flag bit1 = A RESET instruction has been executed0 = A RESET instruction has not been executed

bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)

1 = WDT is enabled0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out Flag bit1 = WDT time-out has occurred0 = WDT time-out has not occurred

bit 3 SLEEP: Wake-up from Sleep Flag bit1 = Device has been in Sleep mode0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up from Idle Flag bit1 = Device was in Idle mode0 = Device was not in Idle mode

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does notcause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of theSWDTEN bit setting.


dsPIC33FJXXXGSXXX

bit 1 BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

1 = A Power-on Reset has occurred0 = A Power-on Reset has not occurred

REGISTER 7-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does notcause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of theSWDTEN bit setting.


dsPIC33FJXXXGSXXX

7.1 System ResetThe dsPIC33FJXXXGSXXX family of devices have twotypes of Reset:

• Cold Reset• Warm Reset

A cold Reset is the result of a POR or a BOR. On a coldReset, the FNOSC configuration bits in the FOSCdevice configuration register selects the device clocksource.

A warm Reset is the result of all other Reset sources,including the RESET instruction. On warm Rese t, thedevice will continue to operate from the current clocksource as indicated by the Current Oscillator Selection(COSC<2:0>) bits in the Oscillator Control(OSCCON<14:12>) register.

The device is kept in a Re set state until the systempower supplies have stabilized at app ropriate levelsand the oscil lator clock is ready. The sequence inwhich this occurs is shown in Figure 7-2.

TABLE 7-1: OSCILLATOR DELAY

Oscillator Mode Oscillator Startup Delay

Oscillator Startup Timer PLL Lock Time Total Delay

FRC, FRCDIV16, FRCDIVN

TOSCD — — TOSCD

FRCPLL TOSCD — TLOCK TOSCD + TLOCK

MS TOSCD TOST — TOSCD + TOST

HS TOSCD TOST — TOSCD + TOST

EC — — — —MSPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK

ECPLL — — TLOCK TLOCK

SOSC TOSCD TOST — TOSCD + TOST

LPRC TOSCD — — TOSCD

Note 1: TOSCD = Oscillator Start-up Delay (1.1 s max for FRC, 70 s max for LPRC). Crystal Oscillator start-up times vary with crystal characteristics, load capacitance, etc.

2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 s for a 10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.

3: TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.


dsPIC33FJXXXGSXXX

FIGURE 7-2: SYSTEM RESET TIMING

Reset RunDevice Status

VDD

VPOR

VborVBOR

POR

BOR

SYSRST

TPWRT

TPOR

TBOR

Oscillator Clock

TOSCD TOST TLOCK

Time

FSCMTFSCM

1

23

4

5

6

1. POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses theVPOR threshold and the delay TPOR has elapsed.

2. BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and thedelay TBOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable.

3. PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT)after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed oper-ation. After the delay TPWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start gen-erating clock cycles.

4. Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in Table 7-1. Refer toSection 9.0 “Oscillator Configuration” for more information.

5. When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTOinstruction at the Reset address, which redirects program execution to the appropriate start-up routine.

6. The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delayTFSCM elapsed.

TABLE 7-2: OSCILLATOR DELAYSymbol Parameter Value

VPOR POR threshold 1.8V nominalTPOR POR extension time 30 s maximumVBOR BOR threshold 2.5V nominalTBOR BOR extension time 100 s maximum

TPWRT Programmable power-up time delay

0-128 ms nominal

TFSCM Fail-safe Clock Monitor Delay

900 s maximum

Note: When the device exits the Reset condi-tion (begins normal operation), thedevice operating parameters (voltage,frequency, temperature, etc.) must bewithin their o perating ranges, otherwisethe device may not function correctly. Theuser application must ensure that thedelay between the time power is firstapplied, and the time SYSRST becomesinactive, is long enough to g et alloperating parameters withinspecification.


dsPIC33FJXXXGSXXX

7.2 PORA POR circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses theVPOR threshold and the delay TPOR has elapsed. Thedelay TPOR ensures the internal device bias circuitsbecome stable.

The device supply voltage characteristics must meetthe specified starting voltage and rise rate requ ire-ments to generate the POR. Refer to Section 18.0“Electrical Characteristics” for details.

The POR st atus (POR) bit in the Re set Control(RCON<0>) register is set to ind icate the Power-onReset.

7.3 BOR and PWRTThe on-chip regulator has a BOR circuit that resets thedevice when the VDD is too low (VDD < VBOR) for properdevice operation. The BOR circuit keeps the device inReset until VDD crosses the VBOR threshold and thedelay TBOR has elapsed. The delay TBOR ensures thevoltage regulator output becomes stable.

The BOR st atus (BOR) bit in the Re set Control(RCON<1>) register is set to in dicate the Brown-outReset.

The device will not run at full speed after a BOR as theVDD should rise to acceptable levels for full-speedoperation. The PWRT provides power-up time delay(TPWRT) to ensure that the system power supplies havestabilized at the appropriate levels for full-speed oper-ation before the SYSRST is released.

The power-up timer delay (TPWRT) is programmed bythe Power-on Reset T imer Value Select(FPWRT<2:0>) bits in the POR Co nfiguration(FPOR<2:0>) register, which provides eight settings(from 0 ms to 128 ms). Refer to Section 15.0 “SpecialFeatures” for further details.

Figure 7-3 shows the typical brown-out scenarios. TheReset delay (TBOR + TPWRT) is initiated each time VDDrises above the VBOR trip point.

FIGURE 7-3: BROWN-OUT SITUATIONS

VDD

SYSRST

VBOR

VDD

SYSRST

VBOR

VDD

SYSRST

VBOR TBOR + TPWRT

VDD dips before PWRT expires

TBOR + TPWRT

TBOR + TPWRT


dsPIC33FJXXXGSXXX

7.4 External Reset (EXTR)The external Reset is generated by driving the MCLRpin low. The MCLR pin is a Schmitt trigger input with anadditional glitch filter. Reset pulses that are longer thanthe minimum pulse width will generate a Reset. Referto Section 18.0 “Electrical Characteristics” forminimum pulse width specifications. The ExternalReset (MCLR) Pin (EXTR) bit in the Reset Control(RCON) register is set to indicate the MCLR Reset.

7.4.1 EXTERNAL SUPERVISORY CIRCUIT

Many systems have external supervisory circuits thatgenerate Reset signals to Reset multiple devices in thesystem. This external Reset signal can be directly con-nected to the MCLR pin to Reset the device when therest of system is Reset.

7.4.2 INTERNAL SUPERVISORY CIRCUITWhen using the in ternal power supervisory circuit toReset the device, the external Reset pin (MCLR)should be tied directly or resistively to VDD. In this case,the MCLR pin will not be used to generate a Reset. Theexternal Reset pin (MCLR) does not have an internalpull-up and must not be left unconnected.

7.5 Software RESET Instruction (SWR)Whenever the RESET instruction i s executed, thedevice will assert SYSRST, placing the device in a spe-cial Reset state. This Reset state will not re-initialize theclock. The clock source in effect prior to the RESETinstruction will remain. SYSRST is released at the nextinstruction cycle, and the Reset vector fetch willcommence.

The Software Reset (Instruction) Flag (SWR) bit in theReset Control (RCON<6>) register is set to indicate thesoftware Reset.

7.6 Watchdog Time-out Reset (WDTO)Whenever a Watchdog Time-out occurs, the device willasynchronously assert SYSRST. The clock source willremain unchanged. A WD T time-out during Sleep orIdle mode will wake-up the processor, but will not resetthe processor.

The Watchdog Timer Time-out Flag (WDTO) bit in theReset Control (RCON<4>) register is set to indicate theWatchdog Reset. Refer t o Section 15.4 “WatchdogTimer (WDT)” for more in formation on W atchdogReset.

7.7 Trap Conflict Reset If a lower-priority hard trap occurs while a higher-prior-ity trap is being processed, a hard trap conflict Resetoccurs. The hard traps include exceptions of prioritylevel 13 through level 15, inclusive. The address error(level 13) and oscillator error (l evel 14) traps fall intothis category.

The Trap Reset Flag (TRAPR) bit in the Reset Control(RCON<15>) register is set to indicate the Trap ConflictReset. Refer to Section 8.0 “Interrupt Controller” formore information on trap conflict Resets.

7.8 Configuration Mismatch Reset To maintain the integrity of the peripheral pin sele ctcontrol registers, they ar e constantly monitored withshadow registers in h ardware. If an unexpectedchange in any of the registers occur (su ch as cell dis-turbances caused by ESD or other external events), aconfiguration mismatch Reset occurs.

The Configuration Mismatch Flag (CM) bit in the ResetControl (RCON<9>) register is set to indicate the con-figuration mismatch Reset. Refer to Section 11.0 “I/OPorts” for more information on the configuration mis-match Reset.

7.9 Illegal Condition Device ResetAn illegal condition device Reset occurs due to thefollowing sources:

• Illegal Opcode Reset• Uninitialized W Register Reset• Security Reset

The Illegal Opcode or Uninitialized W Access ResetFlag (IOPUWR) bit in the Reset Control (RCON<14>)register is set to i ndicate the illegal condition deviceReset.

7.9.1 ILLEGAL OPCODE RESETA device Reset is generated if the device attempts toexecute an il legal opcode value that is fetched fromprogram memory.

The illegal opcode Reset function can p revent thedevice from executing program memory sections thatare used to store constant data. To take advantage ofthe illegal opcode Reset, use only the lower 16 bits ofeach program memory section to store the data values.The upper 8 bit s should be programmed with 3Fh,which is an illegal opcode value.

Note: The configuration mismatch feature andassociated Reset flag is not available onall devices.


dsPIC33FJXXXGSXXX

7.9.2 UNINITIALIZED W REGISTER RESET

Any attempts to use the uninitialized W register as anaddress pointer will Reset the device. The W registerarray (with the exception of W15) is cleared during allResets and is considered uninitialized until written to.

7.9.3 SECURITY RESET If a Program Flow Change (PFC) or Vector FlowChange (VFC) t argets a restricted location in a pro-tected segment (Boot and Secure Segment), thatoperation will cause a security Reset.

The PFC occurs whe n the Prog ram Counter isreloaded as a result of a Cal l, Jump, Computed Jump,Return, Return from Subrou tine, or other form ofbranch instruction.

The VFC occurs whe n the Prog ram Counter isreloaded with an Interrupt or Trap vector.

7.10 Using the RCON Status BitsThe user application can read the Reset Control(RCON) register af ter any device Reset to determinethe cause of the Reset.

Table 7-3 provides a su mmary of Reset fl ag bitoperation.

TABLE 7-3: RESET FLAG BIT OPERATION

Note: The status bits in the RCON registershould be cleared after they are rea d sothat the next RCON register value after adevice Reset will be meaningful.

Flag Bit Set by: Cleared by:

TRAPR (RCON<15>) Trap conflict event POR, BORIOPWR (RCON<14>) Illegal opcode or uninitialized

W register access or Security ResetPOR, BOR

CM (RCON<9>) Configuration Mismatch POR, BOREXTR (RCON<7>) MCLR Reset PORSWR (RCON<6>) RESET instruction POR, BOR

WDTO (RCON<4>) WDT Time-out PWRSAV instruction, CLRWDT instruction, POR, BOR

SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BORIDLE (RCON<2>) PWRSAV #IDLE instruction POR, BORBOR (RCON<1>) POR, BOR —POR (RCON<0>) POR —

Note: All Reset flag bits can be set or cleared by user software.


dsPIC33FJXXXGSXXX

8.0 INTERRUPT CONTROLLER

The dsPIC33FJXXXGSXXX interrupt controllerreduces the numerous peripheral interrupt requestsignals to a single interrupt request signal to thedsPIC33FJXXXGSXXX CPU. It has the following fea-tures:

• Up to eight processor exceptions and software traps• Seven user-selectable priority levels• Interrupt Vector Table (IVT) with up to 118 vectors• A unique vector for each interrupt or exception

source• Fixed priority within a specified user priority level• Alternate Interrupt Vector Table (AIVT) for debug

support• Fixed interrupt entry and return latencies

8.1 Interrupt Vector TableThe Interrupt Vector Table (IVT) is shown in Figure 8-1.The IVT resides in program memory, starting at location000004h. The IVT contains 126 vectors consisting ofeight non-maskable trap vectors, plus up to 118sources of interrupt. In general, each interrupt sourcehas its own vector. Each interrupt vector contains a 24-bit-wide address. The value programmed into eachinterrupt vector location is the st arting address of theassociated Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their naturalpriority. This priority is linked to thei r position in thevector table. Lower addresses generally have a highernatural priority. For example, the interrupt associatedwith vector 0 will take priority over interrupt s at anyother vector address.

dsPIC33FJXXXGSXXX devices implement up to 26unique interrupts and 4 nonmaskable traps. These aresummarized in Table 8-1 and Table 8-2.

8.1.1 ALTERNATE INTERRUPT VECTOR TABLE

The Alternate Interrupt Vector Table (AIVT) is lo catedafter the IVT, as shown in Figure 8-1. Access to theAIVT is p rovided by the AL TIVT control bit(INTCON2<15>). If the ALTIVT bit is set, all interruptand exception processes use the alternate vectorsinstead of the default vectors. The alternate vectors areorganized in the same manner as the default vectors.

The AIVT sup ports debugging by providing a way toswitch between an application and a su pportenvironment without requiring the in terrupt vectors tobe reprogrammed. This feature also enables switchingbetween applications to facilitate evaluation of differentsoftware algorithms at run time. If the AIVT is notneeded, the AIVT should be programmed with thesame addresses used in the IVT.

8.2 Reset SequenceA device Reset is no t a true exception because theinterrupt controller is not involved in the Reset process.The dsPIC33FJXXXGSXXX device clears its registersin response to a Reset, forcing the PC to zero. The dig-ital signal controller then begins program execution atlocation 0x000000. A GOTO instruction at the Resetaddress can redirect program execution to theappropriate start-up routine.

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not inten ded to b e acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 41. “Interrupts(Part IV)” (DS70300) in the “dsPIC33F/PIC24H Family Reference Manual”,which is available on the Microchip website (www.microchip.com).


Note: Any unimplemented or unused vectorlocations in the IVT and AIVT should beprogrammed with the address of a defaultinterrupt handler routine that cont ains aRESET instruction.




dsPIC33FJXXXGSXXX

FIGURE 8-1: dsPIC33FJXXXGSXXX INTERRUPT VECTOR TABLE

Reset – GOTO Instruction 0x000000Reset – GOTO Address 0x000002

Reserved 0x000004Oscillator Fail Trap VectorAddress Error Trap Vector

Stack Error Trap VectorMath Error Trap Vector

ReservedReservedReserved

Interrupt Vector 0 0x000014Interrupt Vector 1

~~~

Interrupt Vector 52 0x00007CInterrupt Vector 53 0x00007EInterrupt Vector 54 0x000080

~~~

Interrupt Vector 116 0x0000FCInterrupt Vector 117 0x0000FE

Reserved 0x000100Reserved 0x000102Reserved

Oscillator Fail Trap VectorAddress Error Trap Vector

Stack Error Trap VectorMath Error Trap Vector

ReservedReservedReserved

Interrupt Vector 0 0x000114Interrupt Vector 1

~~~

Interrupt Vector 52 0x00017CInterrupt Vector 53 0x00017EInterrupt Vector 54 0x000180

~~~

Interrupt Vector 116Interrupt Vector 117 0x0001FE

Start of Code 0x000200

Dec

reas

ing

Nat

ural

Ord

er P

riorit

y

Interrupt Vector Table (IVT)(1)

Alternate Interrupt Vector Table (AIVT)(1)

Note 1: See Table 8-1 for the list of implemented interrupt vectors.


dsPIC33FJXXXGSXXX

TABLE 8-1: INTERRUPT VECTORS

Vector Number

Interrupt Request (IRQ)

NumberIVT Address AIVT Address Interrupt Source

8 0 0x000014 0x000114 INT0 – External Interrupt 09 1 0x000016 0x000116 IC1 – Input Capture 110 2 0x000018 0x000118 OC1 – Output Compare 111 3 0x00001A 0x00011A T1 – Timer112 4 0x00001C 0x00011C Reserved13 5 0x00001E 0x00011E IC2 – Input Capture 214 6 0x000020 0x000120 OC2 – Output Compare 215 7 0x000022 0x000122 T2 – Timer216 8 0x000024 0x000124 T3 – Timer317 9 0x000026 0x000126 SPI1E – SPI1 Error 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done19 11 0x00002A 0x00012A U1RX – UART1 Receiver20 12 0x00002C 0x00012C U1TX – UART1 Transmitter21 13 0x00002E 0x00012E ADC1 – ADC122 14 0x000030 0x000130 Reserved23 15 0x000032 0x000132 Reserved24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Events25 17 0x000036 0x000136 MI2C1 – I2C1 Master Events26 18 0x000038 0x000138 CMP – Comparator Interrupt27 19 0x00003A 0x00013A Change Notification Interrupt28 20 0x00003C 0x00013C INT1 – External Interrupt 129 21 0x00003E 0x00013E Reserved30 22 0x000040 0x000140 Reserved31 23 0x000042 0x000142 Reserved32 24 0x000044 0x000144 Reserved33 25 0x000046 0x000146 Reserved34 26 0x000048 0x000148 Reserved35 27 0x00004A 0x00014A Reserved36 28 0x00004C 0x00014C Reserved37 29 0x00004E 0x00014E INT2 – External Interrupt 238 30 0x000050 0x000150 Reserved39 31 0x000052 0x000152 Reserved40 32 0x000054 0x000154 Reserved41 33 0x000056 0x000156 Reserved42 34 0x000058 0x000158 Reserved 43 35 0x00005A 0x00015A Reserved44 36 0x00005C 0x00015C Reserved45 37 0x00005E 0x00015E IC3 – Input Capture 346 38 0x000060 0x000160 Reserved47 39 0x000062 0x000162 Reserved48 40 0x000064 0x000164 Reserved49 41 0x000066 0x000166 Reserved50 42 0x000068 0x000168 Reserved51 43 0x00006A 0x00016A Reserved52 44 0x00006C 0x00016C Reserved53 45 0x00006E 0x00016E Reserved


dsPIC33FJXXXGSXXX

54 46 0x000070 0x000170 Reserved55 47 0x000072 0x000172 Reserved56 48 0x000074 0x000174 Reserved57 49 0x000076 0x000176 Reserved58 50 0x000078 0x000178 Reserved59 51 0x00007A 0x00017A Reserved60 52 0x00007C 0x00017C Reserved61 53 0x00007E 0x00017E Reserved62 54 0x000080 0x000180 Reserved63 55 0x000082 0x000182 Reserved 64 56 0x000084 0x000184 Reserved65 57 0x000086 0x000186 PWM1 – PWM1 Period Match66 58 0x000088 0x000188 Reserved67 59 0x00008A 0x00018A Reserved68 60 0x00008C 0x00018C Reserved69 61 0x00008E 0x00018E Reserved70 62 0x000090 0x000190 RTCC – Real-Time Clock and Calendar71 63 0x000092 0x000192 FLTA1 – PWM1 Fault A72 64 0x000094 0x000194 FLTB1 – PWM1 Fault B73 65 0x000096 0x000196 U1E – UART1 Error74 66 0x000098 0x000198 Reserved75 67 0x00009A 0x00019A Reserved76 68 0x00009C 0x00019C Reserved77 69 0x00009E 0x00019E Reserved78 70 0x0000A0 0x0001A0 Reserved79 71 0x0000A2 0x0001A2 Reserved80 72 0x0000A4 0x0001A4 Reserved81 73 0x0000A6 0x0001A6 Reserved82 74 0x0000A8 0x0001A8 Reserved83 75 0x0000AA 0x0001AA Reserved84 76 0x0000AC 0x0001AC Reserved85 77 0x0000AE 0x0001AE CTMU – Charge Time Measurement Unit

86-125 78-117 0x0000B0-0x0000FE

0x0001B0-0x0001FE

Reserved

TABLE 8-1: INTERRUPT VECTORS (CONTINUED)

Vector Number

Interrupt Request (IRQ)

NumberIVT Address AIVT Address Interrupt Source


dsPIC33FJXXXGSXXX

TABLE 8-2: TRAP VECTORS

8.3 Interrupt Control and Status Registers

The dsPIC33FJXXXGSXXX devices implement a totalof 22 registers for the interrupt controller:

• INTCON1 • INTCON2 • IFSx• IECx• IPCx • INTTREG

8.3.1 INTCON1 AND INTCON2Global interrupt control functions are controlled fromINTCON1 and INTCON2. INTCON1 contains theInterrupt Nesting Disable (NSTDIS) bit as well as thecontrol and status flags for the processor trap sources.The INTCON2 register contro ls the externa l interruptrequest signal behavior and the use of the AlternateInterrupt Vector Table.

8.3.2 IFSxThe IFS registers maintain all of the interrupt requestflags. Each source of interrupt has a status bit, which isset by the respective peripherals or external signal andis cleared via software.

8.3.3 IECxThe IEC registers maintain all of the interrupt enablebits. These control bits are used to individually enableinterrupts from the peripherals or external signals.

8.3.4 IPCxThe IPC registers are used to set the interrupt prioritylevel for each source of interrupt. Each user interruptsource can be assigned to one of eight priority levels.

8.3.5 INTTREGThe INTTREG register contains the associatedinterrupt vector numbe r and the new CPU interruptpriority level, which are latched into vector n umber(VECNUM<6:0>) and interrupt level (ILR<3:0>) bitfields in the INTTREG register. The new interruptpriority level is the priority of the pending interrupt.

The interrupt sources are assign ed to the IFSx, IECxand IPCx registers in the same sequence that they arelisted in Table 8-1. For example, the INT0 (ExternalInterrupt 0) is shown as having vector number 8 and anatural order priority of 0. Thus, the INT0IF bit is foundin IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IPbits in the first positions of IPC0 (IPC0<2:0>).

8.3.6 STATUS/CONTROL REGISTERSAlthough they are no t specifically part of the interruptcontrol hardware, two of the CPU Co ntrol registerscontain bits that control interrupt functionality.

• The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU interrupt priority level. The user application can change the current CPU priority level by writing to the IPL bits.

• The CORCON register contains the IPL3 bit which, together with IPL<2:0>, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software.

All Interrupt regi sters are described in Register 8-1through Register 8-27 in the following pages.

Vector Number IVT Address AIVT Address Trap Source

0 0x000004 0x000104 Reserved1 0x000006 0x000106 Oscillator Failure2 0x000008 0x000108 Address Error3 0x00000A 0x00010A Stack Error4 0x00000C 0x00010C Math Error5 0x00000E 0x00010E Reserved6 0x000010 0x000110 Reserved7 0x000012 0x000112 Reserved


dsPIC33FJXXXGSXXX

REGISTER 8-1: SR: CPU STATUS REGISTER(1)

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0OA OB SA SB OAB SAB DA DC

bit 15 bit 8

R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL2(2) IPL1(2) IPL0(2) RA N OV Z C

bit 7 bit 0

Legend:C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’S = Set only bit W = Writable bit -n = Value at POR‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled110 = CPU Interrupt Priority Level is 6 (14)101 = CPU Interrupt Priority Level is 5 (13)100 = CPU Interrupt Priority Level is 4 (12)011 = CPU Interrupt Priority Level is 3 (11)010 = CPU Interrupt Priority Level is 2 (10)001 = CPU Interrupt Priority Level is 1 (9)000 = CPU Interrupt Priority Level is 0 (8)

Note 1: For complete register details, see Register 4-1: “SR: CPU Status Register”.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt PriorityLevel. The value in p arentheses indicates the IPL if IPL<3> = 1. User interrupts are di sabled whenIPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

REGISTER 8-2: CORCON: CORE CONTROL REGISTER(1)

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0— — — US EDT DL<2:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF

bit 7 bit 0

Legend: C = Clear only bitR = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)

1 = CPU interrupt priority level is greater than 70 = CPU interrupt priority level is 7 or less

Note 1: For complete register details, see Register 4-2: “CORCON: Core Control Register”.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.


dsPIC33FJXXXGSXXX

REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —

bit 7 bit 0


bit 15 NSTDIS: Interrupt Nesting Disable bit1 = Interrupt nesting is disabled0 = Interrupt nesting is enabled

bit 14 OVAERR: Accumulator A Overflow Trap Flag bit1 = Trap was caused by overflow of Accumulator A0 = Trap was not caused by overflow of Accumulator A

bit 13 OVBERR: Accumulator B Overflow Trap Flag bit1 = Trap was caused by overflow of Accumulator B0 = Trap was not caused by overflow of Accumulator B

bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A

bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B

bit 10 OVATE: Accumulator A Overflow Trap Enable bit1 = Trap overflow of Accumulator A0 = Trap disabled

bit 9 OVBTE: Accumulator B Overflow Trap Enable bit1 = Trap overflow of Accumulator B0 = Trap disabled

bit 8 COVTE: Catastrophic Overflow Trap Enable bit1 = Trap on catastrophic overflow of Accumulator A or B enabled0 = Trap disabled

bit 7 SFTACERR: Shift Accumulator Error Status bit1 = Math error trap was caused by an invalid accumulator shift0 = Math error trap was not caused by an invalid accumulator shift

bit 6 DIV0ERR: Arithmetic Error Status bit1 = Math error trap was caused by a divide by zero0 = Math error trap was not caused by a divide by zero

bit 5 Unimplemented: Read as ‘0’bit 4 MATHERR: Arithmetic Error Status bit

1 = Math error trap has occurred0 = Math error trap has not occurred

bit 3 ADDRERR: Address Error Trap Status bit1 = Address error trap has occurred0 = Address error trap has not occurred


dsPIC33FJXXXGSXXX

bit 2 STKERR: Stack Error Trap Status bit1 = Stack error trap has occurred0 = Stack error trap has not occurred

bit 1 OSCFAIL: Oscillator Failure Trap Status bit1 = Oscillator failure trap has occurred0 = Oscillator failure trap has not occurred

bit 0 Unimplemented: Read as ‘0’

REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)


dsPIC33FJXXXGSXXX

REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0ALTIVT DISI — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0— — — — — INT2EP INT1EP INT0EP

bit 7 bit 0


bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit1 = Use alternate vector table0 = Use standard (default) vector table

bit 14 DISI: DISI Instruction Status bit1 = DISI instruction is active0 = DISI instruction is not active

bit 13-3 Unimplemented: Read as ‘0’bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit1 = Interrupt on negative edge 0 = Interrupt on positive edge


dsPIC33FJXXXGSXXX

REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF

bit 7 bit 0


bit 15-14 Unimplemented: Read as ‘0’bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 8 T3IF: Timer3 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 7 T2IF: Timer2 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 4 Unimplemented: Read as ‘0’bit 3 T1IF: Timer1 Interrupt Flag Status bit


bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred


dsPIC33FJXXXGSXXX

bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 0 INT0IF: External Interrupt 0 Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)


dsPIC33FJXXXGSXXX


U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0— — INT2IF — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — — INT1IF CNIF CMPIF MI2C1IF SI2C1IF

bit 7 bit 0


bit 15-14 Unimplemented: Read as ‘0’bit 13 INT2IF: External Interrupt 2 Flag Status bit


bit 12-5 Unimplemented: Read as ‘0’bit 4 INT1IF: External Interrupt 1 Flag Status bit


bit 3 CNIF: Input Change Notification Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 2 CMPIF: Comparator Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred


dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0— — IC3IF — — — — —

bit 7 bit 0


bit 15-6 Unimplemented: Read as ‘0’bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit


bit 4-0 Unimplemented: Read as ‘0’


R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0FLTA1IF RTCCIF — — — — PWM1IF —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 7 bit 0


bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 14 RTCCIF: RTCC Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred

bit 13-10 Unimplemented: Read as ‘0’bit 9 PWM1IF: PWM1 Interrupt Flag Status bit




dsPIC33FJXXXGSXXX


U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0— — CTMUIF — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0— — — — — — U1EIF FLTB1IF

bit 7 bit 0


bit 15-14 Unimplemented: Read as ‘0’bit 13 CTMUIF: CTMU Interrupt Flag Status bit


bit 12-2 Unimplemented: Read as ‘0’bit 1 U1EIF: UART1 Error Interrupt Flag Status bit


bit 0 FLTB1IF: PWM1 Fault B Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred


dsPIC33FJXXXGSXXX

REGISTER 8-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE

bit 7 bit 0


bit 15-14 Unimplemented: Read as ‘0’bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit

1 = Interrupt request enabled0 = Interrupt request not enabled

bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 10 SPI1IE: SPI1 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 8 T3IE: Timer3 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 7 T2IE: Timer2 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 4 Unimplemented: Read as ‘0’bit 3 T1IE: Timer1 Interrupt Enable bit


bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled


dsPIC33FJXXXGSXXX

bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 0 INT0IE: External Interrupt 0 Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

REGISTER 8-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)


dsPIC33FJXXXGSXXX


U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0— — INT2IE — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0— — — INT1IE CNIE CMPIE MI2C1IE SI2C1IE

bit 7 bit 0


bit 15-14 Unimplemented: Read as ‘0’bit 13 INT2IE: External Interrupt 2 Enable bit


bit 12-5 Unimplemented: Read as ‘0’bit 4 INT1IE: External Interrupt 1 Enable bit


bit 3 CNIE: Input Change Notification Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 2 CMPIE: Comparator Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled


dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0— — IC3IE — — — — —

bit 7 bit 0


bit 15-6 Unimplemented: Read as ‘0’bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit




R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0FLTA1IE RTCCIE — — — — PWM1IE —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 7 bit 0


bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 14 RTCCIE: RTCC Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled

bit 13-10 Unimplemented: Read as ‘0’bit 9 PWM1IE: PWM1 Interrupt Enable bit




dsPIC33FJXXXGSXXX


U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0— — CTMUIE — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0— — — — — — U1EIE FLTB1IE

bit 7 bit 0


bit 15-14 Unimplemented: Read as ‘0’bit 13 CTMUIE: CTMU Interrupt Enable bit


bit 12-2 Unimplemented: Read as ‘0’bit 1 U1EIE: UART1 Error Interrupt Enable bit


bit 0 FLTB1IE: PWM1 Fault B Interrupt Enable bit1 = Interrupt request has occurred0 = Interrupt request has not occurred


dsPIC33FJXXXGSXXX

REGISTER 8-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— T1IP<2:0> — OC1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— IC1IP<2:0> — INT0IP<2:0>

bit 7 bit 0


bit 15 Unimplemented: Read as ‘0’bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits


bit 7 Unimplemented: Read as ‘0’bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits


bit 3 Unimplemented: Read as ‘0’bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits



dsPIC33FJXXXGSXXX


U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— T2IP<2:0> — OC2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— IC2IP<2:0> — — — —

bit 7 bit 0




bit 11 Unimplemented: Read as ‘0’bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits


bit 7 Unimplemented: Read as ‘0’bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits




dsPIC33FJXXXGSXXX


U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— U1RXIP<2:0> — SPI1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— SPI1EIP<2:0> — T3IP<2:0>

bit 7 bit 0


bit 15 Unimplemented: Read as ‘0’bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits


bit 11 Unimplemented: Read as ‘0’bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits


bit 7 Unimplemented: Read as ‘0’bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits





dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— AD1IP<2:0> — U1TXIP<2:0>

bit 7 bit 0


bit 15-7 Unimplemented: Read as ‘0’bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits


bit 3 Unimplemented: Read as ‘0’bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits



dsPIC33FJXXXGSXXX


U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— CNIP<2:0> — CMPIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— MI2C1IP<2:0> — SI2C1IP<2:0>

bit 7 bit 0


bit 15 Unimplemented: Read as ‘0’bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits


bit 11 Unimplemented: Read as ‘0’bit 10-8 CMPIP<2:0>: Comparator Interrupt Priority bits


bit 7 Unimplemented: Read as ‘0’bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits


bit 3 Unimplemented: Read as ‘0’bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits



dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0— — — — — INT1IP<2:0>

bit 7 bit 0


bit 15-3 Unimplemented: Read as ‘0’bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits



U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— INT2IP<2:0> — — — —

bit 7 bit 0


bit 15-7 Unimplemented: Read as ‘0’bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits




dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— IC3IP<2:0> — — — —

bit 7 bit 0


bit 15-7 Unimplemented: Read as ‘0’bit 6-4 IC3IP<2:0>: External Interrupt 3 Priority bits




U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— PWM1IP<2:0> — — — —

bit 7 bit 0


bit 15-7 Unimplemented: Read as ‘0’bit 6-4 PWM1IP<2:0>: PWM1 Interrupt Priority bits




dsPIC33FJXXXGSXXX


U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— FLTA1IP<2:0> — RTCCIP<2:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 7 bit 0


bit 15 Unimplemented: Read as ‘0’bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits


bit 11 Unimplemented: Read as ‘0’bit 10-8 RTCCIP<2:0>: RTCC Interrupt Priority bits




dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0— U1EIP<2:0> — FLTB1IP<2:0>

bit 7 bit 0


bit 15-7 Unimplemented: Read as ‘0’bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits


bit 3 Unimplemented: Read as ‘0’bit 2-0 FLTB1IP<2:0>: PWM1 Fault B Interrupt Priority bits



dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— CTMUIP<2:0> — — — —

bit 7 bit 0


bit 15-7 Unimplemented: Read as ‘0’bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits




dsPIC33FJXXXGSXXX

REGISTER 8-27: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0— — — — ILR<3:0>

bit 15 bit 8

U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0— VECNUM<6:0>

bit 7 bit 0


bit 15-12 Unimplemented: Read as ‘0’bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits

1111 = CPU Interrupt Priority Level is 15 •••0001 = CPU Interrupt Priority Level is 10000 = CPU Interrupt Priority Level is 0

bit 7 Unimplemented: Read as ‘0’bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits

0111111 = Interrupt Vector pending is number 135 •••0000001 = Interrupt Vector pending is number 90000000 = Interrupt Vector pending is number 8


dsPIC33FJXXXGSXXX

8.4 Interrupt Setup Procedures

8.4.1 INITIALIZATIONTo configure an interrupt source at initialization:

1. Set the NSTDIS bit (INTCON1<15>) if n estedinterrupts are not desired.

2. Select the u ser-assigned priority level for theinterrupt source by writing the control bits intothe appropriate IPCx register. The priority levelwill depend on the specific application and typeof interrupt source. If mult iple priority levels arenot desired, the IPCx register control bits for allenabled interrupt sources can be programmedto the same non-zero value.

3. Clear the interrupt flag status bit associated withthe peripheral in the associated IFSx register.

4. Enable the interrupt source by setting the inter-rupt enable control bit associated with thesource in the appropriate IECx register.

8.4.2 INTERRUPT SERVICE ROUTINEThe method used to declare an ISR and initialize theIVT with the correct vector address depends on theprogramming language (C or a ssembler) and thelanguage development tool suite used to develop theapplication.

In general, the user application must clear the interruptflag in the appropriate IFSx register for th e source ofinterrupt that the ISR handles. Otherwise, program willre-enter the ISR immediately after exiting the routine. Ifthe ISR is coded in assembly language, it must b eterminated using a RETFIE instruction to unstack thesaved PC value, SRL value and old CPU priority level.

8.4.3 TRAP SERVICE ROUTINEA Trap Service Routine (TSR) is code d like a n ISR,except that the appropriate trap status flag in theINTCON1 register must b e cleared to avo id re-entryinto the TSR.

8.4.4 INTERRUPT DISABLEAll user interrup ts can be di sabled using thisprocedure:

1. Push the current SR val ue onto the softwarestack using the PUSH instruction.

2. Force the CPU to priority le vel 7 by inclusiveORing the value OEh with SRL.

To enable user interrup ts, the POP instruction can beused to restore the previous SR value.

The DISI instruction provides a convenient way todisable interrupts of priority levels 1-6 for a fixed periodof time. Level 7 interrupt sources are not disabled bythe DISI instruction.

Note: At a device Reset, the IPCx registersare initialized such tha t all userinterrupt sources are assigned topriority level 4.

Note: Only user interrupts with a priority level of7 or lower can be disabled. Trap sources(level 8-level 15) cannot be disabled.


dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

9.0 OSCILLATOR CONFIGURATION

The oscillator system for dsPIC33FJXXXGSXXXdevices provides:• External and internal oscillator options as clock

sources• An on-chip 4x Phase-Locked Loop (PLL) to scale

the internal operating frequency to the required system clock frequency

• An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware

• Clock switching between various clock sources• Programmable clock postscaler for system power

savings• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures• A Clock Control register (OSCCON)• Nonvolatile Configuration bits for main oscillator

selectionA simplified diagram of the oscillator system is shownin Figure 9-1.

FIGURE 9-1: dsPIC33FJXXXGSXXX OSCILLATOR SYSTEM DIAGRAM

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not intended to be a compre-hensive reference source. To comple-ment the information in this dat a sheet,refer to Section 52. “Oscillator (PartVI)” (DS70644) in the “dsPIC33F/PIC24H Family Reference Manual”,which is available from the Microchip website (www.microchip.com).


Note 1: If the Oscillator is used with MS or HS modes, an extended parallel resistor with the value of 1 M must be connected.2: The term FP refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU. Throughout this docu-

ment, FCY and FP are used interchangeably, except in the case of DOZE mode. FP and FCY will be different when DOZE mode isused with a doze ratio of 1:2 or lower.

Secondary Oscillator (SOSC)

LPOSCEN

SOSCO

SOSCI

Timer 1

MSPLL, ECPLL,

MS, HS, EC

FRCDIV<2:0>

WDT, PWRT, FSCM

FRCDIVN

SOSC

FRCDIV16

FRCPLL

NOSC<2:0> FNOSC<2:0>

Reset

FRCOscillator

LPRCOscillator

DOZE<2:0>S3

S1

S2

S1/S3

S7

S6

FRC

LPRC

S0

S5

S4

÷ 16

Clock Switch

S7

Clock Fail

÷ 2

TUN<5:0>

4x PLL

FCY(2)

FRC

DIV

DO

ZE

OSC2

OSC1Primary Oscillator (POSC)

R(1)

POSCMD<1:0>

FP(2)

Fosc

(To peripherals)


dsPIC33FJXXXGSXXX

9.1 CPU Clocking SystemThe dsPIC33FJXXXGSXXX devices provide sevensystem clock options:

• Fast RC (FRC) Oscillator• FRC Oscillator with 4x PLL• Primary (MS, HS or EC) Oscillator• Primary Oscillator with 4x PLL• Secondary (LP) Oscillator • Low-Power RC (LPRC) Oscillator• FRC Oscillator with postscaler

9.1.1 SYSTEM CLOCK SOURCES

9.1.1.1 Fast RCThe Fast RC (FRC) internal oscillator runs at a nominalfrequency of 7 .37 MHz. User software can tune theFRC frequency. User software can optionally specify afactor (ranging from 1:2 to 1:256) by which the FRCclock frequency is divided. This factor is selected usingthe FRCDIV<2:0> (CLKDIV<10:8>) bits.

9.1.1.2 PrimaryThe primary oscillator can use one of the following asits clock source:

• MS (Crystal): Crystals and ceramic resonators in the range of 4 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins.

• HS (High-Speed Crystal): Crystals in the range of 10 MHz to 32 MHz. The crystal is connected to the OSC1 and OSC2 pins.

• EC (External Clock): The external clock signal is directly applied to the OSC1 pin.

9.1.1.3 SecondaryThe secondary (LP) oscillator is designed for low powerand uses a 3 2.768 kHz crystal or ceramic resonator.The LP oscillator uses the SOSCI and SOSCO pins.

9.1.1.4 Low-Power RCThe Low-Power RC (LPRC) internal oscIllator runs at anominal frequency of 32.768 kHz. It is also used as areference clock by the W atchdog Timer (WDT) andFail-Safe Clock Monitor (FSCM).

9.1.1.5 FRCThe clock signals generated by the FRC and primaryoscillators can be op tionally applied to an on -chip 4xPhase-Locked Loop (PLL) to pro vide faster outputfrequencies for device operation. PLL configuration isdescribed in Section 9.1.3 “PLL Configuration”.

The FRC frequency depends on the FRC accuracy(see Table 18-18) and the value of the FRC OscillatorTuning register (see Register 9-3).

9.1.2 SYSTEM CLOCK SELECTIONThe oscillator source us ed at a device Power-onReset event is selected using Configuration bitsettings. The oscillator Configuration bit settings arelocated in the Configuration registers in th e programmemory. (Refer to Section 15.1 “ConfigurationBits” for further details.) The Initial OscillatorSelection Configuration bits, FNOSC<2:0>(FOSCSEL<2:0>), and the Primary Oscill ator ModeSelect Configuration bits, POSCMD<1:0>(FOSC<1:0>), select the oscillator source that is usedat a Power-on Reset. Th e FRC primary oscillator isthe default (unprogrammed) selection.

The Configuration bits allow users to choose among 12different clock modes, shown in Table 9-1.

The output of the oscillator (or the output of the PLL ifa PLL mode has been selected) FOSC is divided by 2 togenerate the device instruction clock (FCY) and theperipheral clock time base (FP). FCY defines theoperating speed of the device, and speeds up to 40MHz are supported by the dsPIC33FJXXXGSXXXarchitecture.

Instruction execution speed or devi ce operatingfrequency, FCY, is given by:

EQUATION 9-1: DEVICE OPERATING FREQUENCY

FCYFOSC

2-------------=


dsPIC33FJXXXGSXXX

9.1.3 PLL CONFIGURATIONThe primary oscil lator and internal FRC oscillator canoptionally use an on-chip 4x PLL to obtain higherspeeds of operation.

For example, suppose a 8 MHz crystal is being usedwith the selected oscillator mode of MS with PLL. Thisprovides a Fosc of 8 MHz * 4 = 32 MHz. The resultantdevice operating speed is 32/2 = 16 MIPS.

EQUATION 9-2: MS WITH PLL MODE EXAMPLE

TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

FCYFOSC

2-------------

12--- 8000000 4 16 MIPS= = =

Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> See

Note

Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1Low-Power RC Oscillator (LPRC) Internal xx 101 1Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 1Primary Oscillator (MS) with PLL (MSPLL) Primary 01 011 —Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1Primary Oscillator (HS) Primary 10 010 —Primary Oscillator (MS) Primary 01 010 —Primary Oscillator (EC) Primary 00 010 1Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1Fast RC Oscillator (FRC) Internal xx 000 1Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.


dsPIC33FJXXXGSXXX

REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1)

U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y— COSC<2:0> — NOSC<2:0>(2)

bit 15 bit 8

R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN

bit 7 bit 0

Legend: y = Value set from Configuration bits on PORR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)

000 = Fast RC oscillator (FRC)001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (MS, HS, EC)011 = Primary oscillator (MS, EC) with PLL 100 = Secondary oscillator (SOSC)101 = Low-Power RC oscillator (LPRC)110 = Fast RC oscillator (FRC) with Divide-by-16111 = Fast RC oscillator (FRC) with Divide-by-n

bit 11 Unimplemented: Read as ‘0’bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2)

000 = Fast RC oscillator (FRC)001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (MS, HS, EC)011 = Primary oscillator (MS, EC) with PLL 100 = Secondary oscillator (SOSC)101 = Low-Power RC oscillator (LPRC)110 = Fast RC oscillator (FRC) with Divide-by-16111 = Fast RC oscillator (FRC) with Divide-by-n

bit 7 CLKLOCK: Clock Lock Enable bit If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01)1 = Clock switching is disabled, system clock source is locked0 = Clock switching is enabled, system clock source can be modified by clock switching

bit 6 IOLOCK: Peripheral Pin Select Lock bit1 = Peripherial pin select is locked, write to peripheral pin select registers not allowed0 = Peripherial pin select is not locked, write to peripheral pin select registers allowed

bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4 Unimplemented: Read as ‘0’bit 3 CF: Clock Fail Detect bit (read/clear by application)

1 = FSCM has detected clock failure0 = FSCM has not detected clock failure

bit 2 Unimplemented: Read as ‘0’

Note 1: Writes to this register require an unlock sequence. Refer to Section 52. “Oscillator (Part VI)” (DS70644)in the “dsPIC33F/PIC24H Family Reference Manual” for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.This applies to clock switches in either direction. In these instances, the application must switch to FRC modeas a transition clock source between the two PLL modes.


dsPIC33FJXXXGSXXX

bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit1 = Enable secondary oscillator0 = Disable secondary oscillator

bit 0 OSWEN: Oscillator Switch Enable bit1 = Request oscillator switch to selection specified by NOSC<2:0> bits0 = Oscillator switch is complete

REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)

Note 1: Writes to this register require an unlock sequence. Refer to Section 52. “Oscillator (Part VI)” (DS70644)in the “dsPIC33F/PIC24H Family Reference Manual” for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.This applies to clock switches in either direction. In these instances, the application must switch to FRC modeas a transition clock source between the two PLL modes.


dsPIC33FJXXXGSXXX

REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0ROI DOZE<2:0>(2,3) DOZEN(1,2,3) FRCDIV<2:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 7 bit 0


bit 15 ROI: Recover on Interrupt bit1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:10 = Interrupts have no effect on the DOZEN bit

bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(2,3)

000 = FCY/1001 = FCY/2010 = FCY/4011 = FCY/8 (default)100 = FCY/16101 = FCY/32110 = FCY/64111 = FCY/128

bit 11 DOZEN: DOZE Mode Enable bit(1,2,3)

1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks0 = Processor clock/peripheral clock ratio forced to 1:1

bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits000 = FRC divide by 1 (default)001 = FRC divide by 2010 = FRC divide by 4011 = FRC divide by 8100 = FRC divide by 16101 = FRC divide by 32110 = FRC divide by 64111 = FRC divide by 256


Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.2: If DOZEN = 1, writes to DOZE<2:0> are ignored.3: If DOZE<2:0> = 000, the DOZEN bit cannot be set by the user; writes are ignored.


dsPIC33FJXXXGSXXX

REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNING REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — TUN<5:0>(1)

bit 7 bit 0


bit 15-6 Unimplemented: Read as ‘0’bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1)

011111 = Center frequency +11.625% (8.23 MHz)011110 = Center frequency +11.25% (8.20 MHz)•••000001 = Center frequency +0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal)111111 = Center frequency -0.375% (7.345 MHz) •••100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz)

Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on theFRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neithercharacterized nor tested.


dsPIC33FJXXXGSXXX

9.2 Clock Switching OperationApplications are free to switch among any of the fourclock sources (Primary, LP, FRC, and LPRC) und ersoftware control at any time. To limit the possible sideeffects of this flexibility, dsPIC33FJXXXGSXXXdevices have a safeguard lock built into the switchprocess.

9.2.1 ENABLING CLOCK SWITCHINGTo enable clock switching, the FCKSM1 Configurationbit in the Configuration register must be programmed to‘0’. (Refer to Section 15.1 “Configuration Bits” forfurther details.) If th e FCKSM1 Configuration bit isunprogrammed (‘1’), the clock switching function andFail-Safe Clock Monitor function are disabled. This isthe default setting. The NOSC control b its (OSCCON<10:8>) do notcontrol the clock selection when clock switchin g isdisabled. However, the COSC bits (OSCCON<14:12>)reflect the clock source selected by the FNOSCConfiguration bits. The OSWEN control bit (OSCCON<0>) has no effectwhen clock switching is disabled. It is he ld at ‘0’ at alltimes.

9.2.2 OSCILLATOR SWITCHING SEQUENCEPerforming a clock switch requires this basicsequence:

1. If desired, read the COSC bit s(OSCCON<14:12>) to determine the currentoscillator source.

2. Perform the unlock sequence to allow a write tothe OSCCON register high byte.

3. Write the appropriate value to the NOSC controlbits (OSCCON<10:8>) for the new oscillatorsource.

4. Perform the unlock sequence to allow a write tothe OSCCON register low byte.

5. Set the OSWEN bit (OSCCON<0>) to in itiatethe oscillator switch.

Once the basic sequence is completed, the systemclock hardware responds automatically as follows:

1. The clock switching hardware compares theCOSC status bits with the new value of th eNOSC control bits. If they are the same, theclock switch is a redu ndant operation. In th iscase, the OSWEN bit is cleared automaticallyand the clock switch is aborted.

2. If a valid clock switch has been initiated, theLOCK (OSCCON<5>) and the C F(OSCCON<3>) status bits are cleared.

3. The new oscillator is turned on by the hardwareif it is not currently running. If a crystal oscillatormust be turned on, the hardware waits until theOscillator Start-up Timer (OST) expires. If thenew source is using the PLL, the hardware waitsuntil a PLL lock is detected (LOCK = 1).

4. The hardware waits for 10 clock cycles from thenew clock source and then performs the clockswitch.

5. The hardware clears the OSWEN bit to indicate asuccessful clock transition. In addition, the NOSCbit values are transferred to the COSC status bits.

6. The old clock source is turned off at this time,with the exception of LPRC (if WDT or FSCMare enabled) or LP (if LPOSCEN remains set).

9.3 Fail-Safe Clock Monitor (FSCM)The Fail-Safe Clock Monitor (FSCM) allows the deviceto continue to operate even in the event of an oscillatorfailure. The FSCM function is enabled by programming.If the FSCM function is enabled, the LPRC internaloscillator runs at all times (except during Sleep mode)and is not subject to control by the Watchdog Timer.

In the eve nt of a n oscillator failure, the FSCMgenerates a clock failure trap event and switches thesystem clock over to the FRC oscillator . Then theapplication program can e ither attempt to re start theoscillator or execute a controlled shutdown. The trapcan be treated as a warm Reset by simply loading theReset address into the oscillator fail trap vector.

If the PLL multiplier is used to scale the system clock ,the internal FRC is also multiplied by the same factoron clock failure. Es sentially, the device switches toFRC with PLL on a clock failure.

Note: Primary Oscillator mode has three differentsubmodes (MS, HS, and EC), which aredetermined by the POSCMD<1:0> Config-uration bits. While an application canswitch to an d from Primary Oscil latormode in software, it cannot switch amongthe different primary submodes withoutreprogramming the device.

Note 1: The processor continues to execute codethroughout the clock switching sequence.Timing-sensitive code should not beexecuted during this time.

2: Direct clock sw itches between any pri-mary oscillator mode w ith PLL andFRCPLL mode are not permitted. Thisapplies to clock switches in eithe r direc-tion. In these instances, the applicationmust switch to FRC mode as a transitionclock source between the two PLL modes.

3: Refer to Section 7. “Oscillator”(DS70186) in the “dsPIC33F/PIC24HFamily Reference Manual” for details.


dsPIC33FJXXXGSXXX

10.0 POWER-SAVING FEATURES

The dsPIC33FJXXXGSXXX devices provide the abilityto manage power consumption by selectivelymanaging clocking to the CPU and the peripherals. Ingeneral, a lower clock frequency and a reduction in thenumber of circuits being clocked constitutes lowerconsumed power. dsPIC33FJXXXGSXXX devices canmanage power consumption in four different ways:

• Clock frequency• Instruction-based Sleep and Idle modes• Software-controlled Doze mode• Selective peripheral control in software

Combinations of these methods can be used to selec-tively tailor an application’s power consumption whilestill maintaining critical application features, such astiming-sensitive communications.

10.1 Clock Frequency and Clock Switching

dsPIC33FJXXXGSXXX devices allow a wide range ofclock frequencies to b e selected under applicationcontrol. If the system clock configuration is not locked,users can choose low-power or high-precisionoscillators by si mply changing the NOSC bits(OSCCON<10:8>). The process of changing a systemclock during operation, as well as limit ations to th eprocess, are discussed in more det ail in Section 9.0“Oscillator Configuration”.

10.2 Instruction-Based Power-Saving Modes

dsPIC33FJXXXGSXXX devices have two specialpower-saving modes that are entered through theexecution of a special PWRSAV instruction. Sleep modestops clock operation and halts all code execution. Idlemode halts the CPU and code execution, but al lowsperipheral modules to continue operation. Theassembler syntax of the PWRSAV instruction is shown inExample 10-1.

Sleep and Idle modes can be exited as a result of anenabled interrupt, WDT time-out or a device Reset. Whenthe device exits these modes, it is said to wake-up.

10.2.1 SLEEP MODE The following occur in Sleep mode:

• The system clock source is shut down. If an on-chip oscillator is used, it is turned off.

• The device current consumption is reduced to a minimum, provided that no I/O pin is sourcing current

• The Fail-Safe Clock Monitor does not operate, since the system clock source is disabled

• The LPRC clock continues to run in Sleep mode if the WDT is enabled

• The WDT, if enabled, is automatically cleared prior to entering Sleep mode

• Some device features or peripherals may continue to operate. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input.

• Any peripheral that requires the system clock source for its operation is disabled

The device will wake-up from Sleep mode on any of thethese events:

• Any interrupt source that is individually enabled• Any form of device Reset• A WDT time-out

On wake-up from Sleep mode, the processor restartswith the same clock source that was active when Sleepmode was entered.

EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not inten ded to b e acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 9. “WatchdogTimer and Power-Saving Modes”(DS70196) in the “dsPIC33F/PIC24HFamily Reference Manual”, which isavailable from the Microch ip web site(www.microchip.com).


Note: SLEEP_MODE and IDLE_MODE areconstants defined in the assemblerinclude file for the selected device.

PWRSAV #SLEEP_MODE ; Put the device into SLEEP modePWRSAV #IDLE_MODE ; Put the device into IDLE mode


dsPIC33FJXXXGSXXX

10.2.2 IDLE MODE The following occur in Idle mode:

• The CPU stops executing instructions• The WDT is automatically cleared• The system clock source remains active. By

default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.4 “Peripheral Module Disable”).

• If the WDT or FSCM is enabled, the LPRC also remains active.

The device will wake from Idle mode on any of the seevents:

• Any interrupt that is individually enabled• Any device Reset• A WDT time-out

On wake-up from Idle mode, the clock is reapplied tothe CPU and instruction execution will begin (2-4 clockcycles later), starting with the i nstruction following thePWRSAV instruction, or the first instruction in the ISR.

10.2.3 INTERRUPTS COINCIDENT WITH POWER-SAVE INSTRUCTIONS

Any interrupt that coi ncides with the execution of aPWRSAV instruction is held off until entry into Sleep orIdle mode has completed. The device then wakes upfrom Sleep or Idle mode.

10.3 Doze ModeThe preferred strategies for reducing powerconsumption are ch anging clock speed and i nvokingone of the pow er-saving modes. In somecircumstances, this may not be practical. For example,it may be necessary for an a pplication to main tainuninterrupted synchronous communication, even whileit is doing nothing else. Reducing system clock speedcan introduce communication errors, whi le using apower-saving mode can stop communicationscompletely.

Doze mode is a simple and effective alternative methodto reduce power consumption while the device is stillexecuting code. In this mode, the system clockcontinues to operate from the same source and at thesame speed. Peripheral modules continue to beclocked at the same speed, while the CPU clock speedis reduced. Synchronization between the two clockdomains is ma intained, allowing the peripherals toaccess the SFRs while the CPU executes code at aslower rate.

Doze mode is enabled by setti ng the DOZEN bit(CLKDIV<11>). The ratio between peripheral and coreclock speed is determined by the DOZE<2:0> bits(CLKDIV<14:12>). There are eight possibleconfigurations, from 1:1 to 1:128, with 1:1 being thedefault setting.

Programs can use Doze mode to selectively reducepower consumption in event-driven applications. Thisallows clock-sensitive functions, such as synchronouscommunications, to continue without interruption whilethe CPU idl es, waiting for so mething to invoke aninterrupt routine. An automatic return to full-speed CPUoperation on interrupts can be enabled by setting theROI bit (CLKDIV<15>). By default, interrupt even tshave no effect on Doze mode operation.

For example, suppose the device is operating at20 MIPS and the UART module has been configuredfor 500 kbps based on this device operating speed. Ifthe device is placed in Doze mode with a clockfrequency ratio of 1:4, the UART module continues tocommunicate at the required bit rate of 500 kbps, butthe CPU no w starts executing instructions at afrequency of 5 MIPS.

10.4 Peripheral Module DisableThe Peripheral Module Disable (PMD) registersprovide a metho d to disa ble a peripheral module bystopping all clock sou rces supplied to tha t module.When a peripheral is di sabled using the a ppropriatePMD control bit, the peripheral is in a minimum powerconsumption state. The control and status registersassociated with th e peripheral are also disabled, sowrites to those re gisters will have no effect and readvalues will be invalid.

A peripheral module is enab led only if both theassociated bit in the PMD register i s cleared an d theperipheral is supported by the specific dsPIC ® DSCvariant. If the peripheral is present in the device, it isenabled in the PMD register by default.

Note: If a PMD bit is se t, the co rrespondingmodule is di sabled after a del ay of oneinstruction cycle. Similarly, if a PMD bit iscleared, the corresponding module isenabled after a de lay of one instructioncycle (assuming the module control regis-ters are already configured to enablemodule operation).


dsPIC33FJXXXGSXXX

REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0— — T3MD T2MD T1MD — PWM1MD —

bit 15 bit 8

R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0I2C1MD — U1MD — SPI1MD — — AD1MD

bit 7 bit 0


bit 15-14 Unimplemented: Read as ‘0’bit 13 T3MD: Timer3 Module Disable bit

1 = Timer3 module is disabled0 = Timer3 module is enabled

bit 12 T2MD: Timer2 Module Disable bit1 = Timer2 module is disabled0 = Timer2 module is enabled

bit 11 T1MD: Timer1 Module Disable bit1 = Timer1 module is disabled0 = Timer1 module is enabled

bit 10 Unimplemented: Read as ‘0’bit 9 PWM1MD: PWM1 Module Disable bit

1 = PWM1 module is disabled0 = PWM1 module is enabled

bit 18 Unimplemented: Read as ‘0’bit 7 I2C1MD: I2C1 Module Disable bit

1 = I2C1 module is disabled0 = I2C1 module is enabled

bit 6 Unimplemented: Read as ‘0’bit 5 U1MD: UART1 Module Disable bit

1 = UART1 module is disabled0 = UART1 module is enabled

bit 4 Unimplemented: Read as ‘0’bit 3 SPI1MD: SPI1 Module Disable bit

1 = SPI1 module is disabled0 = SPI1 module is enabled

bit 2-1 Unimplemented: Read as ‘0’bit 0 AD1MD: ADC1 Module Disable bit(1)

1 = ADC1 module is disabled0 = ADC1 module is enabled

Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode.


dsPIC33FJXXXGSXXX

REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0— — — — — IC3MD IC2MD IC1MD

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0— — — — — — OC2MD OC1MD

bit 7 bit 0


bit 15-11 Unimplemented: Read as ‘0’bit 10 IC3MD: Input Capture 3 Module Disable bit

1 = Input Capture 3 module is disabled0 = Input Capture 3 module is enabled

bit 9 IC2MD: Input Capture 2 Module Disable bit1 = Input Capture 2 module is disabled0 = Input Capture 2 module is enabled

bit 8 IC1MD: Input Capture 1 Module Disable bit1 = Input Capture 1 module is disabled0 = Input Capture 1 module is enabled

bit 7-2 Unimplemented: Read as ‘0’bit 1 OC2MD: Output Compare 2 Module Disable bit

1 = Output Compare 2 module is disabled0 = Output Compare 2 module is enabled

bit 0 OC1MD: Output Compare 1 Module Disable bit1 = Output Compare 1 module is disabled0 = Output Compare 1 module is enabled


dsPIC33FJXXXGSXXX

REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3

REGISTER 10-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0— — — — — CMPMD RTCCMD —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 7 bit 0


bit 15-11 Unimplemented: Read as ‘0’bit 10 CMPMD: Comparator Module Disable bit

1 = Comparator module is disabled0 = Comparator module is enabled

bit 9 RTCCMD: RTCC Module Disable bit1 = RTCC module is disabled0 = RTCC module is enabled


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0— — — — — CTMUMD — —

bit 7 bit 0


bit 15-4 Unimplemented: Read as ‘0’bit 3 CTMUMD: CTMU Module Disable bit

1 = CTMU module is disabled0 = CTMU module is enabled



dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

11.0 I/O PORTS

All of th e device pins (e xcept VDD, VSS, MCLR, andOSC1/CLKI) are shared among the peripherals and theparallel I/O ports. All I/ O input ports feature SchmittTrigger inputs for improved noise immunity.

11.1 Parallel I/O (PIO) PortsGenerally a parallel I/O port that shares a pin with aperipheral is subservie nt to the p eripheral. Theperipheral’s output buffer data and control signals areprovided to a pair of multipl exers. The multiplexersselect whether th e peripheral or the associated porthas ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through,” inwhich a port’ s digital output can drive the input of aperipheral that shares the same pin. Figure 11-1 showshow ports are shared with o ther peripherals and theassociated I/O pin to which they are connected. When a peripheral is enabled and the peripheral isactively driving an associated pin, the use of the pin asa general purpose output pin is disabled. The I/O pincan be read, but the output driver for the parallel port bitis disabled. If a peripheral is enabled, but the peripheralis not actively driving a pin, that pin can be driven by aport.All port pins have three registers directly associatedwith their operation as digital I/O. The data directionregister (TRISx) determines whether the pin is an inputor an output. If the data direction bit is a ‘1’, the pin isan input. All port pins are defined as inputs after aReset. Reads from the latch (LA Tx) read the la tch.Writes to the latch write the latch. Reads from the port(PORTx) read the port pins, while writes to the port pinswrite the latch.Any bit and its associated data and control registersthat are not val id for a particular device will bedisabled. This means the co rresponding LATx andTRISx registers and the port pin will read as zeros.When a pin is shared with another peripheral orfunction that is defined as an in put only, it isnevertheless regarded as a ded icated port becausethere is no other competing source of outputs.

FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not intended to be a compre-hensive reference source. To comple-ment the information in this dat a sheet,refer to Section 10. “I/O Ports”(DS70193) in the “dsPIC33F/PIC24HFamily Reference Manual”, which isavailable from the Microch ip web site(www.microchip.com).


QD

CK

WR LAT +

TRIS Latch

I/O Pin

WR Port

Data Bus

QD

CK

Data Latch

Read Port

Read TRIS

1

0

1

0

WR TRIS

Peripheral Output DataOutput Enable

Peripheral Input Data

I/O

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

Read LAT


dsPIC33FJXXXGSXXX

11.1.1 OPEN-DRAIN CONFIGURATIONIn addition to the PORT, LAT, and TRIS registers fordata control, some po rt pins can also be i ndividuallyconfigured for either digital or open-drain output. Thisis controlled by the Open-Drain Control register,ODCx, associated with ea ch port. Setting any of th ebits configures the corresponding pin to act as anopen-drain output.

The open-drain feature allows the generation ofoutputs higher than VDD (e.g., 5V) on any de sired 5Vtolerant pins by usi ng external pull-up resistors. Themaximum open-drain voltage allowed is the same asthe maximum VIH specification.

See “Pin Diagrams” for the available pins and theirfunctionality.

11.2 Configuring Analog Port PinsThe AD1PCFG and TRIS registers control the opera-tion of the analog-to-digital (A/D) port pins. The portpins that are to function as analog inputs must havetheir corresponding TRIS bit set (input). If the TRIS bitis cleared (output), the digital output level (VOH or VOL)will be converted.

The AD1PCFGL register has a default value of 0x0000;therefore, all pins that share ANx functions are analog(not digital) by default.

When the PORT register is read, all pins configured asanalog input channels will read as cleared (a low level).

Pins configured as di gital inputs will n ot convert ananalog input. Analog levels on any p in defined as adigital input (including the ANx pins) can cause theinput buffer to co nsume current that exceeds thedevice specifications.

11.2.1 I/O PORT WRITE/READ TIMINGOne instruction cycle is requ ired between a portdirection change or port write operation and a readoperation of the same port. T ypically this instructionwould be an NOP. An demonstration is sho wn inExample 11-1.

11.3 Input Change NotificationThe input change notification function of the I/O portsallows the dsPIC33FJXXXGSXXX devices to generateinterrupt requests to the processor in response to achange-of-state on selected input pins. This featurecan detect input change-of-states even in Sleep mode,when the clocks are disabled. Depending on the devicepin count, up to 21 external signals (CNx pin) can beselected (enabled) for generating an interrupt requeston a change-of-state.

Four control registers are associated with the CN mod-ule. The CNEN1 and CNEN2 registers contain theinterrupt enable control bits for each of the CN inputpins. Setting any of these bits enables a CN interruptfor the corresponding pins.

Each CN pin also has a weak pull-up connected to it.The pull-ups act as a current source connected to thepin, and eliminate the need for external resistors whenpush-button or keyp ad devices are con nected. Thepull-ups are enabled separately using the CNPU1 andCNPU2 registers, which cont ain the control bit s foreach of the CN pins. Setting any of th e control bi tsenables the weak pull-ups for the corresponding pins.

EXAMPLE 11-1: PORT WRITE/READ EXAMPLE

Note: Pull-ups on change notification pinsshould always be disabled when the portpin is configured as a digital output.

MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputsMOV W0, TRISBB ; and PORTB<7:0> as outputsNOP ; Delay 1 cyclebtss PORTB, #13 ; Next Instruction


dsPIC33FJXXXGSXXX

11.4 Peripheral Pin SelectPeripheral pin select configuration enables peripheralset selection and placement on a wi de range of I/Opins. By increasing the pinout options available on aparticular device, programmers can better t ailor themicrocontroller to their entire application, rather thantrimming the application to fit the device.

The peripheral pin select configuration feature oper-ates over a fixed subset of digital I/O pins. Program-mers can i ndependently map the input and/or outputof most dig ital peripherals to any one of these I/Opins. Peripheral pin select is pe rformed in so ftware,and generally does not require the device to b ereprogrammed. Hardware safeguards are in cludedthat prevent accidental or spurious changes to th eperipheral mapping, once it has been established.

11.4.1 AVAILABLE PINSThe peripheral pin select feature is used with a rangeof up to 16 pins. The number of available pins dependson the particular device and its pin count. Pins thatsupport the peripheral pin select feature include thedesignation “RPn” i n their full pin designation, where“RP” designates a remappable peripheral and “n” is theremappable pin number.

11.4.2 CONTROLLING PERIPHERAL PIN SELECT

Peripheral pin select features are con trolled throughtwo sets of specia l function registers: one to mapperipheral inputs, and one to map outpu ts. Becausethey are separately controlled, a particular peripheral’sinput and output (if th e peripheral has both) can beplaced on any sele ctable function pin withoutconstraint.

The association of a peripheral to a peripheral select-able pin is handled in two different ways, depending onwhether an input or output is being mapped.

11.4.2.1 Input MappingThe inputs of the pe ripheral pin select optio ns aremapped on the basis of th e peripheral. A co ntrolregister associated with a peripheral dictates the pin itwill be mapped to. The RPINRx registers are used toconfigure peripheral input mapping (see Register 11-1through Register 11-8). Each register contains sets of5-bit fields, with each set a ssociated with one of theremappable peripherals. Programming a gi venperipheral’s bit field with an appropriate 5-bit valuemaps the RPn pin with that value to that p eripheral.For any given device, the valid range of values for anybit field corresponds to the maxi mum number ofperipheral pin selections supported by the device.

Figure 11-2 Illustrates remapp able pin selection forU1RX input.

FIGURE 11-2: REMAPPABLE MUX INPUT FOR U1RX

Note: For input mapping only, the Peripheral PinSelect (PPS) functionality does not havepriority over the TRISx settings. There-fore, when configuring the RPx pin forinput, the corresponding bit in the TRISxregister must also be configured for input(i.e., set to ‘1’).

RP0

RP1

RP2

RP15

0

15

1

2

U1RX input

U1RXR<4:0>

to peripheral


dsPIC33FJXXXGSXXX

TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)

11.4.2.2 Output MappingIn contrast to inputs, the outputs of the peripheral pinselect options are mapped on the basis of the pin. Inthis case, a control register associated with a particularpin dictates the peripheral output to be mapped. TheRPORx registers are used to control output mapping.Like the RPINRx registers, each register contains setsof 5-bit fields, with each set associated with one RPnpin (see Register 11-9 through Register 11-16). Thevalue of the bit field corresponds to one of the periph-erals, and that peripheral’s output is mapped to the pin(see Table 11-2 and Figure 11-3).

The list of peripherals for output mapping also includesa null value of ‘00000’ because of the mappingtechnique. This permits any given pin to remai nunconnected from the output of an y of the pi nselectable peripherals.

FIGURE 11-3: MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn

Input Name Function Name Register ConfigurationBits

External Interrupt 1 INT1 RPINR0 INT1R<4:0>External Interrupt 2 INT2 RPINR1 INT2R<4:0>Timer2 External Clock T2CK RPINR3 T2CKR<4:0>Timer3 External Clock T3CK RPINR3 T3CKR<4:0>Input Capture 1 IC1 RPINR7 IC1R<4:0>Input Capture 2 IC2 RPINR7 IC2R<4:0>Input Capture 3 IC3 RPINR8 IC3R<4:0>Output Compare Fault A OCFA RPINR11 OCFAR<4:0>UART1 Receive U1RX RPINR18 U1RXR<4:0>

UART1 Clear To Send U1CTS RPINR18 U1CTSR<4:0>

SPI1 Slave Select Input SS1 RPINR21 SS1R<4:0>Note 1: Unless otherwise noted, all inputs use the Schmitt input buffers.

0

26

3

RPnR<4:0>

default

U1TX Output enable

U1RTS Output enable 4

UPDN Output enable

19OC2 Output enable

0

26

3

default

U1TX Output

U1RTS Output 4

UPDN Output

19OC2 Output

Output enable

Output DataRPn


dsPIC33FJXXXGSXXX

TABLE 11-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)

11.4.3 CONTROLLING CONFIGURATION CHANGES

Because peripheral remapping can be changed duringrun time, some restrictions on peripheral remapping areneeded to preve nt accidental configuration changes.dsPIC33FJXXXGSXXX devices include three fea turesto prevent alterations to the peripheral map:• Control register lock sequence• Continuous state monitoring• Configuration bit pin select lock

11.4.3.1 Control Register LockUnder normal operation, writes to the RPINRx an dRPORx registers are not allowed. Attempted writesappear to execute no rmally, but the con tents of th eregisters remain unchanged. To change theseregisters, they must be unlocked in hardware. Theregister lock is controlled by th e IOLOCK bit(OSCCON<6>). Setting IOLOCK prevents writes to thecontrol registers; clearing IOLOCK allows writes.To set or clear IOLOCK, a specific command sequencemust be executed:1. Write 0x46 to OSCCON<7:0>.2. Write 0x57 to OSCCON<7:0>.3. Clear (or set) IOLOCK as a single operation.

Unlike the similar sequence with the oscillator’s LOCKbit, IOLOCK remains in one state until changed. Thisallows all of the peripheral pin selects to be configuredwith a single unlock sequence followed by an update toall control registers, then locked with a se cond locksequence.

11.4.3.2 Continuous State MonitoringIn addition to b eing protected from dire ct writes, thecontents of the RPINRx and RPORx registers areconstantly monitored in hardware by shadow registers.If an unexpected change in any of the registers occurs(such as cell disturbances caused by ESD o r otherexternal events), a configuration mismatch Reset willbe triggered.

11.4.3.3 Configuration Bit Pin Select LockAs an additional level of safety , the device can beconfigured to prevent more than one write session tothe RPINRx an d RPORx r egisters. The IOL1WAY(FOSC<IOL1WAY>) configuration bit blocks theIOLOCK bit from b eing cleared after it has been setonce. If IOLOCK remain s set, the register unlockprocedure will not execute, and the peripheral pinselect control registers cannot be written to . The onlyway to clear the bit and re-enable peripheral remappingis to perform a device Reset.

In the default (unprogrammed) state, IOL1WAY is set,restricting users to on e write session. ProgrammingIOL1WAY allows user applications unlimited access(with the p roper use of the unlock sequence) to theperipheral pin select registers.

11.5 Peripheral Pin Select RegistersThe dsPIC33FJXXXGSXXX family of devicesimplement 21 regi sters for re mappable peripheralconfiguration:

• Input Remappable Peripheral Registers (13)• Output Remappable Peripheral Registers (8)

Function RPnR<4:0> Output NameNULL 00000 RPn tied to default port pin

C1OUT 00001 RPn tied to Comparator 1 OutputC2OUT 00010 RPn tied to Comparator 2 OutputU1TX 00011 RPn tied to UART1 Transmit

U1RTS 00100 RPn tied to UART1 Ready To SendSS1 01001 RPn tied to SPI1 Slave Select OutputOC1 10010 RPn tied to Output Compare 1OC2 10011 RPn tied to Output Compare 2

CTPLS 11101 RPn tied to CTMU Pulse OutputC3OUT 11110 RPn tied to Comparator 3 Output

Note: MPLAB® C30 p rovides built-in Clanguage functions for unl ocking theOSCCON register:__builtin_write_OSCCONL(value)__builtin_write_OSCCONH(value)

See MPLAB IDE Help for moreinformation.

Note: Input and Output Register values can onlybe changed if OSC CON<IOLOCK> = 0.See Section 11.4.3.1 “Control RegisterLock” for a specific command sequence.


dsPIC33FJXXXGSXXX

REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1— — — INT1R<4:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 7 bit 0


bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin

11111 = Input tied VSS01111 = Input tied to RP15...00001 = Input tied to RP100000 = Input tied to RP0



dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1— — — INT2R<4:0>

bit 7 bit 0


bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin



dsPIC33FJXXXGSXXX


U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1— — — T3CKR<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1— — — T2CKR<4:0>

bit 7 bit 0


bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin


bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin



dsPIC33FJXXXGSXXX


U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1— — — IC2R<4:0>

bit 15 bit 8


bit 7 bit 0


bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin


bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin



dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8


bit 7 bit 0


bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R<4:0>: Assign Input Capture 3 (IC3) to the corresponding pin RPn pin



dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1— — — OCFAR<4:0>

bit 7 bit 0


bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin



dsPIC33FJXXXGSXXX


U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1— — — U1CTSR<4:0>

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1— — — U1RXR<4:0>

bit 7 bit 0


bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin


bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin



dsPIC33FJXXXGSXXX


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1— — — SS1R<4:0>

bit 7 bit 0


bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin



dsPIC33FJXXXGSXXX

REGISTER 11-9: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — — RP1R<4:0>

bit 15 bit 8


bit 7 bit 0


bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 11-2 for

peripheral function numbers)bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 11-2 for

peripheral function numbers)



bit 15 bit 8


bit 7 bit 0






dsPIC33FJXXXGSXXX



bit 15 bit 8


bit 7 bit 0







bit 15 bit 8


bit 7 bit 0






dsPIC33FJXXXGSXXX



bit 15 bit 8


bit 7 bit 0







bit 15 bit 8


bit 7 bit 0






dsPIC33FJXXXGSXXX



bit 15 bit 8


bit 7 bit 0







bit 15 bit 8


bit 7 bit 0






dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

12.0 SERIAL PERIPHERAL INTERFACE (SPI)

The Serial Peripheral Interface (SPI) module is a syn-chronous serial interface useful for communicating withother peripheral or microcontroller devices. Theseperipheral devices can be serial EEPROMs, shif t regis-ters, display drivers, analog-to-digital converters, etc.The SPI module is compatible with SPI and SIOP fromMotorola®.

Each SPI module consists of a 16-bit shift register,SPIxSR (where x = 1 or 2), used for shifting data in andout, and a buf fer register, SPIxBUF. A control register,SPIxCON, configures the module. Additionally, a statusregister, SPIxSTAT, indicates status conditions.

The serial interface consists of four pins:

• SDIx (serial data input)• SDOx (serial data output)• SCKx (shift clock input or output)• SSx (active low slave select).

In Master mode operation, SCK is a clock output. InSlave mode, it is a clock input.

FIGURE 12-1: SPI MODULE BLOCK DIAGRAM

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not inten ded to b e acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 18. “SerialPeripheral Interface (SPI)” (DS70206)in the “dsPIC33F/PIC24H FamilyReference Manual”, which is ava ilablefrom the Microchi p web site(www.microchip.com).


Internal Data Bus

SDIx

SDOx

SSx

SCKx

SPIxSRbit 0

Shift Control

EdgeSelect

FCYPrimary1:1/4/16/64

Enable

Prescaler

Sync

SPIxBUF

Control

TransferTransfer

Write SPIxBUFRead SPIxBUF

16

SPIxCON1<1:0>

SPIxCON1<4:2>

Master Clock

ClockControl

SecondaryPrescaler

1:1 to 1:8

SPIxRXB SPIxTXB


dsPIC33FJXXXGSXXX

12.1 SPI Helpful Tips1. In Frame mode, if there is a possibility that the

master may not be initialized before the slave:a) If FRMPOL (SPIxCON2<13>) = 1, use a

pull-down resistor on SSx.b) If FRMPOL = 0, use a pull-up resistor on

SSx.

2. In non-framed 3-wire mode, (i.e., not using SSxfrom a master):a) If CKP (SPIxCON1<6>) = 1, always place a

pull-up resistor on SSx.b) If CKP = 0, always place a pu ll-down

resistor on SSx.

3. FRMEN (SPIxCON2<15>) = 1 and SSEN(SPIxCON1<7>) = 1 are exclusive and invalid.In Frame mode , SCKx is continuous and theFrame sync pulse is active on the SSx pin,which indicates the start of a data frame.

4. In Master mod e only, set the SMP bit(SPIxCON1<9>) to a ‘1’ for the fastest SPI datarate possible. The SMP bit can only be set at thesame time or after the MSTEN bit(SPIxCON1<5>) is set.

5. To avoid invalid slave read data to the master,the user’s master software must guaranteeenough time for slave software to fill its write buf-fer before the user application initiates a masterwrite/read cycle. It is always advisable to pre-load the SPIxBUF transmit register in advanceof the next master transaction cycle. SPIxBUF istransferred to the SPI shift register and is emptyonce the data transmission begins.

12.1.1 SPI RESOURCES

SPI Code Samples:http://wwwcontribution/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2914&param=en552694

Family Reference Manual Chaptershttp://ww1.microchip.com/downloads/en/DeviceDoc/70206C.pdf

Webseminar: Serial Peripheral Interface (SPI) Modulehttp://techtrain.microchip.com/webseminars/ArchivedDetail.aspx?Active=89

Application Notes and Software LibrariesAN1096 “Using the C30 Compiler and the SPI moduleto Interface EEPROMs with dsPIC33F and PIC24F”

http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1824&appnote=en527719

Note: This insures that the first frametransmission after initialization is no tshifted or corrupted.

Note: Note: This will insure that during power-upand initialization the master/slave will notlose sync due to an errant SCK transitionthat would cause the slave to accumulatedata shift errors for both transmit andreceive appearing as corrupted data.

Note: Not all third-party devices support Framemode timing. Refer to the SPI electricalcharacteristics for details.

Note: Please refer to the Microchip website(www.microchip.com) for the latestupdates and for additional information.


http://wwwcontribution/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2914&param=en552694

http://ww1.microchip.com/downloads/en/DeviceDoc/70206C.pdf



http://techtrain.microchip.com/webseminars/ArchivedDetail.aspx?Active=89


dsPIC33FJXXXGSXXX

REGISTER 12-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0SPIEN — SPISIDL — — — — —

bit 15 bit 8

U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0— SPIROV — — — — SPITBF SPIRBF

bit 7 bit 0

Legend: C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 SPIEN: SPIx Enable bit1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins0 = Disables module

bit 14 Unimplemented: Read as ‘0’bit 13 SPISIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’bit 6 SPIROV: Receive Overflow Flag bit

1 = A new byte/word i s completely received and discarded. The user software has no t read theprevious data in the SPIxBUF register

0 = No overflow has occurred.bit 5-2 Unimplemented: Read as ‘0’bit 1 SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit not yet started, SPIxTXB is full0 = Transmit started, SPIxTXB is emptyAutomatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXBAutomatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR

bit 0 SPIRBF: SPIx Receive Buffer Full Status bit1 = Receive complete, SPIxRXB is full0 = Receive is not complete, SPIxRXB is emptyAutomatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXBAutomatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB


dsPIC33FJXXXGSXXX

REGISTER 12-2: SPIXCON1: SPIx CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — — DISSCK DISSDO MODE16 SMP CKE(1)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0SSEN(2) CKP MSTEN SPRE<2:0>(3) PPRE<1:0>(3)

bit 7 bit 0


bit 15-13 Unimplemented: Read as ‘0’bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)

1 = Internal SPI clock is disabled, pin functions as I/O0 = Internal SPI clock is enabled

bit 11 DISSDO: Disable SDOx pin bit1 = SDOx pin is not used by module; pin functions as I/O0 = SDOx pin is controlled by the module

bit 10 MODE16: Word/Byte Communication Select bit1 = Communication is word-wide (16 bits)0 = Communication is byte-wide (8 bits)

bit 9 SMP: SPIx Data Input Sample Phase bitMaster mode:1 = Input data sampled at end of data output time0 = Input data sampled at middle of data output timeSlave mode:SMP must be cleared when SPIx is used in Slave mode.

bit 8 CKE: SPIx Clock Edge Select bit(1)

1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

bit 7 SSEN: Slave Select Enable bit(2) (Slave mode)1 = SSx pin used for Slave mode0 = SSx pin not used by module. Pin controlled by port function

bit 6 CKP: Clock Polarity Select bit1 = Idle state for clock is a high level; active state is a low level0 = Idle state for clock is a low level; active state is a high level

bit 5 MSTEN: Master Mode Enable bit1 = Master mode0 = Slave mode

Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1).

2: This bit must be cleared when FRMEN = 1.3: Do not set both Primary and Secondary prescalers to a value of 1:1.


dsPIC33FJXXXGSXXX

bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3)

111 = Secondary prescale 1:1110 = Secondary prescale 2:1...000 = Secondary prescale 8:1

bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3)

11 = Primary prescale 1:110 = Primary prescale 4:101 = Primary prescale 16:100 = Primary prescale 64:1

REGISTER 12-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)

Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1).

2: This bit must be cleared when FRMEN = 1.3: Do not set both Primary and Secondary prescalers to a value of 1:1.


dsPIC33FJXXXGSXXX

REGISTER 12-3: SPIxCON2: SPIx CONTROL REGISTER 2

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0FRMEN SPIFSD FRMPOL — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0— — — — — — FRMDLY —

bit 7 bit 0


bit 15 FRMEN: Framed SPIx Support bit1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)0 = Framed SPIx support disabled

bit 14 SPIFSD: Frame Sync Pulse Direction Control bit1 = Frame sync pulse input (slave)0 = Frame sync pulse output (master)

bit 13 FRMPOL: Frame Sync Pulse Polarity bit1 = Frame sync pulse is active-high0 = Frame sync pulse is active-low

bit 12-2 Unimplemented: Read as ‘0’bit 1 FRMDLY: Frame Sync Pulse Edge Select bit

1 = Frame sync pulse coincides with first bit clock0 = Frame sync pulse precedes first bit clock

bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application.


dsPIC33FJXXXGSXXX

13.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)

The Universal Asynchronous Receiver Transmitter(UART) module is one of the serial I/O modulesavailable in the dsPIC33FJXXXGSXXX device family.The UART is a ful l-duplex asynchronous system thatcan communicate with peripheral devices, such aspersonal computers, LIN 2.0, and RS-232, and RS-485interfaces. The module also supports a hardware flowcontrol option with the UxCTS and UxRTS pins andalso includes an IrDA® encoder and decoder.

The primary features of the UART module are:

• Full-Duplex, 8-bit or 9-bit Data Transmission through the UxTX and UxRX pins

• Even, Odd, or No Parity Options (for 8-bit data)• One or two stop bits• Hardware flow control option with UxCTS and

UxRTS pins• Fully integrated Baud Rate Generator with 16-bit

prescaler• Baud rates ranging from 0.4 Mbps to 6 bps at 16x

mode at 16 MIPS• Baud rates ranging from 1.6 Mbps to 24.4 bps at 4x

mode at 16 MIPS• 4-deep First-In First-Out (FIFO) Transmit Data

buffer• 4-deep FIFO Receive Data buffer• Parity, framing and buffer overrun error detection• Support for 9-bit mode with Address Detect

(9th bit = 1)• Transmit and Receive interrupts• A separate interrupt for all UART error conditions• Loopback mode for diagnostic support• Support for sync and break characters• Support for automatic baud rate detection• IrDA® encoder and decoder logic• 16x baud clock output for IrDA® support

A simplified block diagram of th e UART module isshown in Figure 13-1. The UART module consists ofthese key hardware elements:

• Baud Rate Generator• Asynchronous Transmitter• Asynchronous Receiver

FIGURE 13-1: UART SIMPLIFIED BLOCK DIAGRAM

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not inten ded to b e acomprehensive reference source. Tocomplement the information in this datasheet, refer to Section 17. “UART”(DS70188) in the “dsPIC33F/PIC24HFamily Reference Manual”, which isavailable from the Microch ip web site(www.microchip.com).

2: Some registers and associated bitsdescribed in this section may not beavailable on all devices. Refer toSection 5.0 “Memory Organization” inthis data sheet for device-specific registerand bit information.

UxRX

Hardware Flow Control

UART Receiver

UART Transmitter UxTX

BCLK

Baud Rate Generator

UxRTS

IrDA®

UxCTS


dsPIC33FJXXXGSXXX

13.1 UART Helpful Tips1. In multi-node direct-connect UART networks,

UART receive inputs react to th ecomplementary logic level defined by th eURXINV bit (UxMODE< 4>), which defines theidle state, the default of which is logic high, (i.e.,URXINV = 0). Because remote devices do notinitialize at the same time, it is likely that one ofthe devices, because the RX line is floating, willtrigger a start bit detection and will cause thefirst byte received after the device has been ini-tialized to be invalid. To avoid this situation, theuser should use a pull-up or pul l-down resistoron the R X pin depending on the valu e of th eURXINV bit.a) If URXINV = 0, use a pull-up resistor on the

RX pin.b) If URXINV = 1, use a pull-down resistor on

the RX pin. 2. The first character received on a wake-up from

Sleep mode caused by activity on the UxRX pinof the UART module will be inval id. In Sleepmode, peripheral clocks are disab led. By thetime the oscillator system has re started andstabilized from Sle ep mode, the baud rate bitsampling clock relative to the incoming UxRX bittiming is no longer synchronized, resulting in thefirst character being invalid. This is to beexpected.

13.1.1 UART RESOURCES

UART Code Sampleshttp://wwwcontribution/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2914&param=en552697

Family Reference Manual Chapterhttp://ww1.microchip.com/downloads/en/DeviceDoc/70188D.pdf

Webseminar: Universal Asynchronous Receiver Transmitter (UART) Modulehttp://techtrain.microchip.com/webseminars/ArchivedDetail.aspx?Active=90

Application Notes and Software LibrariesAN1094 “UART Bootloader for dsPIC30F/33F andPIC24F/24H Devices”

http://www.microchip.com/stellent/idcplg?IdcSer-vice=SS_GET_PAGE&nodeId=1824&appnote=en530200




http://ww1.microchip.com/downloads/en/DeviceDoc/70188D.pdf





dsPIC33FJXXXGSXXX

REGISTER 13-1: UxMODE: UARTx MODE REGISTER

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0UARTEN(1) — USIDL IREN(2) RTSMD — UEN<1:0>

bit 15 bit 8

R/W-0 HC R/W-0 R/W-0 HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

bit 7 bit 0

Legend: HC = Hardware clearedR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 UARTEN: UARTx Enable bit(1)

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption

minimalbit 14 Unimplemented: Read as ‘0’bit 13 USIDL: Stop in Idle Mode bit


bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)

1 = IrDA encoder and decoder enabled0 = IrDA encoder and decoder disabled

bit 11 RTSMD: Mode Selection for UxRTS Pin bit1 = UxRTS pin in Simplex mode0 = UxRTS pin in Flow Control mode

bit 10 Unimplemented: Read as ‘0’bit 9-8 UEN<1:0>: UARTx Enable bits

11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by

port latchesbit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge

0 = No wake-up enabledbit 6 LPBACK: UARTx Loopback Mode Select bit

1 = Enable Loopback mode0 = Loopback mode is disabled

bit 5 ABAUD: Auto-Baud Enable bit1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h)

before other data; cleared in hardware upon completion0 = Baud rate measurement disabled or completed

Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation.

2: This feature is only available for the 16x BRG mode (BRGH = 0).


dsPIC33FJXXXGSXXX

bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’0 = UxRX Idle state is ‘1’

bit 3 BRGH: High Baud Rate Enable bit1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)

bit 2-1 PDSEL<1:0>: Parity and Data Selection bits11 = 9-bit data, no parity10 = 8-bit data, odd parity01 = 8-bit data, even parity00 = 8-bit data, no parity

bit 0 STSEL: Stop Bit Selection bit1 = Two Stop bits0 = One Stop bit

REGISTER 13-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation.

2: This feature is only available for the 16x BRG mode (BRGH = 0).


dsPIC33FJXXXGSXXX

REGISTER 13-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

bit 7 bit 0

Legend: HC = Hardware cleared C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the

transmit buffer becomes empty01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operations are completed00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is

at least one character open in the transmit buffer)bit 14 UTXINV: Transmit Polarity Inversion bit

If IREN = 0:1 = UxTX Idle state is ‘0’0 = UxTX Idle state is ‘1’

If IREN = 1:1 = IrDA encoded UxTX Idle state is ‘1’0 = IrDA encoded UxTX Idle state is ‘0’

bit 12 Unimplemented: Read as ‘0’bit 11 UTXBRK: Transmit Break bit

1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;cleared by hardware upon completion

0 = Sync Break transmission disabled or completedbit 10 UTXEN: Transmit Enable bit(1)

1 = Transmit enabled, UxTX pin controlled by UARTx0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled

by portbit 9 UTXBF: Transmit Buffer Full Status bit (read-only)

1 = Transmit buffer is full0 = Transmit buffer is not full, at least one more character can be written

bit 8 TRMT: Transmit Shift Register Empty bit (read-only)1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)0 = Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)0x = Interrupt is se t when any character is received and transferred from the UxRSR to th e receive

buffer. Receive buffer has one or more characters

Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation.


dsPIC33FJXXXGSXXX

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect0 = Address Detect mode disabled

bit 4 RIDLE: Receiver Idle bit (read-only)1 = Receiver is Idle0 = Receiver is active

bit 3 PERR: Parity Error Status bit (read-only)1 = Parity error has been detected for the current character (character at the top of the receive FIFO)0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (read-only)1 = Framing error has been detected for th e current character (character at the top of th e receive

FIFO)0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit (read-only/clear-only)1 = Receive buffer has overflowed0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1 0 transition) will reset

the receiver buffer and the UxRSR to the empty statebit 0 URXDA: Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read0 = Receive buffer is empty

REGISTER 13-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation.


dsPIC33FJXXXGSXXX

14.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)

The dsPIC33FJXXXGSXXX devices have up to sixADC module input channels.

14.1 Key FeaturesThe 10-bit ADC configuration has the following keyfeatures:

• Successive Approximation (SAR) conversion• Conversion speeds of up to 1.1 Msps• Up to six analog input pins• Four Sample and Hold circuits for simultaneous

sampling of up to four analog input pins• Automatic Channel Scan mode• Selectable conversion trigger source• Selectable Buffer Fill modes• Four result alignment options (signed/unsigned,

fractional/integer)• Operation during CPU Sleep and Idle modes• 16-word conversion result buffer

Depending on the p articular device pinout, the ADCcan have up to six analog input pins, designated AN0through AN5.

Block diagrams of th e ADC modu le are shown inFigure 14-1 and Figure 14-2.

14.2 ADC InitializationTo configure the ADC module:

1. Select port pins as analog inputs(ADxPCFGH<15:0> or ADxPCFGL<15:0>).

2. Select voltage reference source to matchexpected range on anal og inputs(ADxCON2<15:13>).

3. Select the analog conversion clock to match thedesired data rate with the processor clock(ADxCON3<7:0>).

4. Determine how many sample-and-hold chan-nels will b e used (ADxCON2<9:8> a ndADxPCFGH<15:0> or ADxPCFGL<15:0>).

5. Select the appropriate sample/conversionsequence (ADxCON1<7:5> andADxCON3<12:8>).

6. Select the way conversion results are presentedin the buffer (ADxCON1<9:8>).

7. Turn on the ADC module (ADxCON1<15>).8. Configure ADC interrupt (if required):

a) Clear the ADxIF bit.b) Select the ADC interrupt priority.

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX family ofdevices. It is not intended to be a compre-hensive reference source. To comple-ment the information in this dat a sheet,refer to Section 16. “Analog-to-DigitalConverter (ADC)” (DS70183) in the“dsPIC33F/PIC24H Family ReferenceManual”, which is ava ilable from theMicrochip web site(www.microchip.com).



dsPIC33FJXXXGSXXX

FIGURE 14-1: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ16GP101 AND dsPIC33FJ16MC101 DEVICES

SAR ADC

S/H0

S/H1

ADC1BUF0ADC1BUF1ADC1BUF2

ADC1BUFFADC1BUFE

AN0

AN3

AN1

AVss

CH0SB<4:0>

CH0NA CH0NB

+

-

AN0

AN3

CH123SA

AVss

CH123SB

CH123NA CH123NB

+

-

S/H2

AN1

CH123SA

AVss

CH123SB

CH123NA CH123NB

+

-

S/H3

AN2

CH123SA

AVss

CH123SB

CH123NA CH123NB

+

-

CH1

CH0

CH2

CH3

CH0SA<4:0>

ChannelScan

CSCNA

Alternate

AVDD AVSS

Input Selection

VREFH VREFL

CTMU(1)

Note 1: Internally connected to CTMU temperature sensor.


dsPIC33FJXXXGSXXX

FIGURE 14-2: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ16GP102 ANDdsPIC33FJ16MC102 DEVICES

SAR ADC

S/H0

S/H1

ADC1BUF0ADC1BUF1ADC1BUF2

ADC1BUFFADC1BUFE

AN0

AN5

AN1

AVss

CH0SB<4:0>

CH0NA CH0NB

+

-

AN0

AN3

CH123SA

AVss

CH123SB

CH123NA CH123NB

+

-

S/H2

AN1

AN4

CH123SA

AVss

CH123SB

CH123NA CH123NB

+

-

S/H3

AN2

AN5

CH123SA

AVss

CH123SB

CH123NA CH123NB

+

-

CH1

CH0

CH2

CH3

CH0SA<4:0>

ChannelScan

CSCNA

Alternate Input Selection

VREFH VREFL

AVDD AVSS

CTMU(1)

Note 1: Internally connected to CTMU temperature sensor.


dsPIC33FJXXXGSXXX

FIGURE 14-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

0

1

ADC Internal RC Clock(1)

TOSC(1) X2

ADC Conversion Clock Multiplier

1, 2, 3, 4, 5,..., 64

ADxCON3<15>

TCY

TAD

6

ADxCON3<5:0>

Note 1: See the ADC specifications in Section 18.0 “Electrical Characteristics” for the exact RC clock value.


dsPIC33FJXXXGSXXX
14.3 ADC Helpful Tips1. The SMPI<3:0> (AD1CON2<5:2>) control bits:
a) Determine when the ADC interrup t flag isset and an interrupt is generated if enabled.

b) When the CSCNA b it (AD1CON2<10>) isset to ‘1’, determines when the ADC analogscan channel list defined in the AD1CSSL/AD1CSSH registers starts over from thebeginning.

c) On devices without a DMA peripheral,determines when ADC result buffer pointerto ADC1BUF0-ADC1BUFF, gets reset backto the beginning at ADC1BUF0.

2. On devices without a DMA module, the ADC has16 result buf fers. ADC conversion result s arestored sequentially in ADC1 BUF0-ADC1BUFFregardless of whi ch analog inputs are bein gused subject to the SMPI<3:0> bits(AD1CON2<5:2>) and the condition describedin 1c above. There is no relationship betweenthe ANx input being measured and which ADCbuffer (ADC1BUF0-ADC1BUFF) that theconversion results will be placed in.

3. On devices with a DMA module, the ADC mod-ule has only 1 ADC result buffer, (i.e.,ADC1BUF0), per ADC peripheral and the ADCconversion result must be read either by theCPU or DMA controller before the n ext ADCconversion is complete to avoid overwriting theprevious value.

4. The DONE bit (AD1CON1<0>) is only cleared atthe start of ea ch conversion and is se t at thecompletion of the conversion, but remains setindefinitely even through the next sample phaseuntil the next conversio n begins. If app licationcode is monitoring the DONE bit in any kind ofsoftware loop, the user must consider thisbehavior because the CPU code execution isfaster than the ADC. As a result, in manual sam-ple mode, particularly where the users code issetting the SAMP b it (AD1CON1<1>), theDONE bit shoul d also be cle ared by the userapplication just before setting the SAMP bit.

5. On devices with two AD C modules, theADCxPCFG registers for bo th ADC modu lesmust be set to a logic ‘ 1’ to configure a targetI/O pin as a d igital I/O pin. Failure to do someans that any alterna te digital input functionwill always see only a logic ‘0’ as th e digitalinput buffer is held in Disable mode.

14.3.1 ADC RESOURCES

ADC Code Sampleshttp://wwwcontribution/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2914&param=en552700

Techniques That Reduce System Noise in ADC Circuitshttp://techtrain.microchip.com/webseminars/ArchivedDetail.aspx?Active=40

Webseminar: dsPIC30F 12-bit ADC Module Part 1 (Similar to dsPIC33F)http://techtrain.microchip.com/webseminars/ArchivedDetail.aspx?Active=82




Application Notes and Software LibrariesAN1152 “Achieving Higher ADC Resolution UsingOversampling”


AN699 “Anti-Aliasing, Analog Filters for Data Acquisi-tion Systems”














dsPIC33FJXXXGSXXX

REGISTER 14-1: AD1CON1: ADC1 CONTROL REGISTER 1

R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0ADON — ADSIDL — — — FORM<1:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0HC,HS

R/C-0HC, HS

SSRC<2:0> — SIMSAM ASAM SAMP DONEbit 7 bit 0

Legend: HC = Cleared by hardware HS = Set by hardware C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADON: ADC Operating Mode bit1 = ADC module is operating0 = ADC is off

bit 14 Unimplemented: Read as ‘0’bit 13 ADSIDL: Stop in Idle Mode bit


bit 12-10 Unimplemented: Read as ‘0’bit 9-8 FORM<1:0>: Data Output Format bits

11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>)10 = Fractional (DOUT = dddd dddd dd00 0000)01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>)00 = Integer (DOUT = 0000 00dd dddd dddd)

bit 7-5 SSRC<2:0>: Sample Clock Source Select bits111 = Internal counter ends sampling and starts conversion (auto-convert)110 = CTMU101 = Reserved100 = Reserved011 = Motor Control PWM interval ends sampling and starts conversion(1)

010 = GP timer 3 compare ends sampling and starts conversion001 = Active transition on INT0 pin ends sampling and starts conversion000 = Clearing sample bit ends sampling and starts conversion

bit 4 Unimplemented: Read as ‘0’bit 3 SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01 or 1x)

1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); orSamples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)

0 = Samples multiple channels individually in sequencebit 2 ASAM: ADC Sample Auto-Start bit

1 = Sampling begins immediately after last conversion. SAMP bit is auto-set0 = Sampling begins when SAMP bit is set

Note 1: Available only on dsPIC33FJ15MC101/102 devices.


dsPIC33FJXXXGSXXX

bit 1 SAMP: ADC Sample Enable bit1 = ADC sample-and-hold amplifiers are sampling0 = ADC sample-and-hold amplifiers are holdingIf ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC 000, automatically cleared by hardware to end sampling and start conversion.

bit 0 DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed0 = ADC conversion not started or in progressAutomatically set by hardwa re when ADC conversio n is complete. Software can write ‘ 0’ to clearDONE status (software not allowed to write ‘1’). Clearing this bit will NOT af fect any operation inprogress. Automatically cleared by hardware at start of a new conversion.

REGISTER 14-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)

Note 1: Available only on dsPIC33FJ15MC101/102 devices.


dsPIC33FJXXXGSXXX


R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0VCFG<2:0> — — CSCNA CHPS<1:0>

bit 15 bit 8

R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0BUFS — SMPI<3:0> BUFM ALTS

bit 7 bit 0


bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits

bit 12-11 Unimplemented: Read as ‘0’bit 10 CSCNA: Scan Input Selections for CH0+ during Sample A bit

1 = Scan inputs0 = Do not scan inputs

bit 9-8 CHPS<1:0>: Select Channels Utilized bits1x =Converts CH0, CH1, CH2 and CH301 =Converts CH0 and CH100 =Converts CH0

bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)1 = ADC is currently filling second half of buffer, user should access data in the first half0 = ADC is currently filling first half of buffer, user application should access data in the second half

bit 6 Unimplemented: Read as ‘0’bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits

1111 =Interrupts at the completion of conversion for each 16th sample/convert sequence1110 =Interrupts at the completion of conversion for each 15th sample/convert sequence•••0001 =Interrupts at the completion of conversion for each 2nd sample/convert sequence0000 =Interrupts at the completion of conversion for each sample/convert sequence

bit 1 BUFM: Buffer Fill Mode Select bit1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt0 = Always starts filling buffer from the beginning

bit 0 ALTS: Alternate Input Sample Mode Select bit1 = Uses channel input selects for Sample A on first sample and Sample B on next sample0 = Always uses channel input selects for Sample A

ADREF+ ADREF-

xxx AVDD AVSS


dsPIC33FJXXXGSXXX


R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ADRC — — SAMC<4:0>(1)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ADCS<7:0>(2)

bit 7 bit 0


bit 15 ADRC: ADC Conversion Clock Source bit1 = ADC internal RC clock0 = Clock derived from system clock

bit 14-13 Unimplemented: Read as ‘0’bit 12-8 SAMC<4:0>: Auto Sample Time bits(1)

11111 = 31 TAD

•••00001 = 1 TAD00000 = 0 TAD

bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2)

11111111 = Reserved••••01000000 = Reserved00111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD

•••00000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD 00000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD

Note 1: This bit only used if AD1CON1<7:5> (SSRC<2:0>) = 1.2: This bit is not used if AD1CON3<15> (ADRC) = 1.


dsPIC33FJXXXGSXXX

REGISTER 14-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0— — — — — CH123NB<1:0> CH123SB

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0— — — — — CH123NA<1:0> CH123SA

bit 7 bit 0


bit 15-11 Unimplemented: Read as ‘0’bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits

11 = Reserved10 = Reserved0x = CH1, CH2, CH3 negative input is AVss

bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bitdsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only:1 = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

dsPIC33FJ16GP102 and dsPIC33FJ16MC102 devices only:1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN50 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

bit 7-3 Unimplemented: Read as ‘0’bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits

11 = Reserved10 = Reserved0x = CH1, CH2, CH3 negative input is AVss

bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bitdsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only:1 = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

dsPIC33FJ16GP102 and dsPIC33FJ16MC102 devices only:1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN50 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2


dsPIC33FJXXXGSXXX

REGISTER 14-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTERR/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NB — — CH0SB<4:0>(1)

bit 15 bit 8

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CH0NA — — CH0SA<4:0>(1)

bit 7 bit 0


bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit1 = Channel 0 negative input is AN10 = Channel 0 negative input is AVss

bit 14-13 Unimplemented: Read as ‘0’bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits(1)

dsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only:01101 = CTMU Temperature Sensor00011 = Channel 0 positive input is AN300010 = Channel 0 positive input is AN200001 = Channel 0 positive input is AN100000 = Channel 0 positive input is AN0

dsPIC33FJ16GP102 and dsPIC33FJ16MC102 devices only:01101 = CTMU Temperature Sensor00101 = Channel 0 positive input is AN500100 = Channel 0 positive input is AN400011 = Channel 0 positive input is AN300010 = Channel 0 positive input is AN200001 = Channel 0 positive input is AN100000 = Channel 0 positive input is AN0

bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit1 = Channel 0 negative input is AN10 = Channel 0 negative input is AVss

bit 6-5 Unimplemented: Read as ‘0’bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits(1)

dsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only:01101 = CTMU Temperature Sensor00011 = Channel 0 positive input is AN300010 = Channel 0 positive input is AN200001 = Channel 0 positive input is AN100000 = Channel 0 positive input is AN0

dsPIC33FJ16GP102 and dsPIC33FJ16MC102 devices only:01101 = CTMU Temperature Sensor00101 = Channel 0 positive input is AN500100 = Channel 0 positive input is AN400011 = Channel 0 positive input is AN300010 = Channel 0 positive input is AN200001 = Channel 0 positive input is AN100000 = Channel 0 positive input is AN0

Note 1: All other values than those listed are Reserved.


dsPIC33FJXXXGSXXX

,2

REGISTER 14-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2,3)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0

bit 7 bit 0


bit 15-6 Unimplemented: Read as ‘0’bit 5-0 CSS<5:0>: ADC Input Scan Selection bits

1 = Select ANx for input scan0 = Skip ANx for input scan

Note 1: On devices without 6 analog inputs, all AD1CSSL bits can be selected by user application. However, inputs selected for scan without a corresponding input on device converts VREFL.

2: CSSx = ANx, where x = 0 through 5.3: CTMU temperature sensor input cannot be scanned.


dsPIC33FJXXXGSXXX

REGISTER 14-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — PCFG5(4) PCFG4(4) PCFG3(4) PCFG2(4) PCFG1(4) PCFG0(4)

bit 7 bit 0


bit 15-6 Unimplemented: Read as ‘0’bit 5-0 PCFG<5:0>: ADC Port Configuration Control bits(4)

1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage

Note 1: On devices without 6 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on ports without a corresponding input on device.

2: PCFGx = ANx, where x = 0 through 5.3: PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx register. When

the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode.4: Pins shared with analog functions (i.e., ANx), are analog by default and therefore, must be set by the user

to enable any digital function on that pin. Reading any port pin with the analog function enabled will return a ‘0’, regardless of the signal input level.


dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

15.0 SPECIAL FEATURES

dsPIC33FJXXXGSXXX devices include severalfeatures intended to maximize application flexibility andreliability, and minimize cost throug h elimination ofexternal components. These are:• Flexible configuration• Watchdog Timer (WDT)• Code Protection• JTAG Boundary Scan Interface• In-Circuit Serial Programming™ (ICSP™)• In-Circuit emulation

15.1 Configuration BitsThe Configuration Shadow register bits can be config-ured (read as ‘0’), or left unprogrammed (read as ‘1’),to select various device configurations. These read-only bits are mapped starting at program memory loca-tion 0xF80000. A detailed explanation of the various bitfunctions is provided in Table 15-3.

Note that address 0xF80000 is beyond the user pro-gram memory space and belongs to the configurationmemory space (0x800000-0xFFFFFF) which can onlybe accessed using table reads.

In dsPIC33FJXXXGSXXX devices, the configurationbytes are implemented as volatile memory. This meansthat configuration data must be programmed each timethe device is powered up. Configuration data is stored inthe two words at the top of the on-chip program memoryspace, known as the Flash Configuration Words. Theirspecific locations are shown in Table 15-2. These arepacked representations of the actual device Configura-tion bits, whose actual locations are distributed amongseveral locations in configuration space. The configura-tion data is automatically loaded from the Flash Config-uration Words to the proper Configuration registersduring device Resets.

When creating applications for these devices, usersshould always specifically allocate the location of theFlash Configuration Word for configuration data. This isto make certain that program code is not stored in thisaddress when the code is compiled.

The upper byte of all Flash Configuration Words in pro-gram memory should always be ‘1111 1111’. Thismakes them appear to be NOP instructions in theremote event that their locations are ever executed byaccident. Since Configuration bits are not implementedin the corresponding locations, writing ‘ 1’s to th eselocations has no effect on device operation.

The Configuration Shadow register map is shown inTable 15-1.

Note 1: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX devices. Itis not intended to be a comprehensivereference source. T o complement theinformation in this data sheet, refer toSection 24. “Programming and Diag-nostics” (DS70207) and Section 25.“Device Configuration” (DS70194) inthe “dsPIC33F/PIC24H Family Refer-ence Manual”, which are available fromthe Microchip web site(www.microchip.com).


Note: Configuration data is reloaded on all typesof device Resets.

Note: Performing a page erase operation on thelast page of program memory clears theFlash Configuration Words, enabling codeprotection as a result. Therefore, usersshould avoid performing p age eraseoperations on the l ast page of progra mmemory.

TABLE 15-1: CONFIGURATION SHADOW REGISTER MAPAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

F80004 FGS — — — — — — GCP GWRPF80006 FOSCSEL IESO PWMLOCK(1) — WDTWIN<1:0> FNOSC<2:0>F80008 FOSC FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0>F8000A FWDT FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>F8000C FPOR PWMPIN(1) HPOL(1) LPOL(1) ALTI2C1 — — — —F8000E FICD Reserved(2) — JTAGEN(3) — — — ICS<1:0>Legend: — = unimplemented, read as ‘1’.Note 1: These bits are only available on dsPIC33FJ16MC101/102 devices.

2: This bit is reserved for use by development tools.3: This bit is not available on the dsPIC33FJ16MC101 device.


dsPIC33FJXXXG

SXXX

DS

00000A-page 176

Data Sheet M

ock-up


5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FNC IOL1WAY LPOL(2) ALTI2C1 POSCMD<1:0>

EN WDTPRE WDTPOST<3:0>

The Configuration Flash Words map is shown in Table 15-2.

TABLE 15-2: CONFIGURATION FLASH WORDS File

Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit

CONFIG2 002BFC — IESO PWMLOCK(2) PWMPIN(2) WDTWIN<1:0> FNOSC<2:0> FCKSM<1:0> OSCIO

CONFIG1 002BFE — Reserved(3) JTAGEN(5) GCP GWRP Reserved(4) HPOL(2) ICS<1:0> FWDTEN WINDIS PLLK

Legend: — = unimplemented, read as ‘1’.Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.

2: This bit is reserved on dsPIC33FJ16GP101/102 devices and reads as ‘1’.3: This bit is reserved; program as ‘0’.4: This bit is reserved for use by development tools and must be programmed as ‘1’.5: This bit is not available on the dsPIC33FJ16MC101 device.

dsPIC33FJXXXGSXXX

TABLE 15-3: dsPIC33F CONFIGURATION BITS DESCRIPTIONBit Field RTSP Effect Description

GCP Immediate General Segment Code-Protect bit1 = User program memory is not code-protected0 = Code protection is enabled for the entire program memory space

GWRP Immediate General Segment Write-Protect bit1 = User program memory is not write-protected0 = User program memory is write-protected

IESO Immediate Two-speed Oscillator Start-up Enable bit1 = Start-up device with FRC, then automatically switch to the

user-selected oscillator source when ready0 = Start-up device with user-selected oscillator source

PWMLOCK Immediate PWM Lock Enable bit1 = Certain PWM registers may only be written after key sequence0 = PWM registers may be written without key

WDTWIN<1:0> Immediate Watchdog Window Select bits11 = WDT Window is 24% of WDT period10 = WDT Window is 37.5% of WDT period01 = WDT Window is 50% of WDT period00 = WDT Window is 75% of WDT period

FNOSC<2:0> If clock switch is enabled, RTSP effect is on any device Reset;

otherwise, Immediate

Oscillator Selection bits111 = Fast RC Oscillator with divide-by-N (FRCDIVN)110 = Reserved; do not use101 = Low-Power RC Oscillator (LPRC)100 = Secondary Oscillator (Sosc)011 = Primary Oscillator with PLL module (MS + PLL, EC + PLL)010 = Primary Oscillator (MS, HS, EC)001 = Fast RC Oscillator with divide-by-N with PLL module

(FRCDIVN + PLL)000 = Fast RC Oscillator (FRC)

FCKSM<1:0> Immediate Clock Switching Mode bits1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

IOL1WAY Immediate Peripheral pin select configuration1 = Allow only one reconfiguration0 = Allow multiple reconfigurations

OSCIOFNC Immediate OSC2 Pin Function bit (except in MS and HS modes)1 = OSC2 is clock output0 = OSC2 is general purpose digital I/O pin

POSCMD<1:0> Immediate Primary Oscillator Mode Select bits11 = Primary oscillator disabled10 = HS Crystal Oscillator mode (10 MHz - 32 MHz)01 = MS Crystal Oscillator mode (3 MHz - 10 MHz)00 = EC (External Clock) mode (DC - 32 MHz)

FWDTEN Immediate Watchdog Timer Enable bit1 = Watchdog Timer always enabled (LPRC oscillator cann ot be disabled.

Clearing the SWDTEN bit in the RCON register will have no effect.)0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled

by clearing the SWDTEN bit in the RCON register)WINDIS Immediate Watchdog Timer Window Enable bit

1 = Watchdog Timer in Non-Window mode0 = Watchdog Timer in Window mode

WDTPRE Immediate Watchdog Timer Prescaler bit1 = 1:1280 = 1:32


dsPIC33FJXXXGSXXX

WDTPOST<3:0> Immediate Watchdog Timer Postscaler bits1111 = 1:32,7681110 = 1:16,384•••0001 = 1:20000 = 1:1

PLLKEN Immediate PLL Lock Enable bit1 = PLL lock enabled0 = PLL lock disabled

ALTI2C Immediate Alternate I2C™ pins1 = I2C mapped to SDA1/SCL1 pins0 = I2C mapped to ASDA1/ASCL1 pins

JTAGEN Immediate JTAG Enable bit 1 = JTAG enabled0 = JTAG disabled

ICS<1:0> Immediate ICD Communication Channel Select bits11 = Communicate on PGEC1 and PGED110 = Communicate on PGEC2 and PGED201 = Communicate on PGEC3 and PGED300 = Reserved, do not use

PWMPIN Immediate Motor Control PWM Module Pin Mode bit1 = PWM module pins controlled by PORT register at device Reset

(tri-stated)0 = PWM module pins controlled by PWM module at device Reset

(configured as output pins)HPOL Immediate Motor Control PWM High Side Polarity bit

1 = PWM module high side output pins have active-high output polarity0 = PWM module high side output pins have active-low output polarity

LPOL Immediate Motor Control PWM Low Side Polarity bit1 = PWM module low side output pins have active-high output polarity0 = PWM module low side output pins have active-low output polarity

TABLE 15-3: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field RTSP Effect Description


dsPIC33FJXXXGSXXX

REGISTER 15-1: DEVID: DEVICE ID REGISTER

R R R R R R R RDEVID<23:16>

bit 23 bit 16


bit 15 bit 8


bit 7 bit 0

Legend: R = Read-Only bit U = Unimplemented bit

bit 23-0 DEIDV<23:0>: Device Identifier bits(1)

Note 1: Refer to the “Flash Programming Specification for dsPIC33F Families with Volatile Configuration Bits” for the list of device ID values.

REGISTER 15-2: DEVREV: DEVICE REVISION REGISTER

R R R R R R R RDEVREV<23:16>

bit 23 bit 16


bit 15 bit 8


bit 7 bit 0

Legend: R = Read-only bit U = Unimplemented bit

bit 23-0 DEVREV<23:0>: Device Revision bits(1)

Note 1: Refer to the “Flash Programming Specification for dsPIC33F Families with Volatile Configuration Bits” for the list of device revision values.


dsPIC33FJXXXGSXXX

15.2 On-Chip Voltage RegulatorAll of the dsPIC33FJXX XGSXXX devices power theircore digital logic at a no minal 2.5V. This can create aconflict for de signs that are required to operate at ahigher typical voltage, such as 3.3V. To simplify systemdesign, all devices in the dsPIC33FJXXXGSXXX fam-ily incorporate an on-chip regulator that all ows thedevice to run its core logic from VDD.

The regulator provides power to the core from the otherVDD pins. When the regulator is enabled, a low-ESR(less than 5 ohms) capacitor (such as tantalum orceramic) must be connected to the V CAP pin(Figure 15-1). This helps to maintain the stability of theregulator. The recommended value for the filter capac-itor is provided in Table 18-14 located in Section 18.1“DC Characteristics”.

On a POR, it takes approximately 20 s for the on-chipvoltage regulator to generate an output voltage. Duringthis time, designated as TSTARTUP, code execution isdisabled. TSTARTUP is applied every ti me the deviceresumes operation after any power-down.

FIGURE 15-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1)

15.3 BOR: Brown-Out ResetThe Brown-out Reset (BOR) modu le is ba sed on aninternal voltage reference circuit that monitors the reg-ulated supply voltage VCAP. The main purpose of theBOR module is to generate a devi ce Reset whe n abrown-out condition occurs. Brown-out conditions aregenerally caused by glitches on the AC mains (forexample, missing portions of the AC cycle waveformdue to bad power transmission lines, or voltage sagsdue to excessive current draw when a large inductiveload is turned on).

A BOR ge nerates a Re set pulse, which rese ts thedevice. The BOR selects the clock source, based onthe device Configuration bit values (FNOSC<2:0> andPOSCMD<1:0>).

If an oscillator mode is selected, the BOR activates theOscillator Start-up Timer (OST). The system clock isheld until OST expires. If the PLL is used, the clock isheld until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the PWRT time-out (TPWRT) is appliedbefore the internal Reset is released. If TPWRT = 0 anda crystal oscillator is being used, then a nominal delayof TFSCM = 100 is applied. The total delay in this caseis TFSCM.

The BOR Status bit (RCON<1>) is set to indicate that aBOR has occurred. The BOR circuit continues to oper-ate while in Sleep or Idle modes and resets the deviceshould VDD fall below the BOR threshold voltage.

Note: It is impo rtant for low-ESR cap acitors tobe placed as close as possible to the VCAPpin.

Note 1: These are typical operating voltages. Refer to Table 18-14 located in Section 18.1 “DC Characteristics” for the full operating ranges of VDD and VCAP.

2: It is important for low-ESR capacitors to be placed as close as possible to the VCAP pin.

VDD

VCAP

VSS

dsPIC33F

CEFC

3.3V

10 µFTantalum


dsPIC33FJXXXGSXXX

15.4 Watchdog Timer (WDT)For dsPIC33FJXXXGSXXX devices, the WDT is drivenby the LPRC oscillator. When the WDT is enabled, theclock source is also enabled.

15.4.1 PRESCALER/POSTSCALERThe nominal WDT clock source from LPRC is 32 kHz.This feeds a prescaler than can be configured for either5-bit (divide-by-32) or 7-b it (divide-by-128) operation.The prescaler is set by the WDTPRE Configuration bit.With a 32 kHz input, the prescaler yields a nominalWDT time-out period (TWDT) of 1 ms in 5-bit mode, or4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaleroutput and allows for a wide range of time-out periods.The postscaler is controlled by the WDTPOST<3:0>Configuration bits (FWDT<3:0>), which allow the selec-tion of 16 settings, from 1:1 to 1:32,768. Using the pres-caler and postscaler, time-out periods ranging from1 ms to 131 seconds can be achieved.

The WDT, prescaler, and postscaler are reset:

• On any device Reset• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to resume normal operation

• By a CLRWDT instruction during normal execution

15.4.2 SLEEP AND IDLE MODESIf the WDT is enabled, it will continue to run during Sleepor Idle modes. When the WDT time-out occurs, thedevice will wake the device and code execution willcontinue from where the PWRSAV instruction wasexecuted. The correspond ing SLEEP or IDLE bit s(RCON<3> and RCON<2>, respectively) will need to becleared in software after the device wakes up.

15.4.3 ENABLING WDTThe WDT is enabled or di sabled by the FWDTENConfiguration bit in the FWDT Configuration register.When the FWDTEN Configuration bit is set, the WDT isalways enabled.

The WDT can be optionally controlled in software whenthe FWDTEN Configuration bit has been programmedto ‘0’. The WDT is enabled in software by setting theSWDTEN control bit (RCON<5>). The SWDTEN con-trol bit is clea red on any device Reset. The softwareWDT option allows the user application to enable theWDT for critical code segments and disable the WDTduring non-critical segments for maximum power savings.

The WDT flag bit, WDTO (RCON<4>), is not automaticallycleared following a WDT time-out. To detect subsequentWDT events, the flag must be cleared in software.

FIGURE 15-2: WDT BLOCK DIAGRAM

Note: The CLRWDT and PWRSAV instructionsclear the prescaler and postscaler countswhen executed.

Note: If the WI NDIS bit (F WDT<6>) is cleared,the CLRWDT instruction should be executedby the application software only during thelast 1/4 of the WDT period. This CLRWDTwindow can be determined by using a timer.If a CLRWDT instruction is executed beforethis window, a WDT Reset occurs.

All Device ResetsTransition to New Clock SourceExit Sleep or Idle ModePWRSAV InstructionCLRWDT Instruction

0

1

WDTPRE WDTPOST<3:0>

Watchdog Timer

Prescaler(divide by N1)

Postscaler(divide by N2)

Sleep/Idle

WDT

WDT Window SelectWINDIS

WDT

CLRWDT Instruction

SWDTENFWDTEN

LPRC Clock

RS RS

Wake-up

Reset


dsPIC33FJXXXGSXXX

15.5 JTAG InterfacedsPIC33FJ16GP101/102 and dsPIC33FJ16MC102devices implement a JTAG interface, which supportsboundary scan device testing. Detailed information onthis interface will be provided in future revisions of thedocument.

15.6 In-Circuit Serial ProgrammingThe dsPIC33FJXXXGSXXX devices can be seriallyprogrammed while in the end application circuit. This isdone with two lines for clock and data and three otherlines for power, ground and the programmingsequence. Serial programming allows customers tomanufacture boards with unprogrammed devices andthen program the digital signal controller just beforeshipping the product. Serial programming also allowsthe most recent firmware or a custom firmware to beprogrammed. Refer to the “Flash ProgrammingSpecification for dsPIC33F Families with VolatileConfiguration Bits” for det ails about In-Circuit SerialProgramming (ICSP).

Any of the three pairs of programming clock/data pinscan be used:

• PGEC1 and PGED1• PGEC2 and PGED2• PGEC3 and PGED3

15.7 In-Circuit DebuggerWhen MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This functionallows simple debugging functions when used withMPLAB IDE. D ebugging functionality is controlledthrough the PGECx (Emulation/Debug Clock) andPGEDx (Emulation/Debug Data) pin functions.

Any of the three pairs of debugging clock/data pins canbe used:

• PGEC1 and PGED1• PGEC2 and PGED2• PGEC3 and PGED3

To use the in-circu it debugger function of the device,the design must imple ment ICSP connections toMCLR, VDD, VSS, and the PGECx/PGEDx pin pair. Inaddition, when the feature is enabled, some of theresources are no t available for ge neral use. Th eseresources include the first 80 bytes of data RAM andtwo I/O pins.


dsPIC33FJXXXGSXXX

16.0 INSTRUCTION SET SUMMARY

The dsPIC33F instruction set is identical to that of thedsPIC30F.

Most instructions are a single program memory word(24 bits). Only three instructions require two programmemory locations.

Each single-word instruction is a 24-bit word, dividedinto an 8-bit opcode, which specifies the i nstructiontype and one or more operands, which further specifythe operation of the instruction.

The instruction set is highly orthogonal and is groupedinto five basic categories:

• Word or byte-oriented operations• Bit-oriented operations• Literal operations• DSP operations• Control operations

Table 16-1 shows the gen eral symbols used indescribing the instructions.

The dsPIC33F instruction set summary in Table 16-2lists all the instructions, alo ng with the status flagsaffected by each instruction.

Most word or byte-oriente d W register instructions(including barrel shift instructions) have threeoperands:

• The first source operand, which is typically a register ‘Wb’ without any address modifier

• The second source operand, which is typically a register ‘Ws’ with or without an address modifier

• The destination of the result, which is typically a register ‘Wd’ with or without an address modifier

However, word or byte-oriented file register instructionshave two operands:

• The file register specified by the value ‘f’• The destination, which could be either the file

register ‘f’ or the W0 register, which is denoted as ‘WREG’

Most bit-oriented instructions (including simple rotate/shift instructions) have two operands:

• The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’)

• The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’)

The literal instructions that involve data movement canuse some of the following operands:

• A literal value to be loaded into a W register or file register (specified by ‘k’)

• The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic orlogical operations use some of the following operands:

• The first source operand, which is a register ‘Wb’ without any address modifier

• The second source operand, which is a literal value

• The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier

The MAC class of DSP instructions can use some of thefollowing operands:

• The accumulator (A or B) to be used (required operand)

• The W registers to be used as the two operands• The X and Y address space prefetch operations• The X and Y address space prefetch destinations• The accumulator write back destination

The other DSP instruction s do not invol ve anymultiplication and can include:

• The accumulator to be used (required)• The source or destination operand (designated as

Wso or Wdo, respectively) with or without an address modifier

• The amount of shift specified by a W register ‘Wn’ or a literal value

The control instructions can use some of the followingoperands:

• A program memory address • The mode of the table read and table write

instructions

Note: This data sheet summarizes the featuresof the dsPIC33FJXXXGSXXX devices.However, it is not intended to be acomprehensive reference source. Tocomplement the information in this dat asheet, refer to the latest family referencesections of the “dsPIC33F/PIC24H FamilyReference Manual”, which are availablefrom the Microchi p website(www.microchip.com).


dsPIC33FJXXXGSXXX

Most instructions are a single word. Certain double-word instructions are desig ned to provide all therequired information in these 48 bits. In the secondword, the 8 MSbs are ‘0’s. If this second word is exe-cuted as an instruction (by itself), it will execute as aNOP.

The double-word instructions execute in two instructioncycles.

Most single-word instructions are executed in a singleinstruction cycle, unless a conditional test is true, or theprogram counter is cha nged as a result of the in struc-tion. In these cases, the execution takes two instructioncycles with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-tional/computed branch), indirect CALL/GOTO, all tablereads and writes and RETURN/RETFIE instructions,which are single-word instructions but take two or threecycles. Certain instructions that involve skipping over thesubsequent instruction require either two or three cyclesif the skip is performed, depending on w hether theinstruction being skipped is a single-word or two-wordinstruction. Moreover, double-word moves requ ire twocycles.

Note: For more details on the instruction set,refer to the “16-bit MCU and DSC Pro-grammer’s Reference Manual (DS70157).

TABLE 16-1: SYMBOLS USED IN OPCODE DESCRIPTIONSField Description

#text Means literal defined by “text”(text) Means “content of text”[text] Means “the location addressed by text”{ } Optional field or operation<n:m> Register bit field.b Byte mode selection.d Double-Word mode selection.S Shadow register select.w Word mode selection (default)Acc One of two accumulators {A, B}AWB Accumulator write back destination address register {W13, [W13]+ = 2}bit4 4-bit bit selection field (used in word addressed instructions) {0...15}C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky ZeroExpr Absolute address, label or expression (resolved by the linker)f File register address {0x0000...0x1FFF}lit1 1-bit unsigned literal {0,1}lit4 4-bit unsigned literal {0...15}lit5 5-bit unsigned literal {0...31}lit8 8-bit unsigned literal {0...255}lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word modelit14 14-bit unsigned literal {0...16384}lit16 16-bit unsigned literal {0...65535}lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’None Field does not require an entry, can be blankOA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB SaturatePC Program CounterSlit10 10-bit signed literal {-512...511}Slit16 16-bit signed literal {-32768...32767}Slit6 6-bit signed literal {-16...16}Wb Base W register {W0..W15}Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }Wdo Destination W register

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing)


dsPIC33FJXXXGSXXX

Wm*Wm Multiplicand and Multiplier working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7}

Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}

Wn One of 16 working registers {W0..W15}Wnd One of 16 destination working registers {W0..W15}Wns One of 16 source working registers {W0..W15}WREG W0 (working register used in file register instructions)Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }Wso Source W register

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X data space prefetch address register for DSP instructions

{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none}

Wxd X data space prefetch destination register for DSP instructions {W4..W7}Wy Y data space prefetch address register for DSP instructions

{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none}

Wyd Y data space prefetch destination register for DSP instructions {W4..W7}

TABLE 16-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)Field Description


dsPIC33FJXXXGSXXX

TABLE 16-2: INSTRUCTION SET OVERVIEW BaseInstr

#AssemblyMnemonic Assembly Syntax Description # of

Words# of

CyclesStatus Flags

Affected

1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB

ADD f f = f + WREG 1 1 C,DC,N,OV,Z

ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z

ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z

ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z

ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z

ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB

2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z

3 AND AND f f = f .AND. WREG 1 1 N,Z

AND f,WREG WREG = f .AND. WREG 1 1 N,Z

AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z

AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z

AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z

4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z

ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z

ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z

5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None

BCLR Ws,#bit4 Bit Clear Ws 1 1 None

6 BRA BRA C,Expr Branch if Carry 1 1 (2) None

BRA GE,Expr Branch if greater than or equal 1 1 (2) None

BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None

BRA GT,Expr Branch if greater than 1 1 (2) None

BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None

BRA LE,Expr Branch if less than or equal 1 1 (2) None

BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None

BRA LT,Expr Branch if less than 1 1 (2) None

BRA LTU,Expr Branch if unsigned less than 1 1 (2) None

BRA N,Expr Branch if Negative 1 1 (2) None

BRA NC,Expr Branch if Not Carry 1 1 (2) None

BRA NN,Expr Branch if Not Negative 1 1 (2) None

BRA NOV,Expr Branch if Not Overflow 1 1 (2) None

BRA NZ,Expr Branch if Not Zero 1 1 (2) None

BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None

BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None

BRA OV,Expr Branch if Overflow 1 1 (2) None

BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None

BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None

BRA Expr Branch Unconditionally 1 2 None

BRA Z,Expr Branch if Zero 1 1 (2) None

BRA Wn Computed Branch 1 2 None

7 BSET BSET f,#bit4 Bit Set f 1 1 None

BSET Ws,#bit4 Bit Set Ws 1 1 None

8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None

9 BTG BTG f,#bit4 Bit Toggle f 1 1 None

BTG Ws,#bit4 Bit Toggle Ws 1 1 None


dsPIC33FJXXXGSXXX

10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3)

None

BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3)

None

11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3)

None

BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3)

None

12 BTST BTST f,#bit4 Bit Test f 1 1 Z

BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C

BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z

BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C

BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z

13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z

BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C

BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z

14 CALL CALL lit23 Call subroutine 2 2 None

CALL Wn Call indirect subroutine 1 2 None

15 CLR CLR f f = 0x0000 1 1 None

CLR WREG WREG = 0x0000 1 1 None

CLR Ws Ws = 0x0000 1 1 None

CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB

16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep

17 COM COM f f = f 1 1 N,Z

COM f,WREG WREG = f 1 1 N,Z

COM Ws,Wd Wd = Ws 1 1 N,Z

18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z

CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z

CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z

19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z

CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z

20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb – Ws – C)

1 1 C,DC,N,OV,Z

21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 (2 or 3)

None

22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 (2 or 3)

None

23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 (2 or 3)

None

24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if 1 1 (2 or 3)

None

25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C

26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z

DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z

DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z

27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z

DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z

DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z

28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None

TABLE 16-2: INSTRUCTION SET OVERVIEW (CONTINUED) BaseInstr


Words# of

CyclesStatus Flags

Affected


dsPIC33FJXXXGSXXX

29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV

30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV

31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None

DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None

32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,SA,SB,SAB

33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,SA,SB,SAB

34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None

35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C

36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C

37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C

38 GOTO GOTO Expr Go to address 2 2 None

GOTO Wn Go to indirect 1 2 None

39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z

INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z

INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z

INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z

41 IOR IOR f f = f .IOR. WREG 1 1 N,Z

IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z

IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z

IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z

IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z

42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,SA,SB,SAB

43 LNK LNK #lit14 Link Frame Pointer 1 1 None

44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z

LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z

LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z

LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z

LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z

45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB

Multiply and Accumulate 1 1 OA,OB,OAB,SA,SB,SAB

MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,SA,SB,SAB

46 MOV MOV f,Wn Move f to Wn 1 1 None

MOV f Move f to f 1 1 N,Z

MOV f,WREG Move f to WREG 1 1 None

MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None

MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None

MOV Wn,f Move Wn to f 1 1 None

MOV Wso,Wdo Move Ws to Wd 1 1 None

MOV WREG,f Move WREG to f 1 1 None

MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None

MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None

47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None



Words# of

CyclesStatus Flags

Affected


dsPIC33FJXXXGSXXX

48 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,SA,SB,SAB

MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd

Square Wm to Accumulator 1 1 OA,OB,OAB,SA,SB,SAB

49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

-(Multiply Wm by Wn) to Accumulator 1 1 None

50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB

Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,SA,SB,SAB

51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None

MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None

MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None

MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws)

1 1 None

MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None

MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5)

1 1 None

MUL f W3:W2 = f * WREG 1 1 None

52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,SA,SB,SAB

NEG f f = f + 1 1 1 C,DC,N,OV,Z

NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

53 NOP NOP No Operation 1 1 None

NOPR No Operation 1 1 None

54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None

POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None

POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1)

1 2 None

POP.S Pop Shadow Registers 1 1 All

55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None

PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None

PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None

PUSH.S Push Shadow Registers 1 1 None

56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep

57 RCALL RCALL Expr Relative Call 1 2 None

RCALL Wn Computed Call 1 2 None

58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None

REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None

59 RESET RESET Software device Reset 1 1 None

60 RETFIE RETFIE Return from interrupt 1 3 (2) None

61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None

62 RETURN RETURN Return from Subroutine 1 3 (2) None

63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z

RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z

RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z

64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z

RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z

RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z

65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z

RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z

RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z



Words# of

CyclesStatus Flags

Affected


dsPIC33FJXXXGSXXX

66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z

RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z

RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z

67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None

SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None

68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z

69 SETM SETM f f = 0xFFFF 1 1 None

SETM WREG WREG = 0xFFFF 1 1 None

SETM Ws Ws = 0xFFFF 1 1 None

70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,SA,SB,SAB

SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,SA,SB,SAB

71 SL SL f f = Left Shift f 1 1 C,N,OV,Z

SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z

SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z

SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z

SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z

72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,SA,SB,SAB

SUB f f = f – WREG 1 1 C,DC,N,OV,Z

SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z

SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z

SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z

SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z

73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z

SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z

SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z

SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z

SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z

74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z

SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z

SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z

SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z

75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z

SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z

76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None

SWAP Wn Wn = byte swap Wn 1 1 None

77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None

78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None

79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None

80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None

81 ULNK ULNK Unlink Frame Pointer 1 1 None

82 XOR XOR f f = f .XOR. WREG 1 1 N,Z

XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z

XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z

XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z

XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z

83 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N



Words# of

CyclesStatus Flags

Affected


dsPIC33FJXXXGSXXX

17.0 DEVELOPMENT SUPPORTThe PIC® microcontrollers and dsPIC® digital signalcontrollers are supported with a full range of softwareand hardware development tools:

• Integrated Development Environment- MPLAB® IDE Software

• Compilers/Assemblers/Linkers- MPLAB C Compiler for Various Device

Families- HI-TECH C for Various Device Families- MPASMTM Assembler- MPLINKTM Object Linker/

MPLIBTM Object Librarian- MPLAB Assembler/Linker/Librarian for

Various Device Families• Simulators

- MPLAB SIM Software Simulator• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator• In-Circuit Debuggers

- MPLAB ICD 3- PICkit™ 3 Debug Express

• Device Programmers- PICkit™ 2 Programmer- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits

17.1 MPLAB Integrated Development Environment Software

The MPLAB IDE sof tware brings an ease of softwaredevelopment previously unseen in the 8 /16/32-bitmicrocontroller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools- Simulator- Programmer (sold separately)- In-Circuit Emulator (sold separately)- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context• A multiple project manager• Customizable data windows with direct edit of

contents• High-level source code debugging• Mouse over variable inspection• Drag and drop variables from source to watch

windows• Extensive on-line help• Integration of select third party tools, such as

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)• One-touch compile or assemble, and download to

emulator and simulator tools (automatically updates all project information)

• Debug using:- Source files (C or assembly)- Mixed C and assembly- Machine code

MPLAB IDE supports multiple debugging tools in asingle development paradigm, from the co st-effectivesimulators, through low-cost in-circuit debuggers, tofull-featured emulators. This eliminates the learningcurve when upgrading to tools with increased flexibilityand power.


dsPIC33FJXXXGSXXX

17.2 MPLAB C Compilers for Various Device Families

The MPLAB C Compiler code development systemsare complete ANSI C compilers for Microchip’s PIC18,PIC24 and PIC32 families of microcontrollers and thedsPIC30 and dsPIC33 families of digital signal control-lers. These compilers provide powerful integrationcapabilities, superior code optimization and ease ofuse.

For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.

17.3 HI-TECH C for Various Device Families

The HI-TECH C Compiler code development systemsare complete ANSI C compilers for Microchip’s PICfamily of microcontrollers and the dsPIC family of digitalsignal controllers. These compilers provide powerfulintegration capabilities, omniscient code generationand ease of use.

For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.

The compilers include a macro assembler, linker, pre-processor, and one-step driver, and can run on multipleplatforms.

17.4 MPASM AssemblerThe MPASM Assembler is a full -featured, universalmacro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable objectfiles for the MPLINK Object Linker, Intel® standard HEXfiles, MAP file s to d etail memory usage and symbolreference, absolute LST files that contain source linesand generated machine code and COFF files fordebugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects• User-defined macros to streamline

assembly code• Conditional assembly for multi-purpose

source files• Directives that allow complete control over the

assembly process

17.5 MPLINK Object Linker/MPLIB Object Librarian

The MPLINK Object Linker combines relocatableobjects created by the MPASM Assembler and theMPLAB C18 C Compiler. It can link relocatable objectsfrom precompiled libraries, using directives from alinker script.

The MPLIB Object Librarian manages the creation andmodification of library files of precompiled code. Whena routine from a library is called from a source file, onlythe modules that contain that routine will be linked inwith the application. This allows large libraries to beused efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many smaller files

• Enhanced code maintainability by grouping related modules together

• Flexible creation of libraries with easy module listing, replacement, deletion and extraction

17.6 MPLAB Assembler, Linker and Librarian for Various Device Families

MPLAB Assembler pr oduces relocatable machinecode from symb olic assembly language for PIC24,PIC32 and dsPIC devices. MPLAB C Compiler usesthe assembler to produce its object file. The assemblergenerates relocatable object files that can then bearchived or linked with other relocatable object files andarchives to create an executable file. Notable featuresof the assembler include:

• Support for the entire device instruction set• Support for fixed-point and floating-point data• Command line interface• Rich directive set• Flexible macro language• MPLAB IDE compatibility


dsPIC33FJXXXGSXXX

17.7 MPLAB SIM Software SimulatorThe MPLAB S IM Software Simulator allows codedevelopment in a PC-hosted environment by simulat-ing the PIC MCUs and dsPIC® DSCs on an instructionlevel. On any given instruction, the data areas can beexamined or modified and stimuli can be applied froma comprehensive stimulus controller. Registers can belogged to files for further run-time analysis. The tracebuffer and logic analyzer display extend the power ofthe simulator to record and track program execution,actions on I/O, most peripherals and internal registers.

The MPLAB SIM Sof tware Simulator fully supportssymbolic debugging using the MPLAB C Compilers,and the MPASM and MPLAB Assemble rs. The soft-ware simulator offers the flexibility to develop anddebug code outside of the hardware laboratory envi-ronment, making it an excellent, economical softwaredevelopment tool.

17.8 MPLAB REAL ICE In-Circuit Emulator System

MPLAB REAL ICE In-Circuit Emulator System isMicrochip’s next gene ration high-speed emulator forMicrochip Flash DSC and MCU devices. It debugs andprograms PIC® Flash MCUs and dsPIC® Flash DSCswith the easy-to-use, powerful graphical user interface ofthe MPLAB Integrated Development Environment (IDE),included with each kit.

The emulator is connected to the design engineer’s PCusing a high-speed USB 2.0 interface and is connectedto the target with either a connector compatible with in-circuit debugger systems (RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal(LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmwaredownloads in MPLAB ID E. In upcoming releases ofMPLAB IDE, new devices will be supported, and newfeatures will be added. MPLAB R EAL ICE of ferssignificant advantages over competitive emul atorsincluding low-cost, full-speed emulation, run-timevariable watches, trace analysis, complex breakpoints, aruggedized probe interface and long (up to three meters)interconnection cables.

17.9 MPLAB ICD 3 In-Circuit Debugger System

MPLAB ICD 3 In-Circuit Debugger System is Micro-chip's most cost ef fective high-speed hardwaredebugger/programmer for Microchip Flash Digital Sig-nal Controller (DSC) and microcontroller (MCU)devices. It debugs and programs PIC® Flash microcon-trollers and dsPIC® DSCs with the powerful, yet easy-to-use graphical user interface of MPLAB IntegratedDevelopment Environment (IDE).

The MPLAB ICD 3 In-Circuit Debu gger probe is con-nected to the design engineer's PC using a high-speedUSB 2.0 interface and is connected to the target with aconnector compatible with the MPLAB ICD 2 or MPLABREAL ICE systems (RJ-11). MPLAB ICD 3 supports allMPLAB ICD 2 headers.

17.10 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-ming of PIC® and dsPIC® Flash microcontrollers at amost affordable price point using the powerful graphicaluser interface of the MP LAB Integrated DevelopmentEnvironment (IDE). The MPLAB PICkit 3 is connectedto the design engineer's PC using a full speed USBinterface and can be connected to the target via anMicrochip debug (RJ-11) connector (compatible withMPLAB ICD 3 and MPLAB REAL ICE). The connectoruses two device I/O pins and the reset line to imple-ment in-circuit debu gging and In-Circuit Serial Pro-gramming™.

The PICkit 3 Debug Express include the PICkit 3, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software.


dsPIC33FJXXXGSXXX

17.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger isa low-cost development tool with an easy to use inter-face for programming and debugging Microchip’s Flashfamilies of microcontrollers. The full fea turedWindows® programming interface supports baseline(PIC10F, PIC12F5xx, PIC16F5xx), midrange(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bitmicrocontrollers, and many Microchip Serial EEPROMproducts. With Microchip’s powerful MPLAB IntegratedDevelopment Environment (IDE) the PICkit™ 2enables in-circuit debugging on most PIC® microcon-trollers. In-Circuit-Debugging runs, halts and singlesteps the program while the PIC microcontroller isembedded in the application. When halted at a break-point, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software.

17.12 MPLAB PM3 Device ProgrammerThe MPLAB PM3 Device Programmer is a un iversal,CE compliant device programmer with programmablevoltage verification at V DDMIN and VDDMAX formaximum reliability. It features a l arge LCD display(128 x 64) for menus and error messages and a modu-lar, detachable socket asse mbly to supp ort variouspackage types. The ICSP™ cable assembly is includedas a standard item. In Stand-Alone mode, the MPLABPM3 Device Programmer can read, verify and programPIC devices without a PC connection. It can also setcode protection in this mod e. The MPLAB PM3connects to the host PC via an RS-232 or USB cable.The MPLAB PM3 has high-speed communications andoptimized algorithms for q uick programming of largememory devices and incorporates an MMC card for filestorage and data applications.

17.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

A wide variety of demonstration, development andevaluation boards fo r various PIC MCUs and dsPICDSCs allows quick application development on fully func-tional systems. Most boards include prototyping areas foradding custom circuitry and provide application firmwareand source code for examination and modification.

The boards support a variety of features, including LEDs,temperature sensors, switches, speakers, RS-232interfaces, LCD displays, potentiometers and additionalEEPROM memory.

The demonstration and development boards can beused in teaching environments, for prototyping customcircuits and for learning about various microcontrollerapplications.

In addition to the PICDEM™ and dsPICDEM™ demon-stration/development board series of circuits, Microchiphas a line of evaluation kits and demonstration softwarefor analog filter design, KEELOQ® security ICs, CAN,IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow ratesensing, plus many more.

Also available are starter kits that con tain everythingneeded to experience the specified device. This usuallyincludes a single application and debug capability, allon one board.

Check the Microchip web page (www.microchip.com)for the complete list of demonstration, developmentand evaluation kits.



dsPIC33FJXXXGSXXX

18.0 ELECTRICAL CHARACTERISTICSThis section provides an overview of dsPIC33FJXXXGSXXX electrical characteristics. Additional information will be pro-vided in future revisions of this document as it becomes available.

Absolute maximum ratings for the dsPIC33FJXXXGSXXX family are listed below. Exposure to these maximum ratingconditions for extended periods may affect device reliability. Functional operation of the device at these or any otherconditions above the parameters indicated in the operation listings of this specification is not implied.

Absolute Maximum Ratings(1) Ambient temperature under bias............................................................................................................ .-40°C to +125°CStorage temperature .............................................................................................................................. -65°C to +150°CVoltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0VVoltage on any pin that is not 5V tolerant with respect to VSS(4) .................................................... -0.3V to (VDD + 0.3V)Voltage on any 5V tolerant pin with respect to VSS when VDD 2.4V(4) .................................................. -0.3V to +5.6VVoltage on any 5V tolerant pin with respect to VSS when VDD 2.4V(4) .................................................... -0.3V to 3.6VVoltage on VCAP with respect to VSS ...................................................................................................... 2.25V to 2.75VMaximum current out of VSS pin ...........................................................................................................................300 mAMaximum current into VDD pin(2)...........................................................................................................................250 mAMaximum output current sunk by any I/O pin(3) ........................................................................................................8 mAMaximum output current sourced by any I/O pin(3)...................................................................................................8 mAMaximum current sunk by all ports .......................................................................................................................200 mAMaximum current sourced by all ports(2)...............................................................................................................200 mA

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only, and functional operation of the device at those or any other conditionsabove those indicated in the operation listings of this specification is not implied. Exposure to maximumrating conditions for extended periods may affect device reliability.

2: Maximum allowable current is a function of device maximum power dissipation (see Table 18-2).

3: Exception is the OSCO pin, which is able to source 12 mA and sink 10 mA.

4: See the “Pin Diagrams” section for 5V tolerant pins.


dsPIC33FJXXXGSXXX

18.1 DC Characteristics

TABLE 18-1: OPERATING MIPS VS. VOLTAGE

Characteristic VDD Range(in Volts)

Temp Range(in °C)

Max MIPS

dsPIC33FJXXXGSXXX

DC5VBOR-3.6V -40°C to +85°C 16

VBOR-3.6V -40°C to +125°C 16

TABLE 18-2: THERMAL OPERATING CONDITIONSRating Symbol Min Typ Max Unit

Industrial Temperature DevicesOperating Junction Temperature Range TJ -40 — +125 °COperating Ambient Temperature Range TA -40 — +85 °C

Extended Temperature DevicesOperating Junction Temperature Range TJ -40 — +140 °COperating Ambient Temperature Range TA -40 — +125 °C

Power Dissipation:Internal chip power dissipation:

PINT = VDD x (IDD – IOH) PD PINT + PI/O WI/O Pin Power Dissipation:

I/O = ({VDD – VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W

TABLE 18-3: THERMAL PACKAGING CHARACTERISTICSCharacteristic Symbol Typ Max Unit Notes

Package Thermal Resistance, 18-pin SPDIP JA 50 — °C/W 1Package Thermal Resistance, 20-pin SPDIP JA 50 — °C/W 1Package Thermal Resistance, 28-pin SPDIP JA 50 — °C/W 1Package Thermal Resistance, 18-pin SOIC JA 63 — °C/W 1Package Thermal Resistance, 20-pin SOIC JA 63 — °C/W 1Package Thermal Resistance, 28-pin SOIC JA 55 — °C/W 1Package Thermal Resistance, 20-pin SSOP JA 90 — °C/W 1Package Thermal Resistance, 28-pin SSOP JA 71 — °C/W 1Package Thermal Resistance, 28-pin QFN (6x6 mm) JA 37 — °C/W 1Package Thermal Resistance, 36-pin TLA (5x5 mm) JA 31.1 — °C/W 1Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.


dsPIC33FJXXXGSXXX

TABLE 18-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.4V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial

-40°C TA +125°C for Extended

Param No. Symbol Characteristic Min Typ(1) Max Units Conditions

Operating VoltageDC10 Supply Voltage

VDD — 2.4 — 3.6 V Industrial and ExtendedDC12 VDR RAM Data Retention Voltage(2) 1.8 — — V —DC16 VPOR VDD Start Voltage

to ensure internal Power-on Reset signal

— — VSS V —

DC17 SVDD VDD Rise Rateto ensure internalPower-on Reset signal

0.024 — — V/ms 0-2.4V in 0.1s

DC18 VCORE VDD Core(3) Internal regulator voltage

2.25 — 2.75 V Voltage is dependent on load, temperature and VDD

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.2: This is the limit to which VDD may be lowered without losing RAM data.3: These parameters are characterized by similarity, but are not tested in manufacturing.

TABLE 18-5: ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS



ParamNo. Symbol Characteristic Min(1) Typ Max Units Conditions

BO10 VBOR BOR Event on VDD transition high-to-low. BOR event triggered by VCAP core voltage drop.

2.40 — 2.55 V —

Note 1: Parameters are for design guidance only and are not tested in manufacturing.


dsPIC33FJXXXGSXXX

TABLE 18-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS



Parameter No. Typical(1) Max Units Conditions

Operating Current (IDD)(2)

DC20d 0.7 1.7 mA -40°C

3.3V LPRC (31 kHz)(3)DC20a 0.7 1.7 mA +25°CDC20b 1.0 1.7 mA +85°CDC20c 1.3 1.7 mA +125°CDC21d 1.9 2.6 mA -40°C

3.3V 1 MIPS(3)DC21a 1.9 2.6 mA +25°CDC21b 1.9 2.6 mA +85°CDC21c 2.0 2.6 mA +125°CDC22d 6.5 8.5 mA -40°C


3.3V 10 MIPS(3)DC23a 12.2 15.9 mA +25°CDC23b 12.2 15.9 mA +85°CDC23c 12.2 15.9 mA +125°CDC24d 16 21 mA -40°C

3.3V 16 MIPSDC24a 16 21 mA +25°CDC24b 16 21 mA +85°CDC24c 16 21 mA +125°CNote 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are opera-tional. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits are all zeroed).

3: These parameters are characterized, but not tested in manufacturing.


dsPIC33FJXXXGSXXX

TABLE 18-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS




Idle Current (IIDLE): Core OFF Clock ON Base Current(2)

DC40d 0.6 1.6 mA -40°C

3.3V LPRC (31 kHz)(3)DC40a 0.6 1.6 mA +25°CDC40b 0.9 1.6 mA +85°CDC40c 1.2 1.6 mA +125°CDC41d 0.5 1.1 mA -40°C


3.3V 4 MIPS(3)DC42a 0.9 1.6 mA +25°CDC42b 1.0 1.6 mA +85°CDC42c 1.2 1.6 mA +125°CDC43a 1.6 2.6 mA +25°C

3.3V 10 MIPS(3)2.6DC43d 1.6 mA -40°CDC43b 1.7 2.6 mA +85°CDC43c 2 2.6 mA +125°CDC44d 2.4 3.8 mA -40°C

3.3V 16 MIPS(3)DC44a 2.4 3.8 mA +25°CDC44b 2.6 3.8 mA +85°CDC44c 2.9 3.8 mA +125°CNote 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.

3: These parameters are characterized, but not tested in manufacturing.


dsPIC33FJXXXGSXXX

TABLE 18-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS




Power-Down Current (IPD)(2)

DC60d 27 250 µA -40°C

3.3V Base Power-Down Current(3,4)DC60a 32 250 µA +25°CDC60b 43 250 µA +85°CDC60c 73 500 µA +125°CDC61d 250 — µA -40°C

3.3V Watchdog Timer Current: IWDT(3,5)DC61a 250 — µA +25°CDC61b 250 — µA +85°CDC61c 250 — µA +125°CNote 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off.

3: The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.

4: These currents are measured on the device containing the most memory in this family.5: These parameters are characterized, but not tested in manufacturing.

TABLE 18-9: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)

DC CHARACTERISTICS



Parameter No. Typical(1) Max Doze Ratio(2) Units Conditions

DC73a 13.2 17.2 1:2 mA-40°C 3.3V 16 MIPSDC73f 4.7 6.2 1:64 mA

DC73g 4.7 6.2 1:128 mA

DC70a 13.2 17.2 1:2 mA+25°C 3.3V 16 MIPSDC70f 4.7 6.2 1:64 mA

DC70g 4.7 6.2 1:128 mA


DC71g 4.7 6.2 1:128 mA


DC72g 4.7 6.2 1:128 mANote 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.

2: Parameters with DOZE ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing.


dsPIC33FJXXXGSXXX

TABLE 18-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS



Param No. Symbol Characteristic Min Typ Max Units Conditions

DO10 VOL Output Low VoltageI/O Ports:

4 mA Source/Sink Capability8 mA Source/Sink Capability16 mA Source/Sink Capability

———

———

0.40.40.4

VVV

IOL = 4 mA, VDD = 3.3VIOL = 8 mA, VDD = 3.3VIOL = 16 mA, VDD = 3.3V

DO16 OSC2/CLKO — — 0.4 V IOL = 2 mA, VDD = 3.3VDO20 VOH Output High Voltage

I/O Ports:4 mA Source/Sink Capability8 mA Source/Sink Capability16 mA Source/Sink Capability

2.402.402.40

———

———

VVV

IOH = -4 mA, VDD = 3.3VIOH = -8 mA, VDD = 3.3VIOH = -16 mA, VDD = 3.3V

DO26 OSC2/CLKO 2.41 — — V IOH = -1.3 mA, VDD = 3.3VDO27 ISOURCE Source Current

Pins:RA3, RA4, RB3, RB4, RB11-RB14

Pins:RC3-RC8, RC11-RC13

Pins:RA0-RA2, RB0, RB1, RB5-RB10, RB15, RC1, RC2, RC9, RC10

—

—

—

—

—

—

16

8

4

mA

mA

mA


dsPIC33FJXXXGSXXX

TABLE 18-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS




VIL Input Low VoltageDI10 I/O pins VSS — 0.2 VDD VDI11 PMP pins VSS — 0.15 VDD V PMPTTL = 1

DI15 MCLR VSS — 0.2 VDD VDI16 I/O Pins with OSC1 or SOSCI VSS — 0.2 VDD VDI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMbus disabledDI19 I/O Pins with SDAx, SCLx VSS — 0.8 V V SMbus enabled

VIH Input High VoltageDI20

DI21

I/O Pins Not 5V Tolerant(4)

I/O Pins 5V Tolerant(4)

I/O Pins Not 5V Tolerant with PMP(4)

I/O Pins 5V Tolerant with PMP(4)

0.7 VDD0.7 VDD

0.24 VDD + 0.8

0.24 VDD + 0.8

———

—

VDD5.5VDD

5.5

VVV

V

—

DI28 SDAx, SCLx 0.7 VDD — 5.5 V SMbus disabledDI29 SDAx, SCLx 2.1 — 5.5 V SMbus enabled

ICNPU CNx Pull-up CurrentDI30 50 250 400 A VDD = 3.3V, VPIN = VSS

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current can be measured at different input voltages.3: Negative current is defined as current sourced by the pin.4: See “Pin Diagrams” for the 5V tolerant I/O pins.5: VIL source < (VSS – 0.3). Characterized but not tested.6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not

tested.7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-

vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.


dsPIC33FJXXXGSXXX

IIL Input Leakage Current(2,3)

DI50 I/O pins 5V Tolerant(4) — — ±2 A VSS VPIN VDD,Pin at high-impedance

DI51 I/O Pins Not 5V Tolerant(4) — — ±1 A VSS VPIN VDD, Pin at high-impedance, 40°C TA +85°C

DI51a I/O Pins Not 5V Tolerant(4) — — ±2 A Shared with external reference pins, 40°C TA +85°C

DI51b I/O Pins Not 5V Tolerant(4) — — ±3.5 A VSS VPIN VDD, Pin at high-impedance, -40°C TA +125°C

DI51c I/O Pins Not 5V Tolerant(4) — — ±8 A Analog pins shared with external reference pins, -40°C TA +125°C

DI55 MCLR — — ±2 A VSS VPIN VDD

DI56 OSC1 — — ±2 A VSS VPIN VDD,XT and HS modes


DC CHARACTERISTICS









dsPIC33FJXXXGSXXX

IICL Input Low Injection CurrentDI60a 0 — -5(5,8) mA All pins except VDD,

VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, and RB14

IICH Input High Injection CurrentDI60b 0 — +5(6,7,8) mA All pins except VDD,

VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, RB14, and digital 5V-tolerant designated pins

IICT Total Input Injection CurrentDI60c (sum of all I/O and control

pins)-20(9) — +20(9) mA Absolute instantaneous

sum of all ± input injection currents from all I/O pins( | IICL + | IICH | ) IICT


DC CHARACTERISTICS









dsPIC33FJXXXGSXXX

TABLE 18-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

TABLE 18-12: DC CHARACTERISTICS: PROGRAM MEMORY

DC CHARACTERISTICS



ParamNo. Symbol Characteristic(3) Min Typ(1) Max Units Conditions

Program Flash MemoryD130a EP Cell Endurance 10,000 — — E/W -40C to +125CD131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating

voltageD132B VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating

voltageD134 TRETD Characteristic Retention 20 — — Year Provided no other specifications

are violatedD135 IDDP Supply Current during

Programming— 10 — mA

D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles, TA = +100°C, See Note 2

D137b TPE Page Erase Time 19.5 — 27.3 ms TPE = 168517 FRC cycles, TA = +125°C, See Note 2

D138a TWW Word Write Cycle Time 47.9 — 48.8 µs TWW = 355 FRC cycles, TA = +100°C, See Note 2

D138b TWW Word Write Cycle Time 47.4 — 49.3 µs TWW = 355 FRC cycles, TA = +125°C, See Note 2

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max).

This parameter depends on the FRC accuracy (see Table 18-18) and the value of the FRC Oscillator Tuning register (see Register 9-3). For complete details on calculating the Minimum and Maximum time, see Section 6.3 “Programming Operations”.

3: These parameters are ensured by design, but are not characterized or tested in manufacturing.

DC CHARACTERISTICS



ParamNo. Symbol Characteristics Min Typ Max Units Comments

CEFC External Filter Capacitor Value

4.7 10 — µF Capacitor must be low series resistance (< 5 ohms)


dsPIC33FJXXXGSXXX

18.2 AC Characteristics and Timing Parameters

This section defines dsPIC33FJXXXGSXXX AC characteristics and timing parameters.

TABLE 18-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 18-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

TABLE 18-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

AC CHARACTERISTICS


-40°C TA +125°C for ExtendedOperating voltage VDD range as described in Section 18.1 “DC Characteristics”.

Param No. Symbol Characteristic Min Typ Max Units Conditions

DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In MS and HS modes when external clock is used to drive OSC1

DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode

VDD/2

CL

RL

Pin

Pin

VSS

VSS

CL

RL = 464CL = 50 pF for all pins except OSC2

15 pF for OSC2 output

Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2


dsPIC33FJXXXGSXXX

FIGURE 18-2: EXTERNAL CLOCK TIMING

Q1 Q2 Q3 Q4

OSC1

CLKO

Q1 Q2 Q3 Q4

OS20

OS25OS30 OS30

OS40OS41

OS31 OS31

TABLE 18-16: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS



ParamNo. Symb Characteristic Min Typ(1) Max Units Conditions

OS10 FIN External CLKI Frequency(External clocks allowed onlyin EC and ECPLL modes)

DC — 32 MHz EC

Oscillator Crystal Frequency 3.01031

———

103233

MHzMHzkHz

MSHSSOSC

OS20 TOSC TOSC = 1/FOSC 31.25 — DC ns —OS25 TCY Instruction Cycle Time(2,4) 62.5 — DC ns —OS30 TosL,

TosHExternal Clock in (OSC1)(5)

High or Low Time0.45 x TOSC — — ns EC

OS31 TosR,TosF

External Clock in (OSC1)(5)

Rise or Fall Time— — 20 ns EC

OS40 TckR CLKO Rise Time(3,5) — 6 10 ns —OS41 TckF CLKO Fall Time(3,5) — 6 10 ns —OS42 GM External Oscillator

Transconductance(4)14 16 18 mA/V VDD = 3.3V

TA = +25ºCNote 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: These parameters are characterized by similarity, but are tested in manufacturing at FIN = 32 MHz only.5: These parameters are characterized by similarity, but are not tested in manufacturing.6: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.


dsPIC33FJXXXGSXXX

TABLE 18-17: PLL CLOCK TIMING SPECIFICATIONS

AC CHARACTERISTICSStandard Operating Conditions: 2.4V to 3.6V (unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial


ParamNo. Symbol Characteristic Min Typ(1) Max Units Conditions

OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range(2)

3.0 — 8 MHz ECPLL and MSPLL modes

OS51 FSYS On-Chip VCO System Frequency(3)

12 — 32 MHz —

OS52 TLOCK PLL Start-up Time (Lock Time)(3) — — 2 mS —OS53 DCLK CLKO Stability (Jitter)(3) -2 1 +2 % —Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.2: These parameters are characterized by similarity, but are tested in manufacturing at 7.7 MHz input only.3: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is

based on clock cycle by clock cycle measurements. The effective jitter for individual time bases or commu-nication clocks used by the user application, are derived from dividing the CLKO stability specification by the square root of “N” (where “N” is equal to FOSC divided by the peripheral data rate clock). For example, if FOSC = 32 MHz and the SPI bit rate is 5 MHz, the effective jitter of the SPI clock is equal to:

TABLE 18-18: AC CHARACTERISTICS: INTERNAL FAST RC (FRC) ACCURACY



Param No. Characteristic Min Typ Max Units Conditions

Internal FRC Accuracy @ 7.3728 MHz(1)

F20a FRC -1 ±0.25 +1 % -40°C TA +85°CF20b FRC -2 — +2 % -40°C TA +125°CNote 1: Frequency calibrated at 25°C and 3.3V. TUN bits may be used to compensate for temperature drift.

DCLK

325

------

-------------- 2%2.53---------- 0.79%= =

TABLE 18-19: INTERNAL LOW-POWER RC (LPRC) ACCURACY



ParamNo. Characteristic Min Typ Max Units Conditions

LPRC @ 32.768 kHz(1,2)

F21a LPRC -40 — +40 % -40°C TA +85°CF21b LPRC -70 — +70 % -40°C TA +125°CNote 1: Change of LPRC frequency as VDD changes.

2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 15.4 “Watchdog Timer (WDT)” for more information.


dsPIC33FJXXXGSXXX

FIGURE 18-3: CLKO AND I/O TIMING CHARACTERISTICS

Note: Refer to Figure 18-1 for load conditions.

I/O Pin(Input)

I/O Pin(Output)

DI35

Old Value New Value

DI40

DO31DO32

TABLE 18-20: I/O TIMING REQUIREMENTS

AC CHARACTERISTICS




DO31 TIOR Port Output Rise Time — 10 25 ns —DO32 TIOF Port Output Fall Time — 10 25 ns —DI35 TINP INTx Pin High or Low Time (input) 25 — — ns —DI40 TRBP CNx High or Low Time (input) 2 — — TCY —Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: These parameters are characterized, but are not tested in manufacturing.


dsPIC33FJXXXGSXXX

FIGURE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS

VDD

MCLR

InternalPOR

PWRTTime-out

OSCTime-out

InternalReset

WatchdogTimerReset

SY11

SY10

SY20SY13

I/O Pins

SY13

Note: Refer to Figure 18-1 for load conditions.FSCM Delay

SY35

SY30

SY12

TABLE 18-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS

AC CHARACTERISTICS




SY10 TMCL MCLR Pulse Width (low) 2 — — s -40°C to +85°CSY11 TPWRT Power-up Timer Period(1) — 64 — ms -40°C to +85°CSY12 TPOR Power-on Reset Delay(3) 3 10 30 s -40°C to +85°C

SY13 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset(1)

— — 1.2 s —

SY20 TWDT1 Watchdog Timer Time-out Period(1)

— — — ms See Section 15.4 “Watch-dog Timer (WDT)” and LPRC parameter F21a (Table 18-19).

SY30 TOST Oscillator Start-up Time — 1024TOSC

— — TOSC = OSC1 period

SY35 TFSCM Fail-Safe Clock Monitor Delay(1) — 500 900 s -40°C to +85°CNote 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.3: These parameters are characterized, but are not tested in manufacturing.


dsPIC33FJXXXGSXXX

FIGURE 18-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS


Tx11

Tx15

Tx10

Tx20

TMRxOS60

TxCK

TABLE 18-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

AC CHARACTERISTICS



ParamNo. Symbol Characteristic(2) Min Typ Max Units Conditions

TA10 TTXH TxCK High Time

Synchronous mode

Greater of:20 or

(TCY + 20)/N

— — ns Must also meet parameter TA15 N = prescaler value (1, 8, 64, 256)

Asynchronous 35 — — ns

TA11 TTXL TxCK Low Time

Synchronous mode

Greater of:20 ns or

(TCY + 20)/N

— — ns Must also meet parameter TA15 N = prescaler value (1, 8, 64, 256)

Asynchronous 10 — — ns

TA15 TTXP TxCK Input Period

Synchronous mode

Greater of:40 or

(2 TCY + 40)/N

— — ns N = prescale value(1, 8, 64, 256)

OS60 Ft1 SOSC1/T1CK Oscillator Input frequency Range (oscillator enabled by set-ting bit TCS (T1CON<1>))

DC — 50 kHz —

TA20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment

0.75 TCY + 40 — 1.75 TCY + 40 ns —

Note 1: Timer1 is a Type A.2: These parameters are characterized by similarity, but are not tested in manufacturing.


dsPIC33FJXXXGSXXX

TABLE 18-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS




TB10 TtxH TxCK High Time

Synchronous mode

Greater of:20 or

(TCY + 20)/N

— — ns Must also meet parameter TB15 N = prescale value(1, 8, 64, 256)

TB11 TtxL TxCK Low Time

Synchronous mode

Greater of:20 or

(TCY + 20)/N

— — ns Must also meet parameter TB15 N = prescale value(1, 8, 64, 256)

TB15 TtxP TxCK Input Period

Synchronous mode

Greater of:40 or

(2 TCY + 40)/N

— — ns N = prescale value(1, 8, 64, 256)

TB20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Incre-ment

0.75 TCY + 40 — 1.75 TCY + 40 ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.

TABLE 18-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS




TC10 TtxH TxCK High Time

Synchronous TCY + 20 — — ns Must also meet parameter TC15

TC11 TtxL TxCK Low Time

Synchronous TCY + 20 — — ns Must also meet parameter TC15

TC15 TtxP TxCK Input Period

Synchronous,with prescaler

2 TCY + 40 — — ns N = prescalevalue (1, 8, 64, 256)

TC20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment

0.75 TCY + 40 — 1.75 TCY + 40 ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.


dsPIC33FJXXXGSXXX

FIGURE 18-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICx

IC10 IC11

IC15


TABLE 18-25: INPUT CAPTURE TIMING REQUIREMENTS

AC CHARACTERISTICS



ParamNo. Symbol Characteristic(1) Min Max Units Conditions

IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns —With Prescaler 10 — ns

IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns —With Prescaler 10 — ns

IC15 TccP ICx Input Period (TCY + 40)/N — ns N = prescale value (1, 4, 16)

Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.


dsPIC33FJXXXGSXXX

FIGURE 18-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

FIGURE 18-8: OC/PWM MODULE TIMING CHARACTERISTICS

OCx

OC11 OC10(Output Compare


or PWM Mode)

TABLE 18-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS



Param No. Symbol Characteristic(1) Min Typ Max Units Conditions

OC10 TccF OCx Output Fall Time — — — ns See parameter DO32OC11 TccR OCx Output Rise Time — — — ns See parameter DO31Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.

OCFA

OCx

OC20

OC15

Active Tri-state

TABLE 18-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

AC CHARACTERISTICS



Param No. Symbol Characteristic(1) Min Typ Max Units Conditions

OC15 TFD Fault Input to PWM I/O Change

— — TCY + 20 ns ns —

OC20 TFLT Fault Input Pulse Width TCY + 20 ns — — ns —Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.


dsPIC33FJXXXGSXXX

FIGURE 18-9: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS

FIGURE 18-10: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS

FLTA1

PWMx

MP30

MP20

See Note 1

Note 1: For the logic state after a Fault, refer to the FAOVxH:FAOVxL bits in the PxFLTACON register.

PWMx

MP11 MP10


TABLE 18-28: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS




MP10 TFPWM PWM Output Fall Time — — — ns See parameter DO32MP11 TRPWM PWM Output Rise Time — — — ns See parameter DO31

MP20 TFD Fault Input to PWMI/O Change

— — 50 ns —

MP30 TFH Minimum Pulse Width 50 — — ns —Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.


dsPIC33FJXXXGSXXX

TABLE 18-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY

FIGURE 18-11: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING CHARACTERISTICS

AC CHARACTERISTICS



Maximum Data Rate

Master Transmit Only (Half-Duplex)

Master Transmit/Receive

(Full-Duplex)

Slave Transmit/Receive

(Full-Duplex)CKE CKP SMP

15 MHz Table 18-30 — — 0,1 0,1 0,110 MHz — Table 18-31 — 1 0,1 1

10 MHz — Table 18-32 — 0 0,1 1

15 MHz — — Table 18-33 1 0 0

11 MHz — — Table 18-34 1 1 0

15 MHz — — Table 18-35 0 1 0

11 MHz — — Table 18-36 0 0 0

SCKx(CKP = 0)

SCKx(CKP = 1)

SDOx

SP10

SP21SP20SP35

SP20SP21

MSb LSbBit 14 - - - - - -1

SP30, SP31SP30, SP31



dsPIC33FJXXXGSXXX

FIGURE 18-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING CHARACTERISTICS

TABLE 18-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS

AC CHARACTERISTICS




SP10 TscP Maximum SCK Frequency — — 15 MHz See Note 3SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32

and Note 4SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31

and Note 4SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32

and Note 4SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31

and Note 4SP35 TscH2doV,

TscL2doVSDOx Data Output Valid after SCKx Edge

— 6 20 ns —

SP36 TdiV2scH,TdiV2scL

SDOx Data Output Setup to First SCKx Edge

30 — — ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not

violate this specification.4: Assumes 50 pF load on all SPIx pins.

SCKx(CKP = 0)

SCKx(CKP = 1)

SDOx

SP10

SP21SP20SP35

SP20SP21

MSb LSbBit 14 - - - - - -1

SP30, SP31


SP36


dsPIC33FJXXXGSXXX

FIGURE 18-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS

TABLE 18-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS


-40°C TA +125°C for ExtendedParam

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscP Maximum SCK Frequency — — 10 MHz See Note 3SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32

and Note 4SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31




TscL2doVSDOx Data Output Valid afterSCKx Edge

— 6 20 ns —

SP36 TdoV2sc, TdoV2scL

SDOx Data Output Setup toFirst SCKx Edge

30 — — ns —

SP40 TdiV2scH, TdiV2scL

Setup Time of SDIx Data Input to SCKx Edge

30 — — ns —

SP41 TscH2diL, TscL2diL

Hold Time of SDIx Data Inputto SCKx Edge

30 — — ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this

specification.4: Assumes 50 pF load on all SPIx pins.

SCKx(CKP = 0)

SCKx(CKP = 1)

SDOx

SP10

SP21SP20SP35

SP20SP21

MSb LSbBit 14 - - - - - -1

SP30, SP31


SP36

SP41

MSb In LSb InBit 14 - - - -1SDIx

SP40


dsPIC33FJXXXGSXXX

FIGURE 18-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS

TABLE 18-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS


-40°C TA +125°C for ExtendedParam

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscP Maximum SCK Frequency — — 10 MHz -40ºC to +125ºC and see Note 3

SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32 and Note 4

SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31 and Note 4

SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4

SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4

SP35 TscH2doV,TscL2doV

SDOx Data Output Valid afterSCKx Edge

— 6 20 ns —

SP36 TdoV2scH, TdoV2scL


30 — — ns —


Setup Time of SDIx Data Input to SCKx Edge

30 — — ns —



30 — — ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this

specification.4: Assumes 50 pF load on all SPIx pins.

SCKx(CKP = 0)

SCKx(CKP = 1)

SDOx

SDIx

SP10

SP40 SP41

SP21SP20SP35

SP20SP21

MSb LSbBit 14 - - - - - -1

MSb In LSb InBit 14 - - - -1

SP30, SP31SP30, SP31



dsPIC33FJXXXGSXXX

FIGURE 18-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

SSx

SCKx(CKP = 0)

SCKx(CKP = 1)

SDOx

SDI

SP50

SP60

SDIx

SP30,SP31

MSb Bit 14 - - - - - -1 LSb

SP51

MSb In Bit 14 - - - -1 LSb In

SP35

SP52

SP73SP72

SP72SP73SP70

SP40SP41



dsPIC33FJXXXGSXXX

TABLE 18-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS




SP70 TscP Maximum SCK Input Frequency — — 15 MHz See Note 3SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32

and Note 4SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31





— 6 20 ns —



30 — — ns —


Setup Time of SDIx Data Inputto SCKx Edge

30 — — ns —



30 — — ns —

SP50 TssL2scH, TssL2scL

SSx to SCKx or SCKx Input 120 — — ns —

SP51 TssH2doZ SSx to SDOx OutputHigh-Impedance(4)

10 — 50 ns —

SP52 TscH2ssHTscL2ssH

SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4

SP60 TssL2doV SDOx Data Output Valid after SSx Edge

— — 50 ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must

not violate this specification.4: Assumes 50 pF load on all SPIx pins.


dsPIC33FJXXXGSXXX


SSx

SCKx(CKP = 0)

SCKx(CKP = 1)

SDOx

SDI

SP50

SP60

SDIx

SP30,SP31

MSb Bit 14 - - - - - -1 LSb

SP51


SP35

SP52

SP52

SP73SP72

SP72SP73SP70

SP40SP41



dsPIC33FJXXXGSXXX


AC CHARACTERISTICS










— 6 20 ns —



30 — — ns —



30 — — ns —



30 — — ns —




10 — 50 ns —



SP60 TssL2doV SDOx Data Output Valid after SSx Edge

— — 50 ns —

Note 1: These parameters are characterized, but are not tested in manufacturing.2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not



dsPIC33FJXXXGSXXX

FIGURE 18-17: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

SSX

SCKX(CKP = 0)

SCKX(CKP = 1)

SDOX

SP50

SP40SP41

SP30,SP31 SP51

SP35

MSb LSbBit 14 - - - - - -1


SP52

SP73SP72

SP72SP73SP70


SDIX


dsPIC33FJXXXGSXXX


AC CHARACTERISTICS










— 6 20 ns —



30 — — ns —



30 — — ns —



30 — — ns —




10 — 50 ns —



Note 1: These parameters are characterized, but are not tested in manufacturing.2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must

not violate this specification.4: Assumes 50 pF load on all SPIx pins.


dsPIC33FJXXXGSXXX


SSX

SCKX(CKP = 0)

SCKX(CKP = 1)

SDOX

SP50

SP40SP41

SP30,SP31 SP51

SP35

MSb LSbBit 14 - - - - - -1


SP52

SP73SP72

SP72SP73SP70


SDIX


dsPIC33FJXXXGSXXX


AC CHARACTERISTICS










— 6 20 ns —



30 — — ns —



30 — — ns —



30 — — ns —




10 — 50 ns —



Note 1: These parameters are characterized, but are not tested in manufacturing.2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not



dsPIC33FJXXXGSXXX

FIGURE 18-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

FIGURE 18-20: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM31 IM34SCLx

SDAx

StartCondition

StopCondition

IM30 IM33


IM11IM10 IM33

IM11IM10

IM20

IM26IM25

IM40 IM40 IM45

IM21

SCLx

SDAxIn

SDAxOut



dsPIC33FJXXXGSXXX

TABLE 18-37: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)

AC CHARACTERISTICS



ParamNo. Symbol Characteristic Min(1) Max Units Conditions

IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s —400 kHz mode TCY/2 (BRG + 1) — s —1 MHz mode(2) TCY/2 (BRG + 1) — s —

IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s —400 kHz mode TCY/2 (BRG + 1) — s —1 MHz mode(2) TCY/2 (BRG + 1) — s —

IM20 TF:SCL SDAx and SCLxFall Time

100 kHz mode — 300 ns CB is specified to be from 10 to 400 pF400 kHz mode 20 + 0.1 CB 300 ns

1 MHz mode(2) — 100 nsIM21 TR:SCL SDAx and SCLx

Rise Time100 kHz mode — 1000 ns CB is specified to be

from 10 to 400 pF400 kHz mode 20 + 0.1 CB 300 ns1 MHz mode(2) — 300 ns

IM25 TSU:DAT Data InputSetup Time

100 kHz mode 250 — ns —400 kHz mode 100 — ns1 MHz mode(2) 40 — ns

IM26 THD:DAT Data InputHold Time

100 kHz mode 0 — s —400 kHz mode 0 0.9 s1 MHz mode(2) 0.2 — s

IM30 TSU:STA Start ConditionSetup Time

100 kHz mode TCY/2 (BRG + 1) — s Only relevant for Repeated Startcondition

400 kHz mode TCY/2 (BRG + 1) — s1 MHz mode(2) TCY/2 (BRG + 1) — s

IM31 THD:STA Start Condition Hold Time

100 kHz mode TCY/2 (BRG + 1) — s After this period thefirst clock pulse isgenerated

400 kHz mode TCY/2 (BRG + 1) — s1 MHz mode(2) TCY/2 (BRG + 1) — s

IM33 TSU:STO Stop Condition Setup Time

100 kHz mode TCY/2 (BRG + 1) — s —400 kHz mode TCY/2 (BRG + 1) — s1 MHz mode(2) TCY/2 (BRG + 1) — s

IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns —Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns

1 MHz mode(2) TCY/2 (BRG + 1) — nsIM40 TAA:SCL Output Valid

From Clock100 kHz mode — 3500 ns —400 kHz mode — 1000 ns —1 MHz mode(2) — 400 ns —

IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before a newtransmission can start

400 kHz mode 1.3 — s1 MHz mode(2) 0.5 — s

IM50 CB Bus Capacitive Loading — 400 pF —IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)”

(DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site for the latest dsPIC33F/PIC24H Family Reference Manual sections.

2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).3: Typical value for this parameter is 130 ns.


dsPIC33FJXXXGSXXX

FIGURE 18-21: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

FIGURE 18-22: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS31 IS34SCLx

SDAx

StartCondition

StopCondition

IS30 IS33

IS30IS31 IS33

IS11

IS10

IS20

IS26IS25

IS40 IS40 IS45

IS21

SCLx

SDAxIn

SDAxOut


dsPIC33FJXXXGSXXX

TABLE 18-38: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

AC CHARACTERISTICS



Param. Symbol Characteristic Min Max Units Conditions

IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz

400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz

1 MHz mode(1) 0.5 — s —IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a

minimum of 1.5 MHz400 kHz mode 0.6 — s Device must operate at a

minimum of 10 MHz1 MHz mode(1) 0.5 — s —

IS20 TF:SCL SDAx and SCLxFall Time

100 kHz mode — 300 ns CB is specified to be from10 to 400 pF400 kHz mode 20 + 0.1 CB 300 ns

1 MHz mode(1) — 100 nsIS21 TR:SCL SDAx and SCLx

Rise Time100 kHz mode — 1000 ns CB is specified to be from

10 to 400 pF400 kHz mode 20 + 0.1 CB 300 ns1 MHz mode(1) — 300 ns

IS25 TSU:DAT Data InputSetup Time

100 kHz mode 250 — ns —400 kHz mode 100 — ns1 MHz mode(1) 100 — ns

IS26 THD:DAT Data InputHold Time

100 kHz mode 0 — s —400 kHz mode 0 0.9 s1 MHz mode(1) 0 0.3 s

IS30 TSU:STA Start ConditionSetup Time

100 kHz mode 4.7 — s Only relevant for Repeated Start condition400 kHz mode 0.6 — s

1 MHz mode(1) 0.25 — sIS31 THD:STA Start Condition

Hold Time 100 kHz mode 4.0 — s After this period, the first

clock pulse is generated400 kHz mode 0.6 — s1 MHz mode(1) 0.25 — s

IS33 TSU:STO Stop Condition Setup Time

100 kHz mode 4.7 — s —400 kHz mode 0.6 — s1 MHz mode(1) 0.6 — s

IS34 THD:STO Stop ConditionHold Time

100 kHz mode 4000 — ns —400 kHz mode 600 — ns1 MHz mode(1) 250 ns

IS40 TAA:SCL Output Valid From Clock

100 kHz mode 0 3500 ns —400 kHz mode 0 1000 ns1 MHz mode(1) 0 350 ns

IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before a new transmission can start

400 kHz mode 1.3 — s1 MHz mode(1) 0.5 — s

IS50 CB Bus Capacitive Loading — 400 pF —Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).


dsPIC33FJXXXGSXXX

TABLE 18-39: ADC MODULE SPECIFICATIONS

AC CHARACTERISTICS



Param No. Symbol Characteristic Min. Typ Max. Units Conditions

Device SupplyAD01 AVDD Module VDD Supply(2,4) Greater of

VDD – 0.3or 2.9

— Lesser ofVDD + 0.3

or 3.6

V—

AD02 AVSS Module VSS Supply(2,5) VSS – 0.3 — VSS + 0.3 V —AD09 IAD Operating Current — 7.0 9.0 mA See Note 1

Analog InputAD12 VINH Input Voltage Range

VINH(2)VINL — AVDD V This voltage reflects Sample

and Hold Channels 0, 1, 2, and 3 (CH0-CH3), positive input

AD13 VINL Input Voltage Range VINL(2)

AVSS — AVSS + 1V V This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), negative input

AD17 RIN Recommended Imped-ance of Analog Voltage Source(3)

— — 200 —

Note 1: These parameters are not characterized or tested in manufacturing.2: These parameters are characterized, but are not tested in manufacturing.3: These parameters are assured by design, but are not characterized or tested in manufacturing.4: This pin may not be available on all devices, in which case, this pin will be connected to VDD internally.

See the “Pin Diagrams” section for availability.5: This pin may not be available on all devices, in which case, this pin will be connected to VSS internally. See

the “Pin Diagrams” section for availability.


dsPIC33FJXXXGSXXX

TABLE 18-40: 10-BIT ADC MODULE SPECIFICATIONS

AC CHARACTERISTICS




10-bit ADC Accuracy – Measurements with AVDD/AVSS(3)

AD20b Nr Resolution 10 data bits bits —AD21b INL Integral Nonlinearity -1 — +1 LSb VINL = AVSS = 0V, AVDD = 3.6VAD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6VAD23b GERR Gain Error 3 7 15 LSb VINL = AVSS = 0V, AVDD = 3.6VAD24b EOFF Offset Error 1.5 3 7 LSb VINL = AVSS = 0V, AVDD = 3.6VAD25b — Monotonicity — — — — Guaranteed(1)

Dynamic Performance (10-bit Mode)(2)

AD30b THD Total Harmonic Distortion — — -64 dB —AD31b SINAD Signal to Noise and

Distortion 57 58.5 — dB —

AD32b SFDR Spurious Free DynamicRange

72 — — dB —

AD33b FNYQ Input Signal Bandwidth — — 550 kHz —AD34b ENOB Effective Number of Bits 9.16 9.4 — bits —Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.2: These parameters are characterized by similarity, but are not tested in manufacturing.3: These parameters are characterized, but are tested at 20 ksps only.


dsPIC33FJXXXGSXXX

FIGURE 18-23: ADC CONVERSION TIMING CHARACTERISTICS(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)

FIGURE 18-24: ADC CONVERSION TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

AD55TSAMP

Clear SAMPSet SAMP

AD61

ADCLKInstruction

SAMP

AD60

DONE

ADxIF

1 2 3 4 5 6 8 5 6 7

1 – Software sets ADxCON. SAMP to start sampling.

2 – Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)”

3 – Software clears ADxCON. SAMP to start conversion.

4 – Sampling ends, conversion sequence starts.

5 – Convert bit 9.

8 – One TAD for end of conversion.

AD50

7

AD55

8



Execution

(DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”.

1 2 3 4 5 6 4 5 6 8

1 – Software sets ADxCON. ADON to start AD operation.

2 – Sampling starts after discharge period. TSAMP is described in




7 3

6 – One TAD for end of conversion.

7 – Begin conversion of next channel.

8 – Sample for time specified by SAMC<4:0>.

ADCLK

Instruction Set ADONExecution

SAMPTSAMP

ADxIF

DONE

AD55 AD55 TSAMP AD55

AD50

Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)in the “dsPIC33F/PIC24H Family Reference Manual”.


dsPIC33FJXXXGSXXX

TABLE 18-41: 10-BIT ADC CONVERSION TIMING REQUIREMENTS

AC CHARACTERISTICS



Param No. Symbol Characteristic Min. Typ(1) Max. Units Conditions

Clock Parameters(2)

AD50 TAD ADC Clock Period 76 — — ns —AD51 tRC ADC Internal RC Oscillator Period — 250 — ns —

Conversion RateAD55 tCONV Conversion Time — 12 TAD — — —AD56 FCNV Throughput Rate — — 1.1 Msps —AD57 TSAMP Sample Time 2.0 TAD — — — —

Timing ParametersAD60 tPCS Conversion Start from Sample

Trigger(1)2.0 TAD — 3.0 TAD — Auto-Convert Trigger

(SSRC<2:0> = 111) not selected

AD61 tPSS Sample Start from SettingSample (SAMP) bit(1)

2.0 TAD — 3.0 TAD — —

AD62 tCSS Conversion Completion toSample Start (ASAM = 1)(1)

— 0.5 TAD — — —

AD63 tDPU Time to Stabilize Analog Stage from ADC Off to ADC On(1)

— — 20 s —

Note 1: These parameters are characterized but not tested in manufacturing.2: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity

performance, especially at elevated temperatures.


dsPIC33FJXXXGSXXX

TABLE 18-42: COMPARATOR TIMING SPECIFICATIONS

AC CHARACTERISTICS




300 TRESP Response Time(1,2) — 150 400 ns —301 TMC2OV Comparator Mode Change

to Output Valid(1)— — 10 s —

302 TON2OV Comparator Enabled to Output Valid

— — 10 µs —

Note 1: Parameters are characterized but not tested.2: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from

VSS to VDD.

TABLE 18-43: COMPARATOR MODULE SPECIFICATIONS

DC CHARACTERISTICS




D300 VIOFF Input Offset Voltage(1) — ±10 — mV —D301 VICM Input Common Mode Voltage(1) 0 — AVDD-1.5V V —

D302 CMRR Common Mode Rejection Ratio(1) -54 — — dB —

D305 IVREF Internal Voltage Reference — 1.2 — V —Note 1: Parameters are characterized but not tested.

TABLE 18-44: COMPARATOR REFERENCE VOLTAGE SETTLING TIME SPECIFICATIONS

AC CHARACTERISTICS




VR310 TSET Settling Time(1) — — 10 s —Note 1: Setting time measured while CVRR = 1 and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’.

TABLE 18-45: COMPARATOR REFERENCE VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions:2.9V to 3.6V(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial



VRD310 CVRES Resolution CVRSRC/24 — CVRSRC/32 LSb —VRD311 CVRAA Absolute Accuracy — — 0.5 LSb —VRD312 CVRUR Unit Resistor Value (R) — 2k — —


dsPIC33FJXXXGSXXX

TABLE 18-46: CTMU CURRENT SOURCE SPECIFICATIONSDC CHARACTERISTICS Standard Operating Conditions:2.9V to 3.6V

(unless otherwise stated)Operating temperature -40°C TA +85°C for Industrial



CTMU CURRENT SOURCE

CTMUI1 IOUT1 Base Range — 550 — na CTMUICON<1:0> = 01CTMUI2 IOUT2 10x Range — 5.5 — µA CTMUICON<1:0> = 10CTMUI3 IOUT3 100x Range — 55 — µA CTMUICON<1:0> = 11Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000).


dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

19.0 DC AND AC DEVICE CHARACTERIZATION GRAPHS

“Typical” represents the mean of the distribution at +25C. “Maximum” or “minimum” represents (mean + 3) or (mean -3) respectively, where is a standard deviation, over the entire temperature range.

FIGURE 19-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)

FIGURE 19-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

Note: The graphs provided following this note are a statistical summary based on a limited number of samplesand are provided for informational purposes only. The performance characteristics listed herein are nottested or guaranteed. In some graphs, the data presented may be outside the specified operating range(e.g., outside specified power supply range) and therefore, outside the warranted range.

0

2

4

6

8

10

12

4 6 8 10 12 14 16 18 20 22 24 26

FOSC (M Hz)

I DD

(mA

)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ +25°CMaximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C)

0

2

4

6

8

10

12

4 6 8 10 12 14 16 18 20 22 24 26

FOSC (M Hz)

I DD

(mA

)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V



dsPIC33FJXXXGSXXX

FIGURE 19-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)

FIGURE 19-4: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE)

0

2

4

6

8

10

12

14

16

18

20

4 5 6 7 8 9 10

FOSC (MHz)

IDD

(mA

)

5.5V

5.0V

4.5V

4.2V


0

2

4

6

8

10

12

14

16

18

20

4 5 6 7 8 9 10

FOSC (MHz)

IDD

(mA

)

5.5V

5.0V

4.5V

4.2V



dsPIC33FJXXXGSXXX

FIGURE 19-5: TYPICAL IDD vs. FOSC OVER VDD (EC MODE)

FIGURE 19-6: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)

0

2

4

6

8

10

12

14

16

4 8 12 16 20 24 28 32 36 40

FOSC (MHz)

IDD

(mA

)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

4.2V


0

2

4

6

8

10

12

14

16

4 8 12 16 20 24 28 32 36 40

FOSC (MHz)

IDD

(mA

)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

4.2V



dsPIC33FJXXXGSXXX

FIGURE 19-7: IPD vs. VDD, -40C TO +125C (SLEEP MODE, ALL PERIPHERALS DISABLED)

FIGURE 19-8: IBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.00 - 2.16V)

0.01

0.1

1

10

100

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD

(uA

)

Typ (+25°C)

Max(+85°C)

Max(-40°C to +125°C)


0

10

20

30

40

50

60

70

80

90

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD

( A

)

Max (125C)

Max (85C)

Typ (25C)

Device Held in Reset

Device in

Sleep


Max (+125°C)

Max (+85°C)

Typ (+25°C)

DeviceHeld inRESET

Devicein

SLEEP


dsPIC33FJXXXGSXXX

FIGURE 19-9: TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)

FIGURE 19-10: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C)

0

10

20

30

40

50

60

70

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD

( A

) Max (125C)

Max (85C)

Typ (25C)


Max (+125°C)

Max (+85°C)

Typ (+25°C)

0

5

10

15

20

25

30

35

40

45

50

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

WD

T Pe

riod

(ms)

Max(125C)

MAX(85C)

Typ(25C)

Min(-40C)


Max(+125°C)

Max(+85°C)

Typ(+25°C)

Min(-40°C)


dsPIC33FJXXXGSXXX

FIGURE 19-11: ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 3.0 - 3.6V)

FIGURE 19-12: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3.6V, -40C TO +125C)

0

10

20

30

40

50

60

70

80

90

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD

( A

)

Max (125C)

Typ (25C)

Max (125C)

Typ (25C)

LVDIF is set by hardware

LVDIF can be cleared by firmware

LVDIF state is unknown

Max (+125°C)

Max (+125°C)

Typ (+25°C)

Typ (+25°C)


0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 5 10 15 20 25

IOH (-mA)

VOH

(V)

Typ (25C)

Max

Min

Max

Typ (+25°C)

Min


dsPIC33FJXXXGSXXX

FIGURE 19-13: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3.6V, -40C TO +125C)

FIGURE 19-14: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3.6V, -40C TO +125C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 5 10 15 20 25

IOH (-mA)

VOH

(V)

Typ (25C)

Max

Min

Typ (+25°C)

Min

Max

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0 5 10 15 20 25

IOL (-mA)

VOL

(V)

Max

Typ (25C)


Typ (+25°C)

Max


dsPIC33FJXXXGSXXX

FIGURE 19-15: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3.6V, -40C TO +125C)

FIGURE 19-16: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)

0.0

0.5

1.0

1.5

2.0

2.5

0 5 10 15 20 25

IOL (-mA)

VOL

(V)

Max

Typ (25C)


Typ (+25°C)

Max

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN

(V)

VIH Max

VIH Min

VIL Max

VIL Min



dsPIC33FJXXXGSXXX

FIGURE 19-17: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C)

FIGURE 19-18: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN

(V)

VTH (Max)

VTH (Min)


0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN

(V)

VIH Max

VIH Min

VILMax

VIL Min



dsPIC33FJXXXGSXXX

FIGURE 19-19: A/D NON-LINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C)

FIGURE 19-20: A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40C TO +125C)

0

0.5

1

1.5

2

2.5

3

3.5

4

2 2.5 3 3.5 4 4.5 5 5.5

VDD and VREFH (V)

Diff

eren

tial o

r Int

egra

l Non

linea

rity

(LSB

)

-40C

25C

85C

125C

-40°C

+25°C

+85°C

+125°C

0

0.5

1

1.5

2

2.5

3

2 2.5 3 3.5 4 4.5 5 5.5

VREFH (V)

Diff

eren

tial o

r Int

egra

l Non

linea

rilty

(LSB

)

Max (-40C to 125C)

Typ (25C)Typ (+25°C)

Max (-40°C to +125°C)


dsPIC33FJXXXGSXXX

20.0 PACKAGING INFORMATION

20.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: If the full Microchip part number cannot be marked on one line, it is carried over to the nextline, thus limiting the number of available characters for customer-specific information.

3e

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XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

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0730235

20-Lead SSOP

XXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

dsPIC33FJ16MC101-ISS

0730235

101-E/P 3e

3e

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XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

dsPIC33FJ16MC101-ISO

06100173e

18-Lead PDIP


YYWWNNN

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0730235101-E/P 3e

18-Lead SOIC

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

dsPIC33FJ16GP101-E/SO

0610017

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20.1 Package Marking Information (Continued)

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: If the full Microchip part number cannot be marked on one line, it is carried over to the nextline, thus limiting the number of available characters for customer-specific information.

3e

3e

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33FJJ16MC102EML0730235

3e

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XXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

33FJ16MC102-E/SS

07302353e

36-Lead TLA

XXXXXXXXXXXXXXXXYYWWNNN

Example

33FJJ16MC102ETL0730235

3e

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YYWWNNN

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dsPIC33FJ16MC

0730235

28-Lead SOIC

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

dsPIC33FJ16MC

0730235

102-E/SP

102-E/SO

3e

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XXXXXXXXXXXXXXXXYYWWNNN


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Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging


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28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]

Notes:1. Pin 1 visual index feature may vary, but must be located within the hatched area.2. § Significant Characteristic.3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.


Units INCHESDimension Limits MIN NOM MAX

Number of Pins N 28Pitch e .100 BSCTop to Seating Plane A – – .200Molded Package Thickness A2 .120 .135 .150Base to Seating Plane A1 .015 – –Shoulder to Shoulder Width E .290 .310 .335Molded Package Width E1 .240 .285 .295Overall Length D 1.345 1.365 1.400Tip to Seating Plane L .110 .130 .150Lead Thickness c .008 .010 .015Upper Lead Width b1 .040 .050 .070Lower Lead Width b .014 .018 .022Overall Row Spacing § eB – – .430

NOTE 1

N

1 2

D

E1

eB

c

E

L

A2

eb

b1A1

A

3

Microchip Technology Drawing C04-070B


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28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

Notes:1. Pin 1 visual index feature may vary, but must be located within the hatched area.2. § Significant Characteristic.3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.REF: Reference Dimension, usually without tolerance, for information purposes only.


Units MILLMETERSDimension Limits MIN NOM MAX

Number of Pins N 28Pitch e 1.27 BSCOverall Height A – – 2.65Molded Package Thickness A2 2.05 – –Standoff § A1 0.10 – 0.30Overall Width E 10.30 BSCMolded Package Width E1 7.50 BSCOverall Length D 17.90 BSCChamfer (optional) h 0.25 – 0.75Foot Length L 0.40 – 1.27Footprint L1 1.40 REFFoot Angle Top φ 0° – 8°Lead Thickness c 0.18 – 0.33Lead Width b 0.31 – 0.51Mold Draft Angle Top α 5° – 15°Mold Draft Angle Bottom β 5° – 15°

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28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]

with 0.55 mm Contact Length

Notes:

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BSC: Basic Dimension. Theoretically exact value shown without tolerances.REF: Reference Dimension, usually without tolerance, for information purposes only.


Units MILLIMETERSDimension Limits MIN NOM MAX

Number of Pins N 28Pitch e 0.65 BSCOverall Height A 0.80 0.90 1.00Standoff A1 0.00 0.02 0.05Contact Thickness A3 0.20 REFOverall Width E 6.00 BSCExposed Pad Width E2 3.65 3.70 4.20Overall Length D 6.00 BSCExposed Pad Length D2 3.65 3.70 4.20Contact Width b 0.23 0.30 0.35Contact Length L 0.50 0.55 0.70Contact-to-Exposed Pad K 0.20 – –

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36-Lead Thermal Leadless Array (TL) – 5x5 mm Body [TLA]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at:http://www.microchp.com/packaging

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dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

APPENDIX A: REVISION HISTORY

Revision A (February 2011)This is the initial released version of this document.


dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

INDEXAAC Characteristics ............................................................ 204

Internal Fast RC (FRC) Accuracy ............................. 206Internal Low-Power RC (LPRC) Accuracy ................ 206Load Conditions ........................................................ 204

ADCInitialization ............................................................... 161Key Features............................................................. 161

ADC ModuleADC1 Register Map .................................................... 58ADC11 Register Map .................................................. 57

Alternate Interrupt Vector Table (AIVT) .............................. 85Analog-to-Digital Converter (ADC).................................... 161Arithmetic Logic Unit (ALU)................................................. 39Assembler

MPASM Assembler................................................... 192

BBarrel Shifter ....................................................................... 43Bit-Reversed Addressing .................................................... 67

Example ...................................................................... 68Implementation ........................................................... 67Sequence Table (16-Entry)......................................... 68

Block DiagramsConnections for On-Chip Voltage Regulator............. 180Device Clock ............................................................. 117DSP Engine ................................................................ 40dsPIC33FJXXXGSXXX............................................... 24dsPIC33FJXXXGSXXX CPU Core ............................. 34Reset System.............................................................. 77Shared Port Structure ............................................... 131SPI ............................................................................ 149UART ........................................................................ 155Watchdog Timer (WDT) ............................................ 181

CC Compilers

MPLAB C18 .............................................................. 192Clock Switching................................................................. 124

Enabling .................................................................... 124Sequence.................................................................. 124

Code ExamplesPort Write/Read ........................................................ 132PWRSAV Instruction Syntax..................................... 125

Code Protection ........................................................ 175, 182Configuration Bits.............................................................. 175Configuration Register Map .............................................. 175Configuring Analog Port Pins............................................ 132CPU

Control Register .......................................................... 36CPU Clocking System....................................................... 118

PLL Configuration ..................................................... 119Selection ................................................................... 118Sources..................................................................... 118

CTMU ModuleRegister Map............................................................... 59

Customer Change Notification Service ............................. 271Customer Notification Service........................................... 271Customer Support ............................................................. 271

DData Accumulators and Adder/Subtracter .......................... 41

Data Space Write Saturation ...................................... 43Overflow and Saturation ............................................. 41Round Logic ............................................................... 43Write Back .................................................................. 42

Data Address Space........................................................... 47Alignment.................................................................... 47Memory Map for dsPIC33FJXXXGSXXX Devices

with 1 KB RAM ................................................... 48Near Data Space ........................................................ 47Software Stack ........................................................... 64Width .......................................................................... 47

DC and AC CharacteristicsGraphs and Tables ................................................... 237

DC Characteristics............................................................ 196BOR.......................................................................... 197I/O Pin Input Specifications ...................................... 201I/O Pin Output Specifications.................................... 202Idle Current (IDOZE) .................................................. 200Idle Current (IIDLE) .................................................... 199Operating Current (IDD) ............................................ 198Power-Down Current (IPD)........................................ 200Program Memory...................................................... 203Temperature and Voltage Specifications.................. 197

Development Support ....................................................... 191Doze Mode ....................................................................... 126DSP Engine ........................................................................ 39

Multiplier ..................................................................... 41

EElectrical Characteristics .................................................. 195

AC............................................................................. 204Equations

Device Operating Frequency.................................... 118Errata.................................................................................. 13

FFlash Program Memory ...................................................... 73

Control Registers........................................................ 74Operations .................................................................. 74Programming Algorithm.............................................. 74RTSP Operation ......................................................... 74Table Instructions ....................................................... 73

Flexible Configuration....................................................... 175

II/O Ports ........................................................................... 131

Parallel I/O (PIO) ...................................................... 131Write/Read Timing.................................................... 132

I2C ModuleI2C1 Register Map...................................................... 55

In-Circuit Debugger........................................................... 182In-Circuit Emulation .......................................................... 175In-Circuit Serial Programming (ICSP)....................... 175, 182Input Change Notification ................................................. 132


dsPIC33FJXXXGSXXX

Instruction Addressing Modes............................................. 64File Register Instructions ............................................ 64Fundamental Modes Supported.................................. 65MAC Instructions......................................................... 65MCU Instructions ........................................................ 64Move and Accumulator Instructions............................ 65Other Instructions........................................................ 65

Instruction SetOverview ................................................................... 186Summary................................................................... 183

Instruction-Based Power-Saving Modes ........................... 125Idle ............................................................................ 126Sleep......................................................................... 125

Internal RC OscillatorUse with WDT ........................................................... 181

Internet Address................................................................ 271Interrupt Control and Status Registers................................ 89

IECx ............................................................................ 89IFSx............................................................................. 89INTCON1 .................................................................... 89INTCON2 .................................................................... 89IPCx ............................................................................ 89

Interrupt Setup Procedures ............................................... 115Initialization ............................................................... 115Interrupt Disable........................................................ 115Interrupt Service Routine .......................................... 115Trap Service Routine ................................................ 115

Interrupt Vector Table (IVT) ................................................ 85Interrupts Coincident with Power Save Instructions.......... 126

JJTAG Boundary Scan Interface ........................................ 175JTAG Interface .................................................................. 182

MMemory Organization.......................................................... 45Microchip Internet Web Site .............................................. 271Modulo Addressing ............................................................. 66

Applicability ................................................................. 67Operation Example ..................................................... 66Start and End Address................................................ 66W Address Register Selection .................................... 66

Motor Control PWM Module6-Output Register Map................................................ 55

MPLAB ASM30 Assembler, Linker, Librarian ................... 192MPLAB Integrated Development Environment Software .. 191MPLAB PM3 Device Programmer..................................... 194MPLAB REAL ICE In-Circuit Emulator System................. 193MPLINK Object Linker/MPLIB Object Librarian ................ 192

NNVM Module

Register Map............................................................... 63

OOpen-Drain Configuration ................................................. 132

PPackaging ......................................................................... 247

Details ....................................................................... 249Marking ............................................................. 247, 248

PAD ConfigurationRegister Map............................................................... 59

Peripheral Module Disable (PMD)..................................... 126Pinout I/O Descriptions (table) ............................................ 25

PMD ModuleRegister Map .............................................................. 63

PORTARegister Map .............................................................. 62

PORTBRegister Map for dsPIC33FJ12MC201....................... 62Register Map for dsPIC33FJ12MC202....................... 62

Power-on Reset (POR)....................................................... 82Power-Saving Features .................................................... 125

Clock Frequency and Switching ............................... 125Program Address Space..................................................... 45

Construction ............................................................... 69Data Access from Program Memory Using

Program Space Visibility..................................... 72Data Access from Program Memory Using

Table Instructions ............................................... 71Data Access from, Address Generation ..................... 70Memory Map............................................................... 45Table Read Instructions

TBLRDH ............................................................. 71TBLRDL.............................................................. 71

Visibility Operation...................................................... 72Program Memory

Interrupt Vector ........................................................... 46Organization ............................................................... 46Reset Vector ............................................................... 46

RReader Response............................................................. 272Register Map

Real-Time Clock and Calendar................................... 59Register Maps

Comparator................................................................. 60Registers

AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 170ADxCHS0 (ADCx Input Channel 0 Select ................ 171ADxCON1 (ADCx Control 1)..................................... 166ADxCON2 (ADCx Control 2)..................................... 168ADxCON3 (ADCx Control 3)..................................... 169ADxCSSL (ADCx Input Scan Select Low) ................ 172ADxPCFGL (ADCx Port Configuration Low)............. 173CLKDIV (Clock Divisor) ............................................ 122CORCON (Core Control) ...................................... 38, 90DEVID (Device ID).................................................... 179DEVREV (Device Revision)...................................... 179IEC0 (Interrupt Enable Control 0) ............................... 99IEC1 (Interrupt Enable Control 1) ............................. 101IEC2 (Interrupt Enable Control 2) ............................. 102IEC3 (Interrupt Enable Control 3) ............................. 102IEC4 (Interrupt Enable Control 4) ............................. 103IFS0 (Interrupt Flag Status 0) ..................................... 94IFS1 (Interrupt Flag Status 1) ..................................... 96IFS2 (Interrupt Flag Status 2) ..................................... 97IFS3 (Interrupt Flag Status 3) ..................................... 97IFS4 (Interrupt Flag Status 4) ..................................... 98INTCON1 (Interrupt Control 1).................................... 91INTCON2 (Interrupt Control 2).................................... 93INTTREG Interrupt Control and Status Register ...... 114IPC0 (Interrupt Priority Control 0) ............................. 104IPC1 (Interrupt Priority Control 1) ............................. 105IPC14 (Interrupt Priority Control 14) ......................... 110IPC15 (Interrupt Priority Control 15) ......................... 111IPC16 (Interrupt Priority Control 16) ......................... 112IPC19 (Interrupt Priority Control 19) ......................... 113


dsPIC33FJXXXGSXXX

IPC2 (Interrupt Priority Control 2) ............................. 106IPC3 (Interrupt Priority Control 3) ............................. 107IPC4 (Interrupt Priority Control 4) ............................. 108IPC5 (Interrupt Priority Control 5) ............................. 109IPC7 (Interrupt Priority Control 7) ............................. 109IPC9 (Interrupt Priority Control 9) ............................. 110NVMCON (Flash Memory Control) ............................. 75NVMKEY (Nonvolatile Memory Key) .......................... 76OSCCON (Oscillator Control) ................................... 120OSCTUN (FRC Oscillator Tuning) ............................ 123PMD1 (Peripheral Module Disable Control

Register 1) ........................................................ 127PMD2 (Peripheral Module Disable Control



Register 4) ........................................................ 129RCON (Reset Control) ................................................ 78RPINR0 (Peripheral Pin Select Input Register 0) ..... 136RPINR1 (Peripheral Pin Select Input Register 1) ..... 137RPINR11 (Peripheral Pin Select Input Register 11) . 141RPINR18 (Peripheral Pin Select Input Register 18) . 142RPINR21 (Peripheral Pin Select Input Register 21) . 143RPINR3 (Peripheral Pin Select Input Register 3) ..... 138RPINR7 (Peripheral Pin Select Input Register 7) ..... 139RPINR8 (Peripheral Pin Select Input Register 8) ..... 140RPOR0 (Peripheral Pin Select Output Register 0) ... 144RPOR1 (Peripheral Pin Select Output Register 1) ... 144RPOR2 (Peripheral Pin Select Output Register 2) ... 145RPOR3 (Peripheral Pin Select Output Register 3) ... 145RPOR4 (Peripheral Pin Select Output Register 4) ... 146RPOR5 (Peripheral Pin Select Output Register 5) ... 146RPOR6 (Peripheral Pin Select Output Register 6) ... 147RPOR7 (Peripheral Pin Select Output Register 7) ... 147SPIxCON1 (SPIx Control 1)...................................... 152SPIxCON2 (SPIx Control 2)...................................... 154SPIxSTAT (SPIx Status and Control) ....................... 151SR (CPU Status)................................................... 36, 90UxMODE (UARTx Mode).......................................... 157UxSTA (UARTx Status and Control)......................... 159

ResetIllegal Opcode ....................................................... 77, 83Trap Conflict................................................................ 83Uninitialized W Register.................................. 77, 83, 84

Reset Sequence ................................................................. 85Resets................................................................................. 77

SSerial Peripheral Interface (SPI) ....................................... 149Software Reset Instruction (SWR) ...................................... 83Software Simulator (MPLAB SIM)..................................... 193Software Stack Pointer, Frame Pointer

CALLL Stack Frame.................................................... 64Special Features of the CPU ............................................ 175SPI Module

SPI1 Register Map...................................................... 56Symbols Used in Opcode Descriptions............................. 184System Control

Register Map............................................................... 63

TTemperature and Voltage Specifications

AC............................................................................. 204Timing Characteristics

CLKO and I/O ........................................................... 207Timing Diagrams

10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)......................... 232

10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)....................................... 233

ADC Conversion Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) ....... 232

Brown-out Situations .................................................. 82External Clock .......................................................... 205I2Cx Bus Data (Master Mode) .................................. 226I2Cx Bus Data (Slave Mode) .................................... 228I2Cx Bus Start/Stop Bits (Master Mode)................... 226I2Cx Bus Start/Stop Bits (Slave Mode)..................... 228Input Capture (CAPx) ............................................... 211Motor Control PWM .................................................. 213Motor Control PWM Fault ......................................... 213OC/PWM .................................................................. 212Output Compare (OCx) ............................................ 212Reset, Watchdog Timer, Oscillator Start-up Timer

and Power-up Timer ......................................... 208Timer1, 2 and 3 External Clock ................................ 209

Timing RequirementsCLKO and I/O ........................................................... 207External Clock .......................................................... 205Input Capture............................................................ 211

Timing Specifications10-bit A/D Conversion Requirements ....................... 233I2Cx Bus Data Requirements (Master Mode)........... 227I2Cx Bus Data Requirements (Slave Mode)............. 229Motor Control PWM Requirements........................... 213Output Compare Requirements................................ 212PLL Clock ................................................................. 206Reset, Watchdog Timer, Oscillator Start-up Timer,

Power-up Timer and Brown-out Reset Requirements ................................................... 208

Simple OC/PWM Mode Requirements ..................... 212Timer1 External Clock Requirements....................... 209Timer2 External Clock Requirements....................... 210Timer3 External Clock Requirements....................... 210

UUART Module

UART1 Register Map ................................................. 56Universal Asynchronous Receiver Transmitter (UART) ... 155Using the RCON Status Bits............................................... 84

VVoltage Regulator (On-Chip) ............................................ 180

WWatchdog Time-out Reset (WDTR).................................... 83Watchdog Timer (WDT)............................................ 175, 181

Programming Considerations ................................... 181WWW Address ................................................................. 271WWW, On-Line Support ..................................................... 13


dsPIC33FJXXXGSXXX

NOTES:


dsPIC33FJXXXGSXXX

THE MICROCHIP WEB SITEMicrochip provides online support via our WWW site atwww.microchip.com. This web site is used as a meansto make files and information easily available tocustomers. Accessible by using your favorite Internetbrowser, the web site contains the foll owinginformation:

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CUSTOMER CHANGE NOTIFICATION SERVICEMicrochip’s customer notification service helps keepcustomers current on Microchip products. Subscriberswill receive e-mail notification whenever there arechanges, updates, revisions or errat a related to aspecified product family or development tool of interest.

To register, access the Microc hip web site atwww.microchip.com. Under “Support”, click on“Customer Change Notification” and follow theregistration instructions.

CUSTOMER SUPPORTUsers of Microchip products can receive assistancethrough several channels:

• Distributor or Representative• Local Sales Office• Field Application Engineer (FAE)• Technical Support• Development Systems Information Line

Customers should contact their di stributor,representative or fi eld application engineer (FAE) forsupport. Local sales offices are also available to helpcustomers. A listing of sales offices and locations isincluded in the back of this document.

Technical support is available through the web siteat: http://support.microchip.com








dsPIC33FJXXXGSXXX

READER RESPONSEIt is our intention to provide you w ith the best documentation possible to ensure successful use of your Microch ipproduct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which ourdocumentation can better serve you, please FAX your comments to the Technical Publications Manager at(480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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DS00000AdsPIC33FJXXXGSXXX

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?


dsPIC33FJXXXGSXXX

PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Architecture: 33 = 16-bit Digital Signal Controller

Flash Memory Family: FJ = Flash program memory, 3.3V

Product Group: MC1 = Motor Control family

Pin Count: 01 = 18-pin and 20-pin02 = 28-pin and 32-pin

Temperature Range: I = -40C to+85C (Industrial)E = -40C to+125C (Extended)

Package: P = Plastic Dual In-Line - 300 mil body (PDIP)SS = Plastic Shrink Small Outline -5.3 mm body (SSOP)SP = Skinny Plastic Dual In-Line - 300 mil body (SPDIP)SO = Plastic Small Outline - Wide, 300 mil body (SOIC)ML = Plastic Quad, No Lead Package - (28-pin) 6x6 mm body (QFN)TL = Thermal Leadless Array - (36-pin) 5x5 mm body (TLA)

Examples:a) dsPIC33FJ16MC102-E/SP:

Motor Control dsPIC33, 16 KB program memory, 28-pin, Extended temperature, SPDIP package.

Microchip TrademarkArchitectureFlash Memory FamilyProgram Memory Size (KB)Product GroupPin Count

Temperature RangePackagePattern

dsPIC 33 FJ 16 MC1 02 T E / SP - XXX

Tape and Reel Flag (if applicable)


dsPIC33FJXXXGSXXX

NOTES:


Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application me ets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT L IMITED TO ITS COND ITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use o f Microchipdevices in life supp ort and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all da mages, claims,suits, or e xpenses resulting f rom such use. No lic enses areconveyed, implicitly or ot herwise, under any Microchipintellectual property rights.

2011 Microchip Technology Inc. Data Sheet M

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN:

ock-up DS00000A-page 277

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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Worldwide Sales and Service

08/04/10

http://support.microchip.com


Documents

dsPIC33FJXXXGSXXX Data Sheet Mock-up - · PDF filedsPIC33FJXXXGSXXX Data Sheet Core: 16-bit Architecture (40 MIPS) • 64K/128K Flash • 8K/16K RAM ... • AN1279 – Offline UPS