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Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

I2C is a registered trademark of Philips Corporation

INT MASKREGISTERS

10-BIT ADC

VALUE AND

LIMITREGISTERS

LIMITCOMPARATORS

CONFIGURATIONREGISTERS

INTERRUPTSTATUS

REGISTERS

SERIAL BUSINTERFACE

ANALOGOUTPUT REGISTER

AND 8-BIT DAC

INPUTATTENUATORS

ANDANALOG

MULTIPLEXER

VID4/IRQ4

VID3/IRQ3

VID1/IRQ1

VID0/IRQ0

VID2/IRQ2

VCC

D1-

+VCCP2/D2-

+12VIN

D1+

+5V IN

+2.5VIN/D2+

VID 0 - 3 ANDFAN DIVISORREGISTERS

BANDGAPTEMPERATURE

SENSOR

NTEST_OUT/ADD

THERM

SDA

SCL

FAN1/AIN1

FAN2/AIN2

CI

GND

INT

NTEST_IN/AOUT

RESET

ADM1024

FAN SPEED

COUNTER

ADDRESSPOINTER

REGISTER

TEMPERATURECONFIGURATION

REGISTER

VID4 ANDDEVICE IDREGISTER

CHASSISINTRUSION

CLEAR REGISTER

2.5VBANDGAP

REFERENCE

CHANNELMODE

REGISTER

INTERRUPTMASKING

VCCP1

100kPULLUPS

VCC

VCC

VCC

VCC

100k

100k

100k

Preliminary Technical Data

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Supply Voltage, VCC 2.8 3.30 5.5 V

Supply Current, ICC 1.4 2.0 mA Interface Inactive, ADC Active1.0 mA ADC Inactive, DAC Active3 100 A Shutdown Mode

Internal Sensor Accuracy 3 oC -40 oC TA+125oC

2 oC TA=+25oC

Resolution 1 oC

External Diode Sensor Accuracy 5 oC -40 oC TA+125oC

3 oC +25OCResolution 1 oCRemote Sensor Source Current 60 90 130 A High Level

3.5 5.5 7.5 Low Level

Total Unadjusted Error, TUE 2 % Note 3Differential Non-Linearity, DNL 1 LSBPower Supply Sensitivity 1 %/VConversion Time (Analog Input or Int.Temp) 754.8 804.1 s +25oC TA+125

oC (Note 4)754.8 856.8 s -40oC TA+125

oC (Note 4)Conversion Time (External Temperature) 9.6 ms (Note 4)Input Resistance (+2.5V,+5V, +12V, VCCP1, VCCP2) 100 140 200 kInput Resistance (AIN1, AIN2) High Resistance

Output Voltage Range 0 2.5 VTotal Unadjusted Error, TUE 3 % IL= 2mAFull-Scale Error 1 3 %Zero Error 2 LSB No LoadDifferential Non-Linearity, DNL 1 LSB Monotonic by DesignIntegral Non-Linearity 1 LSBOutput Source Current 2 mAOutput Sink Current 1 mA

Accuracy 6 % +25oC TA+125

oC12 % -40oC TA+125

oCFull-Scale Count 255FAN1 and FAN2 Nominal Input RPM 8800 RPM Divisor = 1, Fan Count = 153

(Note 5) 4400 RPM Divisor = 2, Fan Count = 1532200 RPM Divisor = 3, Fan Count = 1531100 RPM Divisor = 4, Fan Count = 153

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The ADM1024 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit compari-son of various system parameters. Eight measurement inputs are provided, of which three are dedicated to monitoring +5V and +12Vpower supplies and the processor core voltage. The ADM1024 can monitor a fourth power-supply voltage by measuring its own V CC.One input (two pins) is dedicated to a remote temperature-sensing diode. Two further pins can be configured as inputs to monitor a+2.5V supply and a second processor core voltage, or as a second temperature sensing input.The remaining two inputs can be pro-grammed as general purpose analog inputs or as digital fan-speed measuring inputs.

Measured values can be read out via an I 2C-compatible serial System Management Bus, and values for limit comparisons can be pro-grammed in over the same serial bus. The high-speed successive-approximation ADC allows frequent sampling of all analog channelsto ensure a fast interrupt response to any out-of-limit measurement.

The ADM1024s 2.8V to 5.5V supply voltage range, low supply current, and I2C compatible interface make it ideal for a wide rangeof applications. These include hardware monitoring and protection applications in personal computers, electronic test equipment, andoffice electronics.

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Internal Clock Frequency 21.1 22.5 23.9 kHz +25oC TA+125oC

19.8 22.5 25.2 kHz -40oC TA+125oC

Output High Voltage, VOH 2.4 V IOUT= 3.0mA,

VCC= 2.85V - 3.60VOutput Low Voltage, VOL 0.4 V IOUT= -3.0mA,

VCC= 2.85V - 3.60V

Output Low Voltage, VOL 0.4 V IOUT= -3.0mA, VCC= 3.60VHigh Level Output Current, IOH 0.1 100 A VOUT= VCC

And CI Pulse Width 20 45 ms

Output Low Voltage, VOL 0.4 V IOUT= -3.0mA,

VCC= 2.85V - 3.60VHigh Level Output Current, IOH 0.1 100 A VOUT= VCC

SERIAL BUS DIGITAL INPUTS(SCL, SDA)

Input High Voltage, VIH 2.2 VInput Low Voltage, VIL 0.8 VHysteresis 500 mVGlitch Immunity 100 ns

Input High Voltage, VIH 2.2 V VCC= 2.85V - 5.5VInput Low Voltage, VIL 0.8 V VCC= 2.85V - 5.5V

Input High Voltage, VIH 2.2 V VCC= 2.85V - 5.5V

Input High Current, IIH -1 A VIN= VCCInput Low Current, IIL 1 A VIN= 0Input Capacitance, CIN 20 pF

Clock Frequency, fSCLK 400 kHz See Figure 1Glitch Immunity, tSW 50 ns See Figure 1Bus Free Time, tBUF 1.3 s See Figure 1Start Setup Time, tSU;STA 600 ns See Figure 1Start Hold Time, tHD;STA 600 ns See Figure 1SCL Low Time, tLOW 1.3 s See Figure 1SCL High Time, tHIGH 0.6 s See Figure 1

SCL, SDA Rise Time, tr 300 ns See Figure 1SCL, SDA Fall Time, tf 300 s See Figure 1Data Setup Time, tSU;DAT 100 ns See Figure 1Data Hold Time, tHD;DAT 900 ns See Figure 1

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Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . 6.5 VVoltage on 12V VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . +20VVoltage on AOUT,NTESTOUT/ADD . . . . . . . . . . . . . . . -0.3V to (VCC+0.3V)Voltage on Any Other Input or Output Pin . . . . -0.3V to 6.5VInput Current at any pin (Note 2) . . . . . . . . . . . . . . . . 5mAPackage Input Current (Note 2) . . . . . . . . . . . . . . . .20mAMaximum Junction Temperature (TJmax) . . . . . . . . 150 CStorage Temperature Range . . . . . . . . . . . 65C to +150CLead Temperature, Soldering

Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . +215CInfra-Red 15 sec . . . . . . . . . . . . . . . . . . . . . . . . . . +200CESD Rating all pins . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V

*Stresses above those listed under Absolute Maximum Ratings may causepermanent damage to the device. This is a stress rating only; functional operationof the device at these or any other conditions above those indicated in theoperational section of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.

24-Pin Small Outline Package:JA = 50C/Watt, JC = 10C/Watt

ADM1024ARU -40C to +125C 24-Pin TSSOP RU-24

Package

SDA

PROTOCOL

SCL

StartCondition

(S)

Bit 7MSB(A7)

Bit 6(A6)

tSU;STA tLOW tHIGH 1/fSCL

PROTOCOL

SCL

SDA

Bit 0LSB

(R/W)

Acknowledge(A)

StopCondition

(P)

tVD;DAT tSU;STO

tHD;STA tSU;DAT tHD;DAT

tr tftBUF

9

8

1

2

3

4

7

6

5

24

23

22

21

20

11

10

TOP VIEW(Not to Scale)

ADM1024

NTEST_OUT/ADD

VID3

VID2

VID1

VIDO

THERM

SDA

SCL

+2.5VIN/D2+

+VCCP1

VID4FAN1/AIN1

FAN2/AIN2

CI

GND VCCP2/D2-

12

16

19

18

17

15

14

13

VCC

INT

NTEST_IN/AOUT

RESET

+5VIN

+12VIN

D1+

D1-

1 NTEST_OUT/ADD Digital I/O. Dual Function pin. This is a three-state input that controls the twoLSBs of the Serial Bus Address. This pin functions as an output when doing aNAND Tree test.

2 Digital I/O. Dual Function pin. This pin functions as an interruptoutput for temperature interrupts only, or as an interrupt input for fan control.It has an on-chip 100kpullup resistor.

3 SDA Digital I/O. Serial Bus bidirectional Data. Open-drain output.

4 SCL Digital Input. Serial Bus Clock.

NOTES1 All voltages are measured with respect to GND, unless otherwise specified2 Typicals are at TA=25C and represent most likely parametric norm. Shutdown current typ is measured with VCC= 3.3V3 TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators, including an external series in-

put protection resistor value between zero and 1k.4 Total monitoring cycle time is nominally m x 748s + n x 9600s , where "m" is the number of channels configured as analog inputs, plus 2 for the internal VCC

measurement and internal temperature sensor, and "n" is the number of channels configured as external temperature channels (D1 and D2).5 The total fan count is based on 2 pulses per revolution of the fan tachometer output.6

ADD is a three-state input that may be pulled high, low or left open-circuit.7 Timing specifications are tested at logic levels of VIL = 0.8V for a falling edge and VIH = 2.2V for a rising edge.

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5 FAN1/AIN1 Programmable Analog/Digital Input. 0 to 2.5V analog input or digital (0 to VCC)amplitude fan tachometer input.

6 FAN2/AIN2 Programmable Analog/Digital Input. 0 to 2.5V analog input or digital (0 to VCC)

amplitude fan tachometer input.

7 CI Digital I/O. An active high input from an external latch which captures a ChassisIntrusion event. This line can go high without any clamping action regardless of thepowered state of the ADM1024. The ADM1024 provides an internal open drain onthis line, controlled by Bit 6 of Register 40H or Bit 7 of Register 46H, to provide aminimum 20ms pulse on this line, to reset the external Chassis Intrusion Latch.

8 GND System Ground.

9 VCC POWER (+2.8V to +5.5V). Typically powered from +3.3V power rail. Bypasswith the parallel combination of 10 F (electrolytic or tantalum) and 0.1 F (ceramic)bypass capacitors.

10 Digital Output. (open drain). The output is enabled when Bit 1 of

the Configuration Register is set to 1. The default state is disabled.It has an on-chip 100kpullup resistor.

11 NTEST_IN/AOUT Digital Input/Analog Output. An active-high input that enables NAND Tree modeboard-level connectivity testing. Refer to section on NAND Tree testing.Also functions as a programmable analog output when NAND Tree is not selected

12 Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 45 msminimum pulse width. Set using Bit 4 in Reg40H. Also acts as reset input whenpulled low (e.g. power-on reset). It has an on-chip 100kpullup resistor.

13 D1- Analog Input. Connected to cathode of 1st external temperature sensing diode.

14 D1+ Analog Input. Connected to anode of 1st external temperature sensing diode.

15 +12VIN Programmable Analog Input. Monitors +12 V supply

16 +5VIN Analog Input. Monitors +5 V supply.

17 VCCP2/D2- Programmable Analog Input. Monitors 2nd processor core voltage or cathode of 2ndexternal temperature sensing diode

18 +2.5VIN/D2+ Programmable Analog Input. Monitors 2.5V supply or anode of 2nd externaltemperature sensing diode

19 +VCCP1 Analog Input. Monitors 1st processor core voltage (0 to 3.6V).

20 VID4/IRQ4 Digital Input. Core Voltage ID readouts from the processor. This value is read intothe VID4 Status Register. Can also be re-configured as an interrupt input.It has an on-chip 100kpullup resistor.

21 VID3/IRQ3 Digital Input. Core Voltage ID readouts from the processor. This value is read into

the VID0-VID3 Status Register.Can also be re-configured as an interrupt input.It has an on-chip 100kpullup resistor.

22 VID2/IRQ2 Digital Input. Core Voltage ID readouts from the processor. This value is read intothe VID0-VID3 Status Register.Can also be re-configured as an interrupt input.It has an on-chip 100kpullup resistor.



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The ADM1024 is a complete system hardware monitor for mi-croprocessor-based systems. The device communicates withthe system via a serial System Management Bus. The serial buscontroller has a hardwired address line for device selection (pin

1), a serial data line for reading and writing addresses and data(pin 3), and an input line for the serial clock (pin 4). All con-trol and programming functions of the ADM1024 are per-formed over the serial bus.

Programmability of the measurement inputs makes theADM1024 extremely flexible and versatile. The device has a10 bit A to D converter, and 9 measurement input pins thatcan be configured in different ways.

Pins 5 and 6 can be programmed as general purpose analoginputs with a range of 0 to +2.5V, or as digital inputs tomonitor the speed of fans with digital tachometer outputs.

The fan inputs can be programmed to accommodate fanswith different speeds and different numbers of pulses perrevolution from their tacho outputs.

Pins 13 and 14 are dedicated temperature inputs and may beconnected to the cathode and anode of an external tempera-ture-sensing diode.

Pins 15, 16 and 19 are dedicated analog inputs with on-chipattenuators, configured to monitor +12V,+5V and the pro-cessor core voltage, respectively.

Pins 17 and 18 may be configured as analog inputs with on-chip attenuators to monitor a second processor core voltageand a +2.5V supply, or they may be configured as a tempera-ture input and connected to a second temperature-sensing di-

ode.The ADC also accepts input from an on-chip bandgap tem-perature sensor that monitors system ambient temperature.

Finally, the ADM1024 monitors the supply from which it ispowered, so there is no need for a separate +3.3V analog in-put, if the chip VCC is +3.3V. The range of this VCCmeasure-ment can be configured for either a +3.3V or +5V VCCby bit3 of the Channel Mode Register.

When the ADM1024 monitoring sequence is started, it cyclessequentially through the measurement of analog inputs andthe temperature sensor, while at the same time the fan speed

inputs are independantly monitored. Measured values fromthese inputs are stored in Value Registers. These can be readout over the serial bus, or can be compared with programmedlimits stored in the Limit Registers. The results of out of limitcomparisons are stored in the Interrupt Status Registers, andwill generate an interrupt on the line (pin 10).

Any or all of the Interrupt Status Bits can be masked by ap-propriate programming of the Interrupt Mask Register.

Five digital inputs (VID4 to VID0 - pins 20 to 24) read theprocessor Voltage ID code. These inputs can also be re-con-figured as interrupt inputs.

The VID pins have internal 100kpullup resistors.

A chassis intrusion input (pin 7) is provided to detectunauthorised tampering with the equipment.

A input/output (pin 12) is provided. Pulling this pinlow will reset all ADM1024 internal registers to default val-ues. The ADM1040 can also be programmed to give a low-going 45ms reset pulse at this pin.

The pin has an internal, 100kpullup resistor.

The ADM1024 contains an on-chip, 8-bit digital-to-analogconverter with an output range of zero to 2.5V (pin 11). Thisis typically used to implement a temperature-controlled fan bycontrolling the speed of a fan dependent upon the tempera-ture measured by the on-chip temperature sensor.

Testing of board level connectivity is simplified by providing aNAND tree test function. The AOUT (pin 11) also doublesas a NAND test input, while pin 1 doubles as a NAND treeoutput.

A brief description of the ADM1024's principal internal regis-ters is given below. More detailed information on the func-tion of each register is given in Tables 9 to 22, starting onpage 23.

Provide control and configuration.

Channel Mode Register:Stores the data for the operatingmodes of the input channels.

This register contains the address thatselects one of the other internal registers. When writing to theADM1024, the first byte of data is always a register address, whichis written to the Address Pointer Register.

Two registers to providestatus of each Interrupt event. These registers are also mir-rored at addresses 4Ch and 4Dh.

Allow masking of individualInterrupt sources.

The configuration ofthe temperature interrupt is controlled by the lower 3 bits ofthis register.

The status of the VID0 to VID4pins of the processor can be written to and read from theseregisters. Divisor values for fan-speed measurement are alsostored in this register.

The results of analog voltage in-puts, temperature and fan speed measurements are stored inthese registers, along with their limit values.

:The code controlling the analogoutput DAC is stored in this register.

: A signal latched on the ChassisIntrusion pin can be cleared by writing to this register.

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Control of the ADM1024 is carried out via the serial bus. TheADM1024 is connected to this bus as a slave device, underthe control of a master device, e.g. the PIIX4.

The ADM1024 has a 7-bit serial bus address. When the de-vice is powered up, it will do so with a default serial bus ad-

dress. The five MSB's of the address are set to 01011, the twoLSB's are determined by the logical states of pin1(NTESTOUT/ADD). This is a three-state input that can begrounded, connected to VCC or left open-circuit to give threedifferent addresses:

ADD Pin A1 A0

GND 1 0

No Connect 0 0

VCC 0 1

If ADD is left open-circuit the default address will be0101100.

The facility to make hardwired changes to A1 and A0 allowsthe user to avoid conflicts with other devices sharing the sameserial bus, for example if more than one ADM1024 is used in

a system.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a STARTcondition, defined as a high to low transition on the serialdata line SDA whilst the serial clock line SCL remainshigh. This indicates that an address/data stream will follow

All slave peripherals connected to the serial bus respond tothe START condition, and shift in the next 8 bits, consist-ing of a 7-bit address (MSB first) plus a R/bit, whichdetermines the direction of the data transfer, i.e. whetherdata will be written to or read from the slave device.

The peripheral whose address corresponds to the transmit-ted address responds by pulling the data line low duringthe low period before the ninth clock pulse, known as theAcknowledge Bit. All other devices on the bus now remainidle whilst the selected device waits for data to be readfrom or written to it. If the R/bit is a 0 then the masterwill write to the slave device. If the R/bit is a 1 the mas-ter will read from the slave device.

R/W0

SCL

SDA 1 0 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

ACK. BYADM1024

START BYMASTER

FRAME 1SERIAL BUS ADDRESS BYTE

FRAME 2ADDRESS POINTER REGISTER BYTE

1 9 1

ACK. BYADM1024

9

D7 D6 D5 D4 D3 D2 D1 D0

ACK. BYADM1024

STOP BYMASTER

FRAME 3DATA BYTE

1 9

SCL (CONTINUED)

SDA (CONTINUED)

R/W0

SCL

SDA 1 0 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

ACK. BYADM1024

STOP BYMASTER

START BYMASTER


FRAME 2ADDRESS POINTER REGISTER BYTE

1 9 1

ACK. BYADM1024

9

R/W0

SCL

SDA 1 0 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

NO ACK.BY MASTER

STOP BYMASTER

START BYMASTER


FRAME 2DATA BYTE FROM ADM1024

1 9 1

ACK. BYADM1024

9

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2. Data is sent over the serial bus in sequences of 9 clockpulses, 8 bits of data followed by an Acknowledge Bit fromthe slave device.Transitions on the data line must occurduring the low period of the clock signal and remain stableduring the high period, as a low to high transition when theclock is high may be interpreted as a STOP signal. Thenumber of data bytes that can be transmitted over the se-

rial bus in a single READ or WRITE operation is limitedonly by what the master and slave devices can handle.

3. When all data bytes have been read or written, stop condi-tions are established. In WRITE mode, the master will pullthe data line high during the 10th clock pulse to assert aSTOP condition. In READ mode, the master device willoverride the acknowldge bit by pulling the data line highduring the low period before the 9th clock pulse. This isknown as No Acknowledge. The master will then take thedata line low during the low period before the 10th clockpulse, then high during the 10th clock pulse to assert aSTOP condition.

Any number of bytes of data may be transferred over the se-

rial bus in one operation, but it is not possible to mix readand write in one operation, because the type of operation isdetermined at the beginning and cannot subsequently bechanged without starting a new operation.

In the case of the ADM1024, write operations contain eitherone or two bytes, and read operations contain one byte, andperform the following functions:

To write data to one of the device data registers or read datafrom it, the Address Pointer Register must be set so that thecorrect data register is addressed, then data can be writteninto that register or read from it. The first byte of a write op-eration always contains an address that is stored in the Ad-dress Pointer Register. If data is to be written to the device,

then the write operation contains a second data byte that iswritten to the register selected by the address pointer register.

This is illustrated in figure 2a. The device address is sent overthe bus followed by R/set to 0. This is followed by twodata bytes.The first data byte is the address of the internaldata register to be written to, which is stored in the AddressPointer Register. The second data byte is the data to be writ-ten to the internal data register.

When reading data from a register there are two possibilities:

1. If the ADM1024's Address Pointer Register value is un-known or not the desired value, it is first necessary to set itto the correct value before data can be read from the de-sired data register. This is done by performing a write to

the ADM1024 as before, but only the data byte containingthe register address is sent, as data is not to be written tothe register. This is shown in figure 2b.

A read operation is then performed consisting of the serial busaddress, R/bit set to 1, followed by the data byte read fromthe data register. This is shown in figure 2c.

2. If the Address Pointer Register is known to be already atthe desired address, data can be read from the correspond-ing data register without first writing to the AddressPointer Register, so figure 2b can be omitted.

Notes:

1. Although it is possible to read a data byte from a data reg-

ister without first writing to the Address Pointer Register, ifthe Address Pointer Register is already at the correct value,it is not possible to write data to a register without writingto the Address Pointer Register, because the first data byteof a write is always written to the Address Pointer Register.

2. In figures 2a to 2c, the serial bus address is shown as thedefault value 01011(A1)(A0), where A1 and A0 are set bythe three-state ADD pin.

The ADM1024 has nine external measurement pins, whichcan be configured to perform various functions by program-ming the Channel Mode Register.

Pins 13 and 14 are dedicated to temperature measurement,while pins 15, 16 and 19 are dedicated analog input channels.Their function is unaffected by the Channel Mode Register.

Pins 5 and 6 can be individually programmed as analog in-puts, or as digital fan speed measurement inputs, by program-ming bits 0 and 1 of the Channel Mode Register.

Pins 17 and 18 can be configured as analog inputs or as in-puts for an external temperature sensing diodes by program-ming bit 2 of the Channel Mode Register.

Bit 3 of the Channel Mode Register configures the internalVCCmeasurement range for either 3.3V or 5V.

Bits 4 to 6 of the Channel Mode Register enable or disablepins 22 to 24, when they are configured as interrupt inputs bysetting bit 7 of the Channel Mode Register. This function iscontrolled for pins 20 and 21 by bits 6 and 7 of Configurationregister 2.

Bit 7 of the Channel Mode Register allows the processor corevoltage ID bits (VID0 to VID4, pins 24 to 20) to be re-con-figured as interrupt inputs.

A truth Table for the Channel Mode Register is given inTable 1.

Channel Mode Controls FunctionRegister Bit Pin(s)

0 5 0 = FAN1, 1 = AIN1

1 6 0 = FAN2, 1 = AIN2

2 18, 19 0 = 2.5V, VCCP21 = D2-, D2+

3 Int. VCCMeas. 0 = 3.3V, 1 = 5V

4 24 0 = VID0, 1 = IRQ0

5 23 0 = VID1, 1 = IRQ1

6 22 0 = VID2, 1 = IRQ2

7 20 - 24 0 = VID0 to VID41 = interrupt inputs

Power-on Default = 0000 0000

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These inputs are multiplexed into the on-chip, successive ap-proximation, analog-to-digital converter. This has a resolu-tion of 8 bits. The basic input range is zero to +2.5V, which isthe input range of AIN1 and AIN2, but five of the inputshave built-in attenuators to allow measurement of 2.5V, 5V,12V and the processor core voltages V

CCP1and V

CCP2, without

any external components. To allow for the tolerance of thesesupply voltages, the A to D converter produces an output of3/4 full-scale (decimal 192) for the nominal input voltage,and so has adequate headroom to cope with overvoltages.Table 3 shows the input ranges of the analog inputs and out-put codes of the A to D converter.

When the ADC is running, it samples and converts an inputevery 748s, except for the external temperature(D1 and D2)inputs. These have special input signal conditioning and areaveraged over 16 conversions to reduce noise, and a measure-ment on one of these inputs takes nominally 9.6ms.

The internal structure for the analog inputs are shown in fig-ure 3. Each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order lowpassfilter which gives the input immunity to high frequency noise.

122.2k

22.7k 35pF

91.6k

55.2k 25pF

36.7k

111.2k 25pF

97.3k 50pF

42.7k

+2.5V

+VCCP1/VCCP2

MUX

AIN1 - AIN2

+12V

+5V

10pF

80k

AIN1 and AIN2 can easily be scaled to voltages other than2.5V. If the input voltage range is zero to some positive volt-

age, then all that is required is an input attenuator, as shownin figure 4.

R1

R2

VIN

AIN(1-2)

R1/R2 = (Vfs-2.5)/2.5

Negative and bipolar input ranges can be accommodated byusing a positive refrence voltage to offset the input voltagerange so that it is always positive.

To measure a negative input voltage, an attenuator can beused as shown in figure 5.

R1

R2

VINAIN(1-2)

+VOS

R1/R2 = |VFS-|/VOS

This is a simple and cheap solution, but the following pointshould be noted.

Since the input signal is offset but not inverted, the inputrange is transposed. An increase in the magnitude of the -12V supply (going more negative), will cause the input volt-age to fall and give a lower output code from the ADC.Conversely, a decrease in the magnitude of the -12V supplywill cause the ADC code to increase. The maximum negativevoltage corresponds to zero output from the ADC. Thismeans that the upper and lower limits will be transposed.

Bipolar input ranges can easily be accommodated. By makingR1 equal to R2 and VOS= +2.5V, the input range is 2.5V.other input ranges can be accommodated by adding a thirdresistor to set the positive full-scale input voltage.

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Input Voltage A/D Output

+12VIN +5VIN VCC(3.3V) VCC(5V) +2.5VIN +VCCP1/2 AIN(1/2) Decimal Binary

2.490 255 1111111

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R1

R2

R3

VIN

+VOS

AIN(1-2)

R1/R2 = |VFS-|/R2

(R3 has no effect as the input voltage at the device pin is zerowhen VIN= minus full-scale)

R1/R3 = (VFS+-2.5)/2.5

(R2 has no effect as the input voltage at the device pin is 2.5Vwhen VIN= plus full-scale).

Offset voltages other than +2.5V can be used, but the calcula-tion becomes more complicated.

The ADM1024 contains an on-chip bandgap temperaturesensor, whose output is digitised by the on-chip ADC. Thetemperature data is stored in the Temperature Value Register(address 27h) and the LSB from bits 6 and 7 of the Tempera-ture Configuration Register (address 4Bh). As both positive

and negative temperatures can be measured, the temperaturedata is stored in two's complement format, as shown in Table4, opposite. Theoretically, the temperature sensor and ADCcan measure temperatures from -128oC to +127oC with aresolution of 1oC, although temperatures below -40oC andabove +125oC are outside the operating temperature range ofthe device.

The ADM1024 can measure the temperature of two externaldiode sensors or diode-connected transistors, connected topins 13 and 14 or 17 and 18.

Pins 13 and 14 are a dedicated temperature input channel.

Pins 17 and 18 can be configured to measure a diode sensorby setting bit 2 of the Channel Mode Register to 1.

The forward voltage of a diode or diode-connected transistor,operated at a constant current, exhibits a negative tempera-ture coefficient of about -2mV/oC.Unfortunately, the absolutevalue of Vbe, varies from device to device, and individual cali-bration is equired to null this out, so the technique is unsuit-able for mass-production.

The technique used in the ADM1024 is to measure thechange in Vbewhen the device is operated at two differentcurrents.

This is given by:

Vbe= KT/q x ln(N)

where:

K is Boltzmanns constant

q is charge on the carrier

T is absolute temperature in Kelvins

N is ratio of the two currentsFigure 7 shows the input signal conditioning used to measurethe output of an external temperature sensor. This figureshows the external sensor as a substrate transistor, providedfor temperature monitoring on some microprocessors, but itcould equally well be a discrete transistor.

If a discrete transistor is used, the collector will not begrounded, and should be linked to the base. If a PNP transis-tor is used the base is connected to the D- input and theemitter to the D+ input. If an NPN transistor is used, theemitter is connected to the D- input and the base to the D+input.

Temperature Digital Output

-128 C 1000 0000

-125 C 1000 0011

-100 C 1001 1100

-75 C 1011 0101

-50 C 1100 1110

-25 C 1110 0111

0 C 0000 0000

+0.5 C 0000 0000

+10 C 0000 1010

+25 C 0001 1001

+50 C 0011 0010

+75 C 0100 1011

+100 C 0110 0100

+125 C 0111 1101

+127 C 0111 1111

To prevent ground noise interfering with the measurement,the more negative terminal of the sensor is not referenced toground, but is biased above ground by an internal diode atthe D- input. As the sensor is operating in a noisy environ-ment, C1 is provided as a noise filter. See the section on lay-out considerations for more information on C1.

To measure Vbe, the sensor is switched between operatingcurrents of I and N x I. The resulting waveform is passedthrough a 65kHz lowpass filter to remove noise, thence to achopper-stabilized amplifier that performs the functions ofamplification and rectification of the waveform to produce aDC voltage proportional to Vbe. This voltage is measured by

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the ADC to give a temperature output in 8-bit twos comple-ment format. To further reduce the effects of noise. digital fil-tering is performed by averaging the results of 16measurement cycles. An external temperature measurementtakes nominally 9.6ms.

The results of external temperature measurements are storedin 8 bit, twos-complement forma, as illustrated in Table 4.

Digital boards can be electrically noisy environments, andcare must be taken to protect the analog inputs from noise,particularly when measuring the very small voltages from a re-mote diode sensor. The following precautions should betaken:

1. Place the ADM1024 as close as possible to the remotesensing diode. Provided that the worst noise sources suchas clock generators, data/address buses and CRTs areavoided, this distance can be 4 to 8 inches.

2. Route the D+ and D- tracks close together, in parallel,

with grounded guard tracks on each side. Provide a groundplane under the tracks if possible.

3. Use wide tracks to minimize inductance and reduce noisepickup. 10 mil track minimum width and spacing is recom-mended.

GND

D+

D-

GND

10 mil.

10 mil.

10 mil.

10 mil.

10 mil.

10 mil.

10 mil.

4. Try to minimize the number of copper/solder joints, whichcan cause thermocouple effects. Where copper/solder jointsare used, make sure that they are in both the D+ and D-

path and at the same temperature.

Thermocouple effects should not be a major problem as1oC corresponds to about 240V, and thermocouple volt-ages are about 3V/oC of temperature difference. Unlessthere are two thermocouples with a big temperature differ-ential between them, thermocouple voltages should bemuch less than 200mV.

5. Place 0.1F bypass and 2200pF input filter capacitorsclose to the ADM1024.

6. If the distance to the remote sensor is more than 8 inches,the use of twisted pair cable is recommended. This willwork up to about 6 to 12 feet.

7. For really long distances (up to 100 feet) use shieldedtwisted pair such as Belden #8451 microphone cable. Con-nect the twisted pair to D+ and D- and the shield to GNDclose to the ADM1024. Leave the remote end of the shieldunconnected to avoid ground loops.

Because the measurement technique uses switched currentsources, excessive cable and/or filter capacitance can affect

the measurement. When using long cables, the filter capacitormay be reduced or removed.

Cable resistance can also introduce errors. 1 series resis-tance introduces about 0.5oC error.

Limit values for analog measurements are stored in the appro-priate limit registers. In the case of voltage measurements,high and low limits can be stored so that an interrupt requestwill be generated if the measured value goes above or belowacceptable values. In the case of temperature, a Hot Tem-perature or High Limit can be programmed, and a Hot Tem-perature Hysteresis or Low Limit, which will usually be some

degrees lower. This can be useful as it allows the system to beshut down when the hot limit is exceeded, and re-started au-tomatically when it has cooled down to a safe temperature.

D+

D-

REMOTESENSING

TRANSISTOR

LOWPASS FILTERfc= 65kHz

VDD

TO ADC

VOUT+

VOUT-

I N x I IBIAS

BIASDIODE

OPTIONAL CAPACITOR, UP TO3nF MAX. CAN BE ADDED TOIMPROVE HIGH FREQUENCYNOISE REJECTION IN NOISY

ENVIRONMENTS

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The monitoring cycle begins when a one is written to theStart Bit (bit 0), and a zero to the _Clear Bit (bit 3) ofthe Configuration Register. _Enable (Bit 1) should be setto one to enable the output. The ADC measures eachanalog input in turn, as each measurement is completed theresult is automatically stored in the appropriate value register.This "round-robin" monitoring cycle continues until it is dis-abled by writing a 0 to bit 0 of the Configuration Register.

As the ADC will normally be left to free-run in this manner,the time taken to monitor all the analog inputs will normallynot be of interest, as the most recently measured value of anyinput can be read out at any time.

For applications where the monitoring cycle time is impor-tant, it can be calculated as follows:

m x t1+ n x t2

where:

m is the number of inputs configured as analog inputs, plusthe internal VCC measurement and internal temperaturesensor.

t1 is the time taken for an analog input conversion, nominally748s

n is the number of inputs configured as external temperatureinputs

t2 is the time taken for a temperature conversion, nominally9.6ms.

This rapid sampling of the analog inputs ensures a quick re-sponse in the event of any input going out of limits, unlikeother monitoring chips that employ slower ADCs.

When a monitoring cycle is started, monitoring of the fanspeed inputs begins at the same time as monitoring of theanalog inputs. However, the two monitoring cycles are notsynchronised in any way The monitoring cycle time for thefan inputs is dependent on fan speed and is much slower thanfor the analog inputs. For more details see the section on"FAN SPEED MEASUREMENT".

Scaling of the analog inputs is performed on chip, so externalattenuators are normally not required. However, since thepower supply voltages will appear directly at the pins, its is ad-visable to add small external resistors in series with the sup-

ply traces to the chip to prevent damaging the traces or powersupplies should a accidental short such as a probe connecttwo power supplies together.

As the resistors will form part of the input attenuators, theywill affect the accuracy of the analog measurement if theirvalue is too high. The analog input channels are calibrated as-suming an external series resistor of 500, and the accuracywill remain within specification for any value from zero to1k, so a standard 510 resistor is suitable.

The worst such accident would be connecting -12V to +12V- a total of 24V difference, with the series resistors this woulddraw a maximum current of approx. 24mA.

The ADM1024 has a single analog output from a unsigned 8bit DAC which produces 0 - 2.5V. The analog output registerdefaults to FF during power-on reset, which produces maxi-mum fan speed.The analog output may be amplified andbuffered with external circuitry such as an op-amp and tran-sistor to provide fan speed control.

Suitable fan drive circuits are given in figures 10a to 10f.When using any of these circuits, the following points shouldbe noted:

1. All of these circuits will provide an output range from zeroto almost +12V, apart from figure 10a which loses thebase-emitter voltage drop of Q1 due to the emitter-fol-lower configuration.

2. To amplify the 2.5V range of the analog output up to12V, the gain of these circuits needs to be around 4.8.

3. Care must be taken when choosing the op-amp to ensurethat its input common-mode range and output voltageswing are suitable.

4. The op-amp may be powered from the +12V rail alone orfrom 12V. If it is powered from +12V then the inputcommon-mode range should include ground to accommo-date the minimum output voltage of the DAC, and theoutput voltage should swing below 0.6V to ensure that thetransistor can be turned fully off.

5. If the op-amp is powered from -12V then precautionssuch as a clamp diode to ground may be needed to pre-vent the base-emitter junction of the output transistor be-ing reverse-biased in the unlikely event that the output ofthe op-amp should swing negative for any reason.

6. In all these circuits, the output transistor must have anICMAXgreater than the maximum fan current, and be ca-

pable of dissipating power due to the voltage droppedacross it when the fan is not operating at full-speed.

7. If the fan motor produces a large back e.m.f whenswitched off, it may be necessary to add clamp diodes toprotect the output transistors in the event that the outputgoes from full-scale to zero very quickly.

The ADM1024 incorporates a fault tolerant fan control capa-bility that can override the setting of the analog output andforce it to maximum to give full fan speed in the event of acritical overtemperature problem, even if, for some reason, thishas not been handled by the system software.

There are four temperature set points that will force the ana-log output to FFh if any one of them is exceeded for three ormore consecutive measurements. Two of these limits are pro-grammable by the user and two are hardware limits intendedas "must not exceed" limits that cannot be changed.

The analog output will be forced to FFh if:

the temperature measured by the on-chip sensor exceeds thelimit programmed into register address 13h.

or

the temperature measured by either of the remote sensors ex-ceeds the limit programmed into address 14h.

or

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+12V

+

-

AOUT

R236k

R1

10k

Q12N2219A

1/4 LM324

+12V

+

-AOUT

R2

39k

R1

10k

R3

1k

R4

1k

Q1BD1362SA968

1/4 LM324

+12V

+

-AOUT

R2

39k

R3

100k

R1

10k

Q1

IRF9620

1/4 LM324

AOUT

+12V

R1

100kR2

100k

R3

3.9k

R4

1k

Q3IRF9620

Q1/Q2MBT3904

DUAL

AOUT

+12V

R2

100k

R3

39k

R4

10k

Q3IRF9620

-12V

R1

4.7k

Q1/Q2MBT3904

DUAL

AOUT

+12V

R1

100k

R2

100k

R3

3.9k

R4

1k

R5

100

Q3

BC5562N3906

Q4BD132TIP32A

Q1/Q2MBT3904

DUAL

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the temperature measured by the on-chip sensor exceeds70OC, which is hardware programmed into a read-only regis-ter at address 17h.

or

the temperature measured by either of the remote sensors ex-ceeds 85OC, which is hardware programmed into a read-only

register at address 18h.Once the hardware override of the analog output is triggered,it will only return to normal operation after three consecutivemeasurements that are 5 degrees lower than each of the abovelimits.

The analog output can also be forced to FFh by pulling thepin (pin 2) low.

The limits in registers 13h and 14h can be programmed bythe user. Obviously these limits should not exceed the hard-ware values in registers 17h and 18h, as they would have noeffect. The power-on default values of these registers are thesame as the two hardware registers, 70OC and 85OC respec-tively, so there is no need to program them if these limits are

acceptable.Once these registers have been programmed, or if the de-faults are acceptable, the values in these registers can belocked by writing a 1 to bits 1 and 2 of Configuration Register2 (address 4Ah). This prevents any unauthorised tamperingwith the limits. These lock bits can only be written to 1 andcan only be cleared by power-on reset or by taking the

pin low,, so registers 13h and 14h cannot be written toagain unless the device is powered off, then on.

Analog inputs will provide best accuracy when referred to aclean ground. A separate, low-impedance ground plane foranalog ground, which provides a ground point for the voltage

dividers and analog components, will provide best perfor-mance but is not mandatory.

The power supply bypass, the parallel combination of 10F(electrolytic or tantalum) and 0.1F (ceramic) bypass capaci-tors connected between pin 9 and ground, should also be lo-cated as close as possible to the ADM1024.

Pins 5 and 6 may be configured as analog inputs or fan speedinputs by programming bits 0 and 1 of the Channel ModeRegister. The power-on default for these bits is all zeroes,which makes pins 5 and 6 fan inputs.

Signal conditioning in the ADM1024 accommodates the slow

rise and fall times typical of fan tachometer outputs. Themaximum input signal range is 0 to VCC. In the event thatthese inputs are supplied from fan outputs which exceed 0 to6.5V, either resistive attenuation of the fan signal or diodeclamping must be included to keep inputs within an accept-able range.

Figures 11a to 11c show circuits for most common fan tachooutputs.

If the fan tacho output has a resistive pullup to VCCthen it can beconnected directly to the fan input, as shown in figure 11a.

+12V

FAN SPEEDCOUNTER

FAN1OR FAN2

PULLUP

4.7kTYP.

TACHOOUTPUT

VCC

If the fan output has a resistive pullup to +12V (or other volt-age greater than 6.5V) then the fan output can be clampedwith a zener diode, as shown in figure 11b. The zener voltageshould be chosen so that it is greater than VIHbut less than6.5V, allowing for the voltage tolerance of the zener. A valueof between 3V and 5V is suitable.

+12V

FAN SPEED

COUNTER

FAN1OR FAN2

TACHOOUTPUT

ZD1*ZENER

PULLUP

4.7kTYP.

*CHOOSE ZD1 VOLTAGE APPROX. 0.8 x VCC

VCC

If the fan has a strong pullup (less than 1k) to +12V, or atotem-pole output, then a series resistor can be added to limitthe zener current, as shown in figure 11c. Alternatively, a re-sistive attenuator may be used, as shown in figure 11d.

R1 and R2 should be chosen such that:

2V < VPULLUPx R2/(RPULLUP+ R1 + R2) < 5V

The fan inputs have an input reistance of nominally 160k toground, so this should be taken into account when calculatingresistor values.

With a pullup voltage of 12V and pullup resistor less than1k, suitable values for R1 and R2 would be 100kand47k.This will give a high input voltage of 3.83V.

+12V

FAN SPEEDCOUNTER

FAN1OR FAN2

PULLUP

TYP.

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+12V

FAN SPEEDCOUNTER

FAN1OR FAN2

TACHOOUTPUT

R1*

R2*

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Manufacturers of cooling fans with tachometer outputs arelisted below:

NMB Tech

9730 Independence Ave.

Chatsworth, California 91311

818-341-3355

818-341-8207

Model Frame Size Airflow

CFM

2408NL 2.36 in sq. X 0.79 in (60mm sq. X 20mm) 9-16

2410ML 2.36 in sq. X 0.98 in (60mm sq. X 25mm) 14-25

3108NL 3.15 in sq. X 0.79 in (80mm sq. X 20mm) 25-42

3110KL 3.15 in sq. X 0.98 in (80mm sq. X 25mm) 25-40

Mechatronis Inc.

P.O. Box 20

Mercer Island, WA 98040

800-453-4569

Models - Various sizes available with tach output option.

Sanyo Denki/Keymarc Electronics

2310 205th, Suite 101

Torrance, CA 90501

310-212-7724

Models - 109P Series

The Chassis Intrusion input is an active high input/open-drain output intended for detection and signalling ofunauthorised tampering with the system. An external circuitpowered from the system's CMOS backup battery is used todetect and latch a chassis intrusion event, whether the systemis powered up or not. Once a chassis intrusion has been de-tected and latched, the CI input will generate an interruptwhen the system is powered up

The actual detection of chassis intrusion is performed by anexternal circuit that will detect (for example), when the coverhas been removed. A wide variety of techniques may be used

for the detection, for example:- Microswitch that opens or closes when the cover is re

moved.

- Reed switch operated by magnet fixed to the cover

- Hall-effect switch operated by magnet fixed to thecover.

- Phototransistor that detects light when cover is removed.

The chassis intrusion interrupt will remain asserted until theexternal detection circuit is reset. This can be achieved bysetting bit 7 of the Chassis Intrusion Clear Register to one,which will cause the CI pin to be pulled low for at least20ms. This register bit is self-clearing

The chassis intrusion circuit should be designed so that it canbe reset by pulling its output low. A suitable chassis intrusioncircuit using a phototransistor is shown in figure 8. Light fall-ing on the phototransistor when the PC cover is removed willcause it to turn on and pull up the input of N1, thus settingthe latch N3/N4. After the cover is replaced, a low reset onthe CI output will pull down the input of N4, resetting the

latch.

3

4

5

2

6

7

1

12

11

10

13

9

8

14

+5V

CMOSBACKUPBATTERY

1N914 1N914

7CI

74HC132

470k

100k

10k

MRD901

The Chassis Intrusion input can also be used for other types ofalarm input. Figure 13b shows a temperature alarm circuit us-ing an AD22105 temperature switch sensor. This produces alow-going output when the preset temperature is exceeded, sothe output is inverted by Q1 to make it compatible with the CIinput. Q1 can by almost any small-signal NPN transistor, or aTTL or CMOS inverter gate may be used if one is available.See the AD22105 data sheet for information on selecting RSET.

VCC

RSET AD22105TEMP.

SENSOR1

2

7

3

67

CI

R110k

Q1

Note:The chassis intrusion input does not have a protectiveclamp diode to VCC, as this could pull down the chassis intru-sion latch and reset it when the ADM1024 was powered

down.

The Interrupt Structure of the ADM1024 is shown in Figure 14.As each measurement value is obtained and stored in the appro-priate value register, the value and the limits from the corre-sponding limit registers are fed to the high and low limitcomparators. The result of each comparison (1 = out of limit, 0= in limit) is routed to the corresponding bit input of the Inter-rupt Status Registers via a data demultiplexer, and used to setthat bit high or low as appropriate.

The Interrupt Mask Registers have bits corresponding to each

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of the Interrupt Status Register Bits. Setting an InterruptMask Bit high forces the corresponding Status Bit output low,whilst setting an Interrupt Mask Bit low allows the corre-sponding Status Bit to be asserted. After masking, the statusbits are all OR'd together to produce the output, whichwill pull low if any unmasked status bit goes high, i.e. whenany measured value goes out of limit. The ADM1024 also has

a dedicated output for temperature interrupts only, the input/output pin 2. The function of this is describedlater.

Theoutput is enabled when Bit 1 of Configuration Register1 (_Enable) is high, and Bit 3 (_Clear) is low.

The pin has an internal, 100kpullup resistor.

The processor voltage ID inputs VID0 to VID4 can bereconfigured as interrupt inputs by setting bit 7 of the Chan-nel Mode Register (address 16h). In this mode they operateas level-triggered interrupt inputs, with VID0/IRQ0 toVID2/IRQ2 being active low and VID3/IRQ3 andVID4/IRQ4 being active high. The individual interrupt inputscan be enabled or masked by setting or clearing bits 4 to 6 ofthe Channel Mode Register and bits 6 and 7 of ConfigurationRegister 2(address 4Ah). These interrupt inputs are notlatched in the ADM1024, so they do not require clearing asdo bits in the Status Registers. However, the external inter-rupt source should be cleared once the interrupt has been ser-viced, or the interrupt request will be re-asserted.

INTERRUPT

STATUS

REGISTER1

0

1

2

3

4

5

6

7

INT ENABLE INT_CLEAR

INT

DATA

DEMULTIPLEXER

HIGHAND

LOWL

IMIT

COMPARATORS

2.5V/EXT. TEMP2

VCCP1

VCC

+5V

INT. TEMP

EXT. TEMP1

FAN1/AIN1

FAN2/AIN2

HIGH LIMIT

LOW LIMIT

VALUEFROM VALUE

AND LIMITREGISTERS

1 = OUTOF LIMIT

MASKING DATAFROM BUS

STATUSBIT

MASKBIT

MASK GATING X 11

CHANNELMODE

REGISTER

VID0/IRQ0

VID1/IRQ1

VID2/IRQ2

VID3/IRQ3

VID4/IRQ4

VID0-V

ID4

REGISTERS

4

5

6

7

CONFIG.

REGISTER2

6

7

+12V

VCCP2

RESERVED

RESERVED

CITHERM

D1 FAULT

D2 FAULT

INTER

RUPT

STATUS

REGIS

TER2

0

1

2

3

4

5

6

7

16 MASK BITS

INTERRUPT MASKREGISTERS 1 AND 2

(SAME BIT ORDER ASSTATUS REGISTERS)

CONFIGURATIONREGISTER 1

THERM

THERMCLEAR THERM

HARDWARETEMP. ERROR H/W TEMP

ERRORLATCH

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Reading an Interrupt Status Register will output the contentsof the Register, then clear it. It will remain cleared until themonitoring cycle updates it, so the next read operation shouldnot be performed on the register until this has happened, or theresult will be invalid. The time taken for a complete monitoringcycle is mainly dependent on the time taken to measure the fanspeeds, as described earlier.

The output is cleared with the _Clear bit, which isBit 3 of the Configuration Register, without affecting thecontents of the Interrupt () Status Registers.

Whenever a bit in one of the Interrupt Status Registers is up-dated, the same bit is written to duplicate registers at addresses4Ch and 42h. These registers allow a second management sys-tem to access the status data without worrying about clearingthe data. The data in these registers is for reading only andhas no effect on the interrupt output.

The ADM1024 has two distinct methods of producing inter-rupts for out-of-limit temperature measurements from the in-ternal or external sensors. Temperature errors can generatean interrupt on the pin along with other interrupts, butthere is also a separate pin that generates an inter-rupt only for temperature errors.

Operation of the output for temperature interrupts is il-lustrated in figure 15. Assuming that the temperature startsoff within the programmed limits and that temperature inter-rupt sources are not masked, will go low if the tempera-ture measured by any of the internal or external sensorsexceeds the programmed high temperature limit for that sen-

sor, or the hardware limits in register 13h, 14h, 17h or 18h.

100oC

90oC

80oC

70oC

60oC

50oC

40oC

INT

Temp.*

*

*

*

*

*

ACPI CONTROL

METHODSCLEAR EVENT

*ACPI AND DEFAULT CONTROL METHODSADJUST TEMP. LIMIT VALUES

HIGH LIMIT

LOW LIMIT

Once the interrupt has been cleared, it will not be re-assertedeven if the temperature remains above the high limit(s). How-ever, will be re-asserted if:

a) the temperature falls below the low limit for the sensor

or

b) the high limit is/are re-programmed to a new value, andthe temperature then rises above the new high limit on the

next monitoring cycle

or

c) the pin is pulled low externally, which sets bit 5of Interrupt Status Register 1

or

d) An interrupt is generated by another source.Similarly, should the temperature measured by a sensor startoff within limits then fall below the low limit, will be as-serted. Once cleared, it will not be re-asserted unless:

a) the temperature rises above the high limit

or

b) the low limit is/are re-programmed, and the temperaturethen falls below the new low limit

or

c) the pin is pulled low externally, which sets bit 5of Interrupt Status Register 1

or

d) an interrupt is generated by another source.

The Thermal Management Input/Output () is a logicinput/output with an internal, 100kpullup resistor, that pro-vides a separate output for temperature interrupts only. It is en-abled by setting bit 2 of Configuration Register 1. The

output has two operating modes that can be pro-grammed by bit 3 of Configuration Register 2 (address 4Ah).With this bit set to the default value of 0, the THERM outputoperates in "Default" interrupt mode. With this bit set to 1, theTHERM output operates in "ACPI" mode.

Thermal interrupts can still be generated at the outputwhile is enabled, but if these are not required theycan be masked by writing a 1 to bit 0 of Configuration Regis-ter 2 (address 4Ah). The pin can also function as alogic input for an external sensor, for example a temperaturesensor such as the ADM22105 used in figure 13b. IfTHERM is taken low by an external source, the analog out-put will be forced to FFh to switch a controlled fan to maxi-mum speed. This also generates an output as describedpreviously.

In Default mode, the output operates like a thermo-stat with hysteresis. will go low and bit 5 of Inter-

rupt Status Register 2 will be set, if the temperarure measuredby any of the sensors exceeds the high limit programmed forthat sensor. It will remain asserted until reset by reading In-terrupt Status register 2, by setting bit 6 of ConfigurationRegister 1, or when the temperature falls below the low limitprogrammed for that sensor.

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THERM

TEMP.HIGH LIMIT

TEMP

PROGRAMMEDVALUE FFh

EXT.THERMINPUT

CLEARED BYREAD OR

THERM CLEAR

CLEARED BYTEMP. FALLING

BELOW LOW LIMIT

ANALOGOUTPUT

TEMP.LOW LIMIT

If is cleared by reading the status register, it will bere-asserted after the next temperature reading and compari-son if it remains above the high limit.

If is cleared by setting bit 6 of Configuration Regis-ter 1, it cannot be re-asserted until this bit is cleared.

will also be asserted if one of the hardware tempera-ture limits at addresses 13h, 14h, 17h or 18h is exceeded forthree cobsecutive measurements. When this happens, the ana-log output will be forced to FFh to boost a controlled coolingfan to full speed.

Reading Status Register 1 will not clear in this case,because errors caused by exceeding the hardware temperaturelimits are stored in a separate register that is not cleared byreading the status register. In this case, can only becleared by setting bit 0 of Configuration Register 2.

THERM will be cleared automatically if the temperature fallsat leaset 5 degrees below the limit for three consuctivemeausrements.

In ACPI mode, only responds to the hardware tem-perature limits at addresses 13h, 14h, 17h and 18h, not to thesoftware programmed limits.

THERM

HARDWARETRIP POINT

TEMP

5o

PROGRAMMEDVALUE FFh

EXT.THERMINPUT

FFh

ANALOGOUTPUT

will go low if either the internal or external hardwaretemperature limit is exceeded for three consecutive measure-ments. It will remain low until the temperature falls at least 5degrees below the limit for three consecutive measurements.While is low, the analog output will go to FFh toboost a controlled fan to full speed.

(pin 12) is an I/O pin that can function as an open-drain output, providing a low-going 20ms output pulse whenbit 4 of the Configuration Register is set to 1, provided the re-set function has first been enabled by setting bit 7 of InterruptMask Register #2 to 1. The bit is cleared automatically whenthe reset pulse is output. Pin 11 can also function as a

input by pulling this pin low to reset the internal regis-ters of the ADM1024 to default values. Only those registersthat have power on default values as listed in Table 6 are af-fected by this function. The DAC register, Value and LimitRegisters are not affected.

A NAND tree is provided in the ADM1024 for AutomatedTest Equipment (ATE) board level connectivity testing. Thedevice is placed into NAND Test Mode by powering up withpin 11 held high. This pin is sampled automatically afterpower-up and if it connected high, then the NAND test modeis invoked.

In NAND test mode, all digital inputs may be tested as illus-trated below. NTEST_OUT/ADD will become the NANDtree output pin. To perform a NAND tree test all pins in-cluded in the NAND tree should be driven high.

The structure of the NAND tree is shown in figure 17.

Each pin can be toggled and a resulting toggle can be ob-served on NTEST_OUT/ADD.

Allow for a typical propagation delay of 500 ns.

SCLFAN1FAN2VID0VID1VID2VID3VID4

RESET

NTESTOUT

SDA

Note: If any of the inputs shown in figure 19 are unused, theyshould not be connected direct to ground, but via a resistorsuch as 10k. This will allow the ATE (Automatic TestEquipment) to drive every input high so that the NAND treetest can be properly carried out.

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ter contents will not be affected.

Bit 4 of Configuration Register 1 causes a low-going 45ms(typ) pulse at the pin (pin 12).

Bit 6 of Configuration Register 1 is used to clear an interruptat the output when it is set to 1.

Bit 7 of Configuration Register 1 is used to start a Configura-tion Register Initialization when it is set to 1.

Bit 0 of Configuration Register 2 is used to mask temperatureinterrupts at theoutput when it is set to 1. The output is unaffected by this bit.

Bits 1 and 2 of Configuration Register 2 lock the valuesstored in the Local and Remote Fan Control Registers at ad-dresses 13h and 14h. The values in these registers can thennot be changed until a power-on reset is performed.

Bit 3 of Configuration Register 2 selects the inter-rupt mode. The default value of 0 selects one-time mode.Setting this bit to 1 selects ACPI mode.

The monitoring function (Analog inputs, temperature, andfan speeds) in the ADM1024 is started by writing to Configu-ration Register 1 and setting Start (Bit 0), high. TheINT_Enable (Bit 1) should be set to 1, and Clear (Bit3) set to 0 to enable interrupts. The enable bit (bit2) should be set to 1 and the Clear bit (bit 6)should be set to 0 to enabletemperature interrupts at the

pin. Apart from initially starting together, the ana-log measurements and fan speed measurements proceed inde-pendently, and are not synchronised in any way.

The time taken to complete the analog measurements de-

pends on how they are configured, as describedelsewhere.The time taken to complete the fan speed measure-ments depends on the fan speed and the number of tachooutput pulses per revolution.

Once the measurements have been completed, the results canbe read from the Value Registers at any time.

The ADM1024 can be placed in a low-power mode by settingbit 0 of the Configuration register to 0. This disables the in-ternal ADC. Full shutdown mode may then be achieved bysetting bit 0 of the Test Register to 1. This turns off the ana-log output and stops the monitoring cycle, if running, but it

does not affect the condition of any of the registers. The de-vice will return to its previous state when this bit is reset tozero.

When power is first applied, the ADM1024 performs apower on reset on several of its registers. Registers whosepower on values are not shown have power on conditions thatare indeterminate (this includes the Value and Limit Regis-ters). The ADC is inactive. In most applications, usually thefirst action after power on would be to write limits into theLimit Registers.

Power on reset clears or initializes the following registers (theinitialized values are shown in Table 8 on page 19/20):

- Configuration Registers #1 and #2

- Channel Mode Register

- Interrupt () Status Registers #1 and #2

- Interrupt () Status Mirror Registers #1 and #2

- Interrupt () Mask Register #1 and #2

- VID /Fan Divisor Register

- VID4 Register

- Chassis Intrusion Clear Register

- Test Register

- Analog Output Register

- Hardware Trip Registers

Configuration Register INITIALIZATION performs a simi-lar, but not identical, function to power on reset. The TestRegister and Analog Output register are not intialized.

Configuration Register INITIALIZATION is accomplished

by setting Bit 7 of the Configuration Register high. This Bitautomatically clears after being set.

Control of the ADM1024 is provided through two configura-tion registers. The ADC is stopped upon power up, and theINT_Clear signal is asserted, clearing the output. TheConfiguration Registers are used to start and stop theADM1024; enable or disable interrupt outputs and modes,and provides the initialization function described above.

Bit 0 of Configuration Register 1 controls the monitoringloop of the ADM1024. Setting Bit 0 low stops the monitoringloop and puts the ADM1024 into a low power mode thereby

reducing power consumption. Serial bus communication isstill possible with any register in the ADM1024 while in low-power mode. Setting Bit 0 high starts the monitoring loop.

Bit 1 of Configuration Register 1 enables or disables the Interrupt output. Setting Bit 1 high enables the output,setting bit 1 low disables the output.

Bit 2 of Configuration Register 1enables or disables the output. Setting Bit 1 high enables the output,setting bit 1 low disables the output.

Bit 3 of Configuration Register 1 is used to clear the in-terrupt output when set high. The ADM1024 monitoringfunction will stop until bit 3 is set low. Interrupt Status regis-

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Figure 18 shows a generic application circuit using theADM1024. The analog monitoring inputs are connected tothe power supplies including two processor core voltage in-puts. The VID inputs are connected to the processor VoltageID pins. There are two tacho inputs from fans, and the analogoutput is used to control the speed of a third fan. An opto-sensor for chassis intrusion detection is connected to the CIinput. Of course, in an actual application, every input andoutput may not be used, in which case unused analog anddigital inputs should be tied to analog or digital ground as ap-propriate.

D1+

D1-

TEMP.SENSING

TRANSISTOR

2N3904

+

3

4

5

2

6

7

1

12

11

10

13

9

8

14

+5V

CMOSBACKUPBATTERY

1N914

1N914

2

4

3

5

9

7

10

11

8

6

1

12

+

-

+12V

SDA

SCL

SERIAL BUS

+5V

+5V

+12V

INT TO PROCESSOR

RESET

+5V

14

15

19

16

17

18

20

21

23

24

22

13

+12VIN

+5VIN

+2.5VIN/D2+

+VCCP1

VID0/IRQ0

VID1/IRQ1

VID2/IRQ2

VID3/IRQ3

VID4/IRQ4

FROMV

ID

PINS

OFPROCESSOR

NTEST_OUT/ADD

THERM

CI

FAN1/AIN1

FAN2/AIN2

GNDD

VCC

INT

NTEST_IN/AOUT

510

510

510

510

74HC132

ADM1024

470k

100k

10k

10F 0.1F

82k

10k

OP-2952N2219A

MRD901

+VCCP2

91k

10k

VCC

THERM I/O TOOTHER CIRCUITS

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Bit Name R/W Description

7-0 Address Pointer Write Address of ADM1024 Registers. See the tables below for detail.

Power on Value (Binary Bit 7 - 0)

13h Internal Temp. = 70OC Cannot be written to a higher value. Can be writtenHardwareTrip Point to a lower value, but only if write once bit in

Config. Reg. 2 has not been set.

14h External Temp = 85OC Cannot be written to a higher value. Can be writtenHardware Trip Point to a lower value, but only if write once bit in .

Config. Reg. 2 has not been set.

15h Test Register 0000 0000 Setting Bit 0 of this register to 1 selects shutdown

mode. Caution: Do Not write to any other bits inthis register

16h Channel Mode Register 0000 0000 This register configures the input channels andconfigures VID0 to VID as processor voltage IDor interrupt inputs

17h Internal Temp = 70OC Read Only. Cannot be changed.Hardware Trip Point

18h External Temp = 85OC Read-Only. Cannot be changed.Hardware Trip Point

19h Programmed Value of Analog Output 1111 1111

1Ah AIN1 Low Limit Indeterminate

1Bh AIN2 Low Limit Indeterminate

20h +2.5V Measured Value/EXT Temp2 Indeterminate Read Only

21h +VCCP1 Measured Value Indeterminate Read Only

22h VCC Measured Value Indeterminate Read Only

23h +5V Value Indeterminate Read Only. Stores +5V input reading

24h +12V Measured Value Indeterminate Read Only.

25h VCCP2Measured Value Indeterminate Read Only

26h Ext. Temp1Value Indeterminate Read Only. Stores the measurement from adiode sensor connected to pins 13 and 14

27h Internal Temp Value Indeterminate Read Only. This register is used to store 8 bits of the internal temperature reading.

28h FAN1/AIN1 Value Indeterminate Read Only. Stores FAN1 or AIN1 readingdepending on the configuration of pin 5

29h FAN2/AIN1 Value Indeterminate Read Only. Stores FAN2 or AIN2 readingdepending on the configuration of pin 6

2Ah Reserved Indeterminate

2Bh +2.5V/Ext. Temp2 High Limit Indeterminate Stores high limit for +2.5V input or, intemperature mode, this register stores the highlimit for a diode sensor connected to pins 17 and 18

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Power on Value

(Binary Bit 7 - 0)

2Ch +2.5V/Ext. Temp2 Low Limit Indeterminate Stores high limit for +2.5V input or, intemperature mode, this register stores the lowlimit for a diode sensor connected to pins 17and 18

2Dh +VCCP1 High Limit Indeterminate Stores VCCP1 high limit

2Eh +VCCP1 Low Limit Indeterminate

2Fh VCCHigh Limit Indeterminate

30h VCC Low Limit Indeterminate

31h +5V High Limit Indeterminate Stores high limit for 5V

32h +5V Low Limit Indeterminate Stores low limit for 5V input

33h +12V High Limit Indeterminate

34h +12V Low Limit Indeterminate35h VCCP2 High Limit Indeterminate

36h VCCP2 Low Limit Indeterminate

37h Ext.Temp1. High Limit Indeterminate Stores high limit for a diode sensor connected topins 13 and 14

38h Ext Temp1. Low Limit Indeterminate Stores low limit for a diode sensor connected topins 13 and 14

39h Internal Temp. High Limit Indeterminate Stores the high limit for the internaltemperature reading.

3Ah Internal Temp. Low Limit Indeterminate Stores the low limit for the internal temperature

reading.3Bh AIN1/FAN1 High Limit Indeterminate Stores high limit for AIN1 or FAN1, depending on

the configuration of pin 5

3Ch AIN2/FAN2 High Limit Indeterminate Stores high limit for AIN2 or FAN2, depending onthe configuration of pin 6

3Dh Reserved Indeterminate

3Eh Company ID number 0100 0001 This location will contain the companyidentification number (Read Only)

3Fh Revision number 0001 nnnn Last four bits of this location will contain therevision number of the part. (Read Only)

40h Configuration Register 1 0000 1000 See Table 11

41h Interrupt Status Register 1 0000 0000 See Table 13

42h Interrupt Status Register 2 0000 0000 See Table 14

43h Mask Register 1 0000 0000 See Table 15

44h Mask Register 2 0000 0000 See Table 16

46h Chassis Intrusion Clear Register 0000 0000 See Table 17

47h VID 0-3/Fan Divisor Register 0101 (VID3-VID0) See Table 18

49h VID 4 Register 1000 000(VID 4) See Table 19

4Ah Configuration Register 2 0000 0000 See Table 20

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Power on Value

(Binary Bit 7 - 0)

4Ch Interrupt Status Register Mirror No. 1 0000 0000 See Table 21.

4Dh Interrupt Status Register Mirror No.2 0000 0000 SeeTable 22.

0 FAN1/AIN1 R/W Clearing this bit to 0 configures pin 5 as FAN1 input. Setting this bit to 1 configures pin 5as AIN1. Power-on default = 0.

1 FAN2/AIN2 R/W Clearing this bit to 0 configures pin 6 as FAN2 input. Setting this bit to 1 configures pin 6as AIN2. Power-on default = 0.

2 2.5V,VCCP/D2 R/W Clearing this bit to 0 configures pins 18 and 19 to measure +2.5V and VCCP2. Setting thisbit to 1 configures pins 18 and 19 as an input for a second remote temperature-sensing diode.Power-on default = 0

3 Int VCC R/W Clearing this bit to 0 sets the measurement range for the internal VCC

measurement to 3.3V.Setting this bit to 1 sets the internal VCC measurement range to 5V. Power-on default = 0

4 IRQ0 EN R/W Setting this bit to 1 enables pin 24 as an active high interrupt input, providedpins 20 to 24have been configured as interrupts by setting bit 7 of the Channel Mode Register.Power-on default = 0



7 VID/IRQ R/W Clearing this bit to 0 configures pins 20 to 24 as processor voltage ID inputs. Setting this bit

to 1 configures pins 20 to 24 as interrupt inputs. Power-on default = 0.

0 START R/W Logic 1 enables startup of ADM1024, logic 0 places it in standby mode. Caution: Theoutputs of the Interrupt pins will not be cleared if the user writes a zero to this location after

an interrupt has occurred (see INT Clear bit). At startup, limit checking functions andscanning begins. Note, all high and low limits should be set into the ADM1024 prior toturning on this bit. (Powerup default=0)

1 Enable R/W Logic 1 enables the output. 1=Enabled 0=Disabled (Powerup Default = 0)

2 R/W 0 = disabled

Enable 1 = enabled

3 INT_Clear R/W During Interrupt Service Routine (ISR) this bit is asserted logic 1 to clearoutputwithout affecting the contents of the Interrupt Status Register. The device will stopmonitoring. It will resume upon clearing of this bit. (Powerup default=1)

4 R/W Setting this bit generates a low-going 45ms reset pulse at pin 12. This bit is self-clearing andpower-up default is 0

5 Reserved R/W Default = 0

6 CLR R/W A one clears the output without changing the Status Register contents.

7 Initialization R/W Logic 1 restores powerup default values to the Configuration register, Interrupt statusregisters, Interrupt Mask Registers, Fan Divisor Register, and the TemperatureConfiguration Register. This bit automatically clears itself since the power on default is zero.

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BIT Name R/W Description

0 +2.5V/Ext. Temp2 Error Read Only A one indicates that a High or Low limit has been exceeded

1 VCCP1 Error Read Only A one indicates that a High or Low limit has been exceeded

2 VCCError Read Only A one indicates that a High or Low limit has been exceeded3 +5V Error Read Only A one indicates that a High or Low limit has been exceeded

4 Int. Temp Error Read Only A one indicates that a temperature interrupt has been set, orthat a High or Low limit has been exceeded .

5 Ext. Temp1 Error Read Only A one indicates that a temperature interrupt has been set, orthat a High or Low limit has been exceeded

6 FAN1/AIN1 Error Read Only A one indicates that a High or Low limit has been exceeded.



0 +12V Error Read Only A one indicates a High or Low limit has been exceeded,

1 VCCP2 Error Read Only A one indicates a High or Low limit has been exceeded

2 Reserved Read Only Undefined


4 Chassis Error Read Only A one indicates Chassis Intrusion has gone high.

5 Interrupt Read Only Indicates thatpin has been pulled low by an externalsource

6 D1 Fault Read Only Short or open-circuit sensor diode D1


Note:Anytime the STATUS Register is read out, the conditions (i.e. Register) that are read are automatically reset. In the caseof the channel priority indication, if two or more channels were out of limits, then another indication would automati-cally be generated if it was not handled during the ISR.

In the Mask Register, the errant voltage interrupt may be disabled, until the operator has time to clear the errant condi-tion or set the limit higher/lower.


0 +2.5V/Ext. Temp2 Read/Write A one disables the corresponding interrupt status bit for interrupt.

1 +VCCP1 Read/Write A one disables the corresponding interrupt status bit for interrupt.

2 VCC Read/Write A one disables the corresponding interrupt status bit for interrupt.

3 +5V Read/Write A one disables the corresponding interrupt status bit for interrupt.

4 Int. Temp Read/Write A one disables the corresponding interrupt status bit for interrupt.

5 Ext. Temp1 Read/Write A one disables the corresponding interrupt status bit for interrupt.

6 FAN1/AIN1 Read/Write A one disables the corresponding interrupt status bit for interrupt.

7 FAN2/AIN2 Read/Write A one disables the corresponding interrupt status bit for interrupt.

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0 +12V Read/Write A one disables the corresponding interrupt status bit for interrupt

1 VCCP2 Read/Write A one disables the corresponding interrupt status bit for interrupt

2 Reserved Read/Write Power up default set to Low.3 Reserved Read/Write Power up default set to Low.

4 CI Read/Write A one disables the corresponding interrupt status bit for interrupt.

5 (input) Read/Write A one disables the corresponding interrupt status bit for interrupt

6 D1 Fault Read/Write A one disables the corresponding interrupt status bit for interrupt

7 D2 Fault Read/Write A one disables the corresponding interrupt status bit for interrupt

0-6 Reserved Read Only Undefined , always reads as 00h

7 Chassis Int. Clear. Read/Write A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin.The register bit clears itself after the pulse has been output.

0-3 VID Read The VID[3:0] inputs from processor core power supplies to indicate the operatingvoltage (e.g. 1.3V to 3.5V)

4-5 FAN1 Divisor Read/Write Sets counter prescaler for fan1 speed measurement = 00 - divide by 1 = 01 - divide by 2

= 10 - divide by 4 = 11 - divide by 8.

6-7 FAN2 Divisor Read/Write Sets counter prescaler for fan 2 speed measurement = 00 - divide by 1 = 01 - divide by 2 = 10 - divide by 4 = 11 - divide by 8

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0 VID 4 Read Only VID 4 Input from Pentium

1-7 Reserved Read Only Undfined, always reads as 1000 000(VID4)

0 Thermal Read / Write Setting this bit masks the thermal interrupts for theoutput ONLY. TheMask output will still be generated, regardless of the setting of this bit.

1 Ambient Temp Read/Write Writing a one to this bit will lock in the values set into the ambientFan Control Once temperature automatic fan control register 13h. This register wil l not be ableRegisterWrite to be written again until a power on reset is performed.

Once Bit

2 Remote Temp Read/Write Writing a one to this bit will lock in the values set into the remoteFan Control Once temperature automatic fan control register 14h. This register will not be able

Register Write to be written again until a power on reset is performed.

Once Bit

3 Read/Write If this bit is 0 theoutput operates in default mode.Interrupt Mode If this bit is 1, the output operates in ACPI mode.

4,5 Reserved Read Only Reserved

6 IRQ3 EN Read/Write Setting this bit to 1 enables pin 21 as an active high interrupt input, providedpins 20 to 24 have been configured as interrupts by setting bit 7 of theChannel Mode Register. Power-on default = 0.

7 IRQ4 EN Read/Write Setting this bit to 1 enables pin 20 as an active high interrupt input, providedpins 20 to 24 have been configured as interrupts by setting bit 7 of theChannel Mode Register. Power-on default = 0.

Bit Name Read/Write Description

0 2.5V/Ext. Temp2 Err. Read Only A one indicates that a High or Low limit has been exceeded

1 VCCP1Error Read Only A one indicates that a High or Low limit has been exceeded

2 VCCError Read Only A one indicates that a High or Low limit has been exceeded

3 +5V Error Read Only A one indicates that a High or Low limit has been exceeded

4 Int. Temp Error Read Only A one indicates that a temperature interrupt has been set, or that a High orLow limit has been exceeded .

5 Ext. Temp1 Error Read Only A one indicates that a temperature interrupt has been set, or that a High or

Low limit has been exceeded



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Bit Name Read/Write Description

0 +12V Error Read Only A one indicates a High or Low limit has been exceeded,

1 VCCP2Error Read Only A one indicates a High or Low limit has been exceeded



4 Chassis Error Read Only A one indicates Chassis Intrusion has gone high.

5 Interrupt Read Only Indicates that pin has been pulled low by an externalsource



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Dimensions shown in inches and (mm).

24 13

121

0.311 (7.90)

0.303 (7.70)

PIN 1

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

BSC

0.0433

(1.10)

MA X

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)80

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Dsa 0060135