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STOCKHOLMOBSERVATORY
HERSCHEL SPIRE
DRCU InstrumentSimulator
Date : 2003-02-10Issue : 1.0 Page : 1 / 28
File: simulator.doc
DRCU Instrument Simulator
Hardware Software User Manual
Draft 1.0 Stockholm Observatory
H-G Florén Göran Olofsson [email protected] [email protected]
ICU Polska sp. z o.o.Świętojańska 75/481-389 Gdynia
Tel: +48 58 621 7920Fax: +48 58 661 6726
e-mail: [email protected]
STOCKHOLMOBSERVATORY
HERSCHEL SPIRE
DRCU InstrumentSimulator
Date : 2003-02-10Issue : 1.0 Page : 2 / 28
File: simulator.doc
Table of contents
1 .Hardware1.1 General PCI board description1.2.1Parts & References to drawings1.2.3 Fast channels receivers (HSII)1.2.4 Slow channels’ transmitters1.2.5 Internal registers address decoder1.2.6 Interrupt mask1.2.7 Clock 20 MHz dividers1.2.8 500 us interrupt1.2.9 FIFO control signal generation1.2.10 FIFO busy signals generator1.2.11 Fast channel selection signal (H4)1.2.12 Transmission direction selection for RS485 driversbus Hold description1.2.13 Add-on bus Hold description1.2.14 Reset1.2.15 PCI interface description1.3 Connectors and pin functions1.4.1 Computer Controlled Power Consumption Simulator1.4.2 Example
2.Software 2.1 Interaction of Driver - and Application-software2.2 Driver software.2.3 Application software2.4 Transmitter:2.5 User Manual2.5.1 Installation:2.5.2 Graphical User Interface (DRCU simulator)2.5.3 How to use and modify the Database2.5.4 Receiver IF2.5.5Test Examples(Current implementation)2.6.1 Log Files2.6.2 LogFileReader2.7Commanding The Power consumption Load Simulator2.8.Network connection2.9.1How to modify application software2.9.2 How to define new simulation functions2.9.3 Current Implementation /How To Define New Actions Upon Incoming Request2.9.4 Commanding Example2.10 Trouble Shooting
3 Testing 3.1 System tests3.2 Logic Analyser Displays
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File: simulator.doc
4 AppendixA1 Building BlocksA2 PCI/IFA3 XILINX overviewA4 XILINX Transmit MainA5 XILINX Transmitter FastChannelA6 Transmitter IRQ MaskA7 Transmitter PhaseA8 Transmitter Slow Channel Input PA9 Transmitter Slow ChannelInput A10 Transmitter Slow Channel OutputA11 Receiver MainA12 Receiver Fast ChannelA13 Receiver IRQ MaskA14 Receiver PhaseA15 Receiver Slow Channel InputA16 Receiver Slow Channel OutputA17 In and Out drawingsA18 Cables Pin AssignmentA19 Cable I/FA20 TerminatorsA21 RS 422 definition ADM 485A29 Power Consumption Simulator circuit layout
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DRCU InstrumentSimulator
Date : 2003-02-10Issue : 1.0 Page : 4 / 28
File: simulator.doc
1 Hardware
1.1 General PCI board descriptionMain parts
PCI MATCHMAKER CARDS59200 0106 A027
AMCCwww.amcc.com/
XILINX SPARTANXCS30FPGAhttp://www.xilinx.com/
MemorySN74ACT7882-20FN2048*18Clocked FIFO[TexasInstrumentwww.ti.com]
ADM 485EIA RS-485 StandardAnalog Devices
Appendix A17-A25
20 MHzClock
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File: simulator.doc
1.2.1 Building Blocks
PCI XILINX IN OUT
The detailed logical description of the blocks could be found in appendix (A)
PCI A2 XILINX A3-A15IN and OUT A17
Xilinx XCS30TQ144 contains all the digital parts of Hermes transmitter and receiver boards besides the PCIinterface which is based on AMCC S5920Q Matchmaker IC. Design of both transmitter and receiver is describedbelow.
1.2.2 Parts & References to drawings
1. The receiver can be divided into the following functional blocks:
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File: simulator.doc
A detailed logic layout could be found in the Appendix. (1-16)-use the search function in the appendix sectionto locate the ( )- parts and if needed the zoom function if needed.
fast channels receivers ( H1 .. H3 ) slow channels transmitters ( T1 .. T3 ) slow channels receivers ( R1 .. R3 ) internal registers address decoder ( L8, I56 ) interrupt mask register ( U1, I25, I26, I57 ) 20 MHz clock dividers 500 us interrupt generator ( U3, I150, I151 ) FIFO control signals generation ( I88, I89, I90 ) FIFO busy signals generation ( I142, I143, I144 ) fast channel selection circuit ( H4 ) RS485 direction definition ( I83 ) Add-On bus Hold ( I75 ) Reset
An external 20 MHz creates a basic clock for all receiver parts. Transmission CLKOUT 312,5 kHz, LED 1,5 Hzare generated by dividing 20 MHz. It is distributed by one of BUFGP lines to guarantee small delays. PTADR,DXFR and 1 MHz CLKIN from transmitter are also distributed using BUFGP lines. PTWR, CLKOUT, RD1 andCLKIN are distributed using secondary BUFGS buffers.
1.2.3 Fast channels receivers (HSII)
Serial channel input data are converted to a word in L14 module. Consecutive word bits are registered on risingedge of 1 MHz clock while frame FR is active. Parallel data are latched in L16 by a rising edge of 20MHz clockwhen LATCH_EN is active. LATCH_EN is generated by I162, I163, I550 and is active for half of CLKH periodafter FR goes low. The word received is written to FIFO by signals generated in I471, I487, I488 and I490. Writebegins when both LATCH_FULL and channel selection Q are high. WRITE signal is generated and fed to I488. IfAdd-On bus is free ( DXFR and PTATN are high) WAIT is generated forcing third state on S5920 outputs. On thenext 20MHz cykle FIFO write enable (WEN) is generated. The next 20 MHZ clock generates CLR that resets thecircuit. Simultaneously WAIT opens L15 buffer and the data received are presented on P[15:0] bus. Fast channelreceiver can generate three interrupts IRQ1, IRQ2, IRQ3. IRQ1 is generated on FR transition from high to low,IRQ2 on break between frames longer than 1 CLKH period, IRQ3 on FIFO’s AF ( almost full ) transistion from 1to 0. The interrupts are cleared by CLR_IRQ generated by I132 from DXFR, PTWR, EN (Add-On write to agiven fast channel).
1.2.4 Slow channels’ transmitters
After 32 bit word is written to a slow channel CLK_EN is generated and the data are latched in L16.Simultaneously START is generated starting 32 CLKL periods long FR frame. I163 register synchronises CLKLto START and additionally generates RDY, that together with FR defines the moment when data are written(LOAD) to shift registers module L17. L10 modul generates CLR after 32 CLKL periods are counted. CLR clearsFR. The word written to L17 is transmitted through SER serial output starting from MSB. When FR goes low Iinterrupt is generated. This interrupt is cleared by the appropriate channel read operation (CLR_IRQ from I160 ).
Change from 0 to 1 on S serial input results in FR changing from 0 to 1 and starts L11 counter counting 32 CLKLcycles. Simultaneously CLKL pulses write word bits to L10 shift register. The word is then presented onDO[31:0] bus. After 32 CLKL pulses I147 register resets (FR=0). Falling FR edge is detected in I141, I142registers and CLK_EN is generated. CLK_EN enables word write to L12. Rising CLK_EN produces LATCH_ENand I interrupt. I interrupt is cleared by write to appropriate slow channel (CLR_IRQ from I144). The wordreceived is presented on P[31:0] bus when the appropriate channel is selected (EN).
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File: simulator.doc
1.2.5 Internal registers address decoder
Address from Add-On bus is transmitted to BUSIN[31:0] and latched in L8 module by rising edge of PTADR. Itis then transmitted over A[3:0] to I56 address decoder.
1.2.6 Interrupt mask
Interrupts generated by the modules are connected to internal bus DQ[15:0] transmitting them to U1. Module U1contains 16 registers (L10) where a present interrupt mask is stored. There are also 16 AND gates masking theinterrupts for which a mask bit is equal to 0. The result is presented on O[15:0]. The interrupt mask can bechanged by writing a new value to IRQ_MASK address. After reset the mask has a value of 0x00. O[15:0] bus isbuffered by L4 buffer. L4 is opened when read of interrupt vector occured. All the interrupt lines are also addedby I26, I57 and I25 to create ADDINT.
1.2.7 Clock 20 MHz dividers
20 MHz external clock (generated by quartz oscillator installed on Hermes) is divided by 64 with a duty factor of50% (L7) to produce 312,5 kHz clock. This signal is then buffered by BUFGS (for fast propagation in Xilinx) andcreates receivers CLKOUT (being the transmission clock for slow channels). CLKOUT is divided by 200000 inL2 with a duty factor of 50% and provides approx. 1.5 Hz signal to control on board LED.
1.2.8 500 us interrupt
CLKIN (1MHz fast channel transmission clock coming from transmitter) is divided by 500 in U3 with a dutyfactor of 1/500. It is then synchronised by I151 and fed to line 15 of DO[15:0] bus. 500 us interrupt is cleared byAdd-On write to INT_TICK address.
1.2.9 FIFO control signals generation
FIFOs’ read signals REN1, REN2, REN3 are generated by I88, I89, I90 when Add-On read from H1, H2 or H3address occurs.
1.2.10 FIFO busy signals generation
When a 16 bit value is read from FIFO there are OR1, OR2 or OR3 signals presented on Add-On bits 16, 17 and18 respectively. They are used to confirm that the value read is valid.
1.2.11 Fast channel selection signal (H4)
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Date : 2003-02-10Issue : 1.0 Page : 8 / 28
File: simulator.doc
It is used to select three fast channels in a cycle one after the other to assure conflict free received data writing toone of FIFOs. Every of Q1, Q2, Q3 is active for 3 uS.
1.2.12 Transmission direction selection for RS485 drivers
Logical 1 is fed from I85 gate to pin P75 of Xilinx. It is defining the level on RS485 drivers (ADM485) directionpin [M1].
1.2.13 Add-On bus Hold
WAIT signals from fast channels are added by I75 and fed to Xilinx pin P4, which in turn is connected to WAITinput of S5920. Active WAIT sets S5920 in high impedance state. The bus can be then used by Xilinx – FIFOtransfers.1.2.14 Reset
A standard STARTUP module from Xilinx library is used. S5920 SYSRES (program reset) pin is connected toSTARTUP GSR input through P116 pin.
1.2.15 PCI interface description
PCI interface is based on AMCC S5920Q PCI Matchmaker IC. Its detailed description is available from AMCC.
S5920Q is working in active mode. It has a standard connection with the PCI bus. Its operation is defined byconfiguration record written to 24C02 I2C EEPROM. This configuration record is uploaded by S5920Qautomatically upon its power up. This record contains information about resources (I/O region and IRQ number)used by the board and the board descriptor.1.3 Connectors and pin functions
Appendix p17 Pin Out CablesAppendix -p18 Cables I/F drawingsAppendix p19 Terminators
1.4.1 Computer Controlled Power Consumption Simulator
Users Guide
Computer Controlled Power Supply Load (CCPSL Appendix p29) is a variable PS load that can be used tosimulate changes in power consumption for 28 V power supply. It works in the range from 0.84 W up to 120 W.
RS232
LED
Load
Fuse F 6.3A
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Date : 2003-02-10Issue : 1.0 Page : 9 / 28
File: simulator.doc
CCPSL front case
The front of CCPSL case is shown above. There are two DEMA9 connectors marked „Load” (DEMA9P) and“RS232” (DEMA9S), fuse holder and LED on the it. The power supply output should be connected to “Load” input with positive voltage connected to pins 2 and 7 andground connected to pins 4 and 8. There is fast 6.3A fuse installed in serial with “Load” input to protect the loadagainst overcurrent in case of failure.CCPSL acts as a regulated current load. The current value is set by a controlling computer through RS232 (serial)interface. The interface is optoisolated and requires small amount of power from the computer. The supply voltageis taken from RTS line which must be active for the interface to operate correctly (+12V). It is therefore necessaryto set flow control for the designated serial port to RTS/CTS.Transmission parameters are set to 2400 bauds, 8 data bits, no parity control and one stop bit (2400, 8, N, 1).All the internal CCPSL electronics is supplied from “Load” input. Therefore there is always certain minimalcurrent taken from the PS under test. This current is equal to 30 mA.To set a given current value the user has to send two bytes to CCPSL:X – current value0x21 (ASCII code of “!”)
The maximum current value tha can be set is adjusted to 4 250 mA. If we add 4 250 mA and a constant supplyingcurrent of 30 mA we will have the maximum current that can be set equal to 4 280 mA which gives a maximumpower of 119.84 W for voltage of 28V.A single bit weight is equal to 16.60 mA (0.465 W). The minimum current of 30 mA gives a minimum load of0.84 W.
1.4.2 Example:To set power to 45 W user has to send:
(45 W – 0.84 W)/0.465 W = 95 (0x5F)
User can also read the real current and voltage values by sending 0x3F (ASCII “?”) to CCPSL. CCPSL willanswer with two bytes representing voltage and currentX, YTo calculate voltage and current the following equations should be used:U [V] = X * 0.129 + 0.45I[A] = Y / 60 + 0.03Example:The answer 0xDA 0x5C means 28.6 V and 1.56 A.
The LED mounted above RS232 connector signals current consumption rangesgreen – I =0orange – 0 < I < 3 Ared – I > 3 A
RS232 cable is “one to one” (i.e. pin 1 connected to pin 1 and so on) DEMA9P to DEMA9S. However only fourlines (TxD, RxD, RTS and GND) are used.
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File: simulator.doc
2 Software
2.1Interaction of Driver Software and Application program.
The programming logic is divided between the application programme and the driver.The driver manage very fast response independent of the operating system drawback. The applicationsoftware provides a GUI for interactive operation. The division of tasks between the two levels are asfollows
The application software generates simulation data. TrefreshedIf all settings are done (defined by a series of set comabout a trigger command to initiate transfer-“RunCIThe driver and application share some information tcontaining information about block size, number of bstart transfer command allowing the driver to start sThe start command will then activate a driver responhaving to enter the application software New blocks asimulation loop as the transfer progresses.
2.2 Driver software.
Development tools: Visual c++ (Microsoft) http://w
Application softwareOS Windows NT /2000
Simulation LoopsBorland C++ builder
Driver Logic
GET
StatusBufferACK
32-bit GET ECHO inc ACK
Command word
GetBuffers32-bitresponseword
SET
SetBuffersDataBlocks
Fast ChannelBlock transfer0-2
Common memory1.Length2.Number Of Blocks3.TimeGap4. RunCID
he data in the driver is constantly
mands) the driver has informationD”.
hrough a common memorylocks, time gap between blocks andending se with the current settings withoutre shifted to the driver from the
ww.microsoft.com
32-bit SET ECHO inc. ACK
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DRCU InstrumentSimulator
Date : 2003-02-10Issue : 1.0 Page : 11 / 28
File: simulator.doc
Driver Studio 2.0 and SoftICE DriverStudi(Compuware Corporation)(http://www.microway.com.au/catalog/listcpp_addons.htm )
---------------------------------
Driver start-up
The board driver (hermes.sys) is loaded during Windows NT startup. This driver is uploading the Xilinxdefinition file (defining its internal structure) using S5920Q mailbox MD0 and MD1 bits.
After the Xilinx definition file is uploaded, S5920Q communicates with registers created in Xilinx structureusing 32 bit data DQ bus and control signals ADCLK, DXFR#, PTATN#, PTADR#, PTWR and IRQ#. Thecommunication between S5920Q and Xilinx XCS30 does not use any wait states.
-----------------------------------------------------------------------------------------------------
2.3 Application software
Development tools: Borland C++ Builder.5.0 and Paradox Database
The Application software is referred to as transmitter and receiver. The transmitter is the simulator (DRCU) and the receiver (DPU) making it possible to testsetup.
The application programme is developed and executed in the Windows environment. Thisallows a Graphical User Interface and the possibility to link to a desktop database (Paradox)
In the application programme (transmitter) the simulation functions will be implemented Theapplication software is linked to the database containing all set and get commands. Thedatabase is used as a storage area for parameters to be used by the application programme.
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File: simulator.doc
2.4 Transmitter:
Main units in application software(detailed listing in appendix)
Form1 Main Window
BitFunc Unit containing some simple bit conversion function Driver Open the DriverFunction Place To Define New Simulation Functions (Data for fast channels will be generated here)LogFiles Log File storageRequest Incoming requests that the simulator should react onSettings of transfer specificsTransmit Main wrapper file for application executionForm2 & Unit2 Database handeling
UpdateF Transfer to Driver Buffer of Fast Channel response data DeviceIoControl(Drv, CHANGE_FAST, pb, len, NULL, 0, &u, NULL); // send it !
UpdateS Transfer to Driver of Slow Channel Response data.DeviceIoControl(Form1->Drv->hDrv, WRITE_SLOW, &LS_Par, sizeof(LS_Par), NULL, 0, &i, NULL);//sendit !
Only Demo and test modes will not be used (currently not active)----------UpDataDisplay A Thread to display detector data (will not be used )Form3 & Unit3 Display of Detector readout.
The project also contains a file Common.h that serve as a link between application and driver.
Common.h Link between application and driver.
#ifndef __Common__#define __Common__
#include "Typedef.h"#define HermesVer "Hermes 3.3"
#define LOAD_XILINX 0x00222000#define RESET_XILINX 0x00222004#define CREATE_HOOK 0x00222008#define READ_SLOW 0x0022200C#define WRITE_SLOW 0x00222010#define CHANGE_FAST 0x00222014#define FLUSH_FIFO 0x00222018#define READ_LOG 0x0022201C
// CCAA TIII IIII IIII PPPP PPPP PPPP PPPP --- drv -> appl// GGSS xIII IIII IIII PPPP PPPP PPPP PPPP --- appl -> drv
// CC - channel number// SS - acknowledge bits for SET command// GG - acknowledge bits for GET command// PPPP PPPP PPPP PPPP - parameter
#define GET_MASK 0xC0000000#define SET_MASK 0x30000000#define PAR_MASK 0x0000FFFF#define CHN_ID(p) ((UCHAR)(((p)&GET_MASK) >> 30))
Format DefinitionNote that the twoFirst bits GG areused internally toDefineAck bitsFor get commands
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#define ACK_ID(p) ((UCHAR)(((p)&SET_MASK) >> 28))#define CMD_ID(p) ((USHORT)(((p)&0x0FFF0000) >> 16))#define CMD_NR(p) ((USHORT)(((p)&0x07FF0000) >> 16))#define CMD_SG(p) ((UCHAR)(((p)&0x08000000) ? 0x01 : 0x00))#define PAR_ID(p) ((USHORT)((p)&PAR_MASK))
#define CH 3// number of channels
#define MIN_LEN 5 // min frame length#define MAX_FN 16
// max number of functions for one channel#define MAX_DAT 1023of words in single block#define MAX_LS 2048of SET/GET parameters#define MAX_REQ 200 // max size queue of requests#define MAX_BLK 200 // max size queue of blocks
typedef struct _BLOCK // single block
USHORT Length;// number of data words
USHORT Data[MAX_DAT]; // one extra wo BLOCK;// Frame ID - stored in Data[0]// Time words and CRC stored in Data table (various positions)
typedef struct _FAST_O // application --> driver
USHORT Channel; // which channelUSHORT Loop; // loop mode activeUSHORT BlkNum; // number of blocks
USHORT RunCid; // command "start block transfer"
BLOCK Block;// block
FAST_O;
typedef struct _FAST_I // application <-- driver
USHORT Channel; // which channelBLOCK Block;
// block FAST_I;
typedef struct _LS_PAR // parameters for slow channels
ULONG Data[CH][MAX_LS]; // mixed ACKs/PARAM words LS_PAR;
typedef struct _LS_ONE // GET CMD for channels
USHORT Channel; // which channelUSHORT Idx; // index of ACK/PARAM wordULONG Param; // mixed ACK/PARAM word
LS_ONE;
typedef struct _CHANGE // single transaction for slow ch
Range definitions
// max number
// max number
format
rd for CRC
to change
annel
FAST ODefiniti
+ Block
n
BlockDefinitioUTon
struct
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File: simulator.doc
ULONG In;// incomming word
ULONG Out;// outgoing word
LONGLONG Stamp;// time stamp
CHANGE;
#endif // __Common__
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2.5 User Manual
-----------------------------------------------------------------------------------2.5.1 Installation:
A. The driver Hermes.sys should be put c:\ winNT\system32 \driversB. Folder TransmittPhase3 2002-12-09 contains source files and the (Hermes.reg i double clickon it to registrer file).C: Create a directory “C:\LogFiles” D Paradox Database Engine should be installed.E. Reboot computerF. Start Transmitter (Start Receiver)
2.5.2 Graphical User Interface (DRCU simulator)
Transmitter Gra
The different modin the comboboxIf you want to tes
Predefined Modes couldbe changedfrom keyboard orby set commands **
Hermes.regHermes.sys
RUN CIDSim FunctionDefined in Function
ReceivedCommandsStatus Box
Block Length
Continuously Transfer
phical User Interface
es could be defined in the graphical I/F. es the settings will change block size etc ft a certain combination enter values manu
Unit
Hex Or Dec Input
StatusInformationCurrent Status
TimeGap [ms]
Number ofBlocks
If you select the predefined modesor that specific channel.ally and click TransferSettings to
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File: simulator.doc
file.(you should always finish with this update if you do changes in the boxes. It is alsopossible to change the “modes” by sending the appropriate command and parametercombination (see receiver side instruction below)
The sim function selector references the definitions in the function unit (how to redefinefunction see section xxxx)
The received command box will show if there is a set =s command or get=g comand. If thecommand is the same as in the RUN CID box it is also considered a RUN =R command.(the start command known to the driver that will start transfer.
2.5.3 How to use and modify the Database.
The set parameters are send to the simulator there they are stored and displayed If the Set command has a corresponding Get command it is also stored in the databaselinked to that channel number. It’s possible to manually replace values in the database. If a getcommand parameter is redefined and the Update Buffer is clicked (or close window ) the next incoming request for a get value will contain that modified value.This makes it easy to fill the Get buffers with desired test values.
If a set including parameter value is sent to the simulator the corresponding get value(if any ) will be stored in the database. The set command will also initiate an update buffercommand transferring the values to the driver buffer. It will therefore respond on driver level(=fast response) on a Get command
Edit the database.It’s possible to remove a record press Ctrl+Delete. To insert a record press insert and enter the command value in either Hex or Integer. Use theHex-Int conversion button to make sure that values are defined both as Hex and Int. Youshould also make sure that the co_value and ack field contains some appropriatevalues.(numbers) The ack field defines the status of the commanded word default ack fordefined words=0 (ACK1=1 (unknown) ,ACK=2(Forbidden),Ack=3[S/S time word]The othercolumns are for future use and currently not linked to the simulation loops.
UpdateBuffers(Closingwindowwill dothe same)
Individ. ACK_1 columnvalues can be definedfor Get and Set values.
If value not defined in DBsimulator returns 01
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File: si
2.5.4“Receiver” I/F (DPU) software used for testing the “simulator side”
Com
1 2 3 4
2.6.1LogfilIn HertransmIf Tran
„HHM„HHM„HHM
Command Number
Make sure the same is selected on both si
Hex orDecimal
Parameter
Channel To Send On0-2
mulator.doc
manding the simulator:
.Select channel 0,1,2 Enter command number . Enter parameter value Press Send Now
Log Fileses are stored in directory c:\LogFiles Remenber to clear that directory if disk-space become crucial.mes phase 3 software the driver and „Transmit.exe” were modified. All the data received or sent byitter are written to files.smitter program is started it creates in the (c:\LogFiles) four files with the following names:
MSSs.log” - a common file for all slow channels,MSSf0.log” - file for channel 0,MSSf1.log” - file for channel 1,
cheksumdes
Display
Demo features
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„HHMMSSf2.log” - file for channel 2.
where HH is the current hour, MM minutes, SS seconds.
1. Slow channelsThe following changes were implemented in the driver and transmitter application to log the data:
- added „DeviceIoControl” function named READ_LOG,- write to a file was added to receiving thread („Request”).
READ_LOG function operates similarly to READ_SLOW function that was already used inprevious versions of software. There is however a small difference between the two functions.In READ_SLOW a queue of single words was read. In READ_LOG a queue of CHANGEstructures defined in „common.h” is read. Every structure consisits of the following fields:- ULONG In - a request received from „Receiver.exe”- ULONG Out - an answer sent to „Receiver.exe”- LONGLONG Stamp - „time stamp” (FILETIME structure)
All the structures read are written one after the other to „HHMMSSs.log” file.
The size of file is equal to:
Size = number of words received * sizeof(CHANGE) = number of words received * 16
2. Fast channelsBlocks of data to be sent are additionally stored in COPY_F structure (defined in „UpdateF.h”)in every thread preparing data for fast channels („UpdateF”). The COPY_F structure iscomplemented with time stamp. The structure consists of:
- LONGLONG Stamp - time stamp (FILETIME structure)- FAST_O Data - data block (variable length!)
CHANGE_FAST function was modified. Now the driver informs the application that a givenblock of data was used i.e. transmitted through a fast channel. If it happens, its copy is writtento an appropriate „HHMMSSf?.log” file.
For every transmission the length of a file is increased per::Size = number_of_blocks_sent * (number_of_data_in_the_block + 11) * 2
RemarksYou may use FileTimeToSystemTime (Windows SDK) function to use time stamp.After „LOG” checkbox is pressed present *.log files are closed and new ones are created.Data are written to files by unsynchronised threads and the data may be corrupted if youuse the „LOG” checkbox during the active fast channel transmission.
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File: simulator.doc
2.6.2 Log file ReaderA preliminary file reader is available to view contents Developed in C++ builder.
2.7Commanding The Power consumption Load Simulator
We have constructed simple commanding I/F based on C++ builder and Asynch professional(www.turbopower.com) plug in software is used for the serial communication. It could be integrated with theapplication programme.
2.8.Network connection We have tested to operate the simulator remotely. For that purpose we used Remote Admin(see http://www.famatech.com/). Other commercially available software should also work. In standardnetworks.
2.9.1How to modify application software
Open C++ Builder project fileOpen the Function Unit
Locate void FuncInit()
Load eitherAll blocksOr a certainnumber ofblocks fromBEOF
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File: simulator.doc
void FuncInit()
UCHAR i, j;
randomize();for(i=0; i<CH; i++)
for(j=0; j<MAX_FN; j++)
Form1->Set.pFnHS[i][j] = NULL;Form1->Set.pFnLS[i][j] = NULL;
// Assign functions Form1->Set.pFnHS[0][0] = D0;
Form1->Set.pFnHS[0][1] = D1;Form1->Set.pFnHS[0][2] = Time_F2;…..
Form1->Set.pFnHS[1][0] = T0;Form1->Set.pFnHS[1][1] = Time_F1;…..
Form1->Set.pFnHS[2][0] = Specctro_Array_F;Form1->Set.pFnHS[2][1] = Time_F2;Form1->Set.pFnHS[2][2] = Crazy_F;……
2.9.2 How to define new simulation functions
void D0(BLOCK *pb)
USHORT *pd = &pb->Data[0];USHORT n = pb->Length - MIN_LEN; // Length, Frame ID, TmrTaSYSTEMTIME tm;
GetSystemTime(&tm); int index = Form1->ComboBox3->ItemIndex; *pd++ =FrameId(index); int i=0; while(n--) *pd++ = (int)(1000*(1+sin(0.002*M_PI*Form1->mirror_pos))); *pd++ = tm.wSecond; // TmrTag1 *pd = tm.wMilliseconds; // TmrTag2
2.9.3 Current Implementation /How To Define New Actions Upon Incoming Requvoid __fastcall Request::OnSetRcv(UCHAR Ch, USHORT Cmd, USHORT Par)
switch(Ch)case 0: // Set commands 0-2047switch(Cmd)
Sim Function
Variable Event Ch
Channel NoFunc No
Channel 0
Function DefinitionSelected inComboBoxSimFunction(GUI)
g1, TmrTag2, CRC
ests
from separate Timer Threadanging the position (t )
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Date : 2003-02-10Issue : 1.0 Page : 21 / 28
File: simulator.doc
case 0: Form1->div1=Par;break;case 1: Form1->Set_Frame_Rate(Par);break;case 41: /// Mode Change //// ...543210int p = getbits(Par,4,5);//position 4//Form1->Edit1->Text=IntToStr(p);Form1->ComboBox3->ItemIndex=Par;Form1->ComboBox3Change(this);break;case 42: int p = getbits(Par,7,8);// Number of Blocks// If zero continouslyif(p==0)Form1->CheckBox01->Checked=true; else Form1->SetNumber_of_Blocks(p); break;case 43:
if((Form1->CheckBox01->Checked==true)&&(Par==0))Form1->CheckBox01->Checked=false;break; //end switch
if(Form2->Table2->Locate("CID_DEC",Cmd,Opts)) SET_CH0(Cmd,Par);/// Display Settings & Simulator actions/// Display_Values(Par,Cmd);/// Define -- GETif(Form2->Table1->Locate("CID_DEC",Cmd+2048,Opts)) //Form2->Table1->Edit();Form2->Table1->FieldByName("C0_VALUE"Form2->Table1->Post(); // Table1 = get channel 0
break;
case 1:
switch(Cmd)
// case 1: Form1->ChangeTimeGap(Par); break;
case 73: // Set_Trajectory_Mode
Form1->ComboBox5->ItemIndex=Par;
if(Par==2)
//Load sawtoooth function// SawTooth// Load_MCU//Form1->StopMCU(Par);
Form1->ComboBox5->Font->Color=clGreen;Form1->SetTransferFuncMCU(4);Form1->Timer2->Enabled=true; //start timer
// Par
//Form1->StopMCU(Par); // SetTelemetryPacket break;
Chann
Sending these specifcommands + param
0 Hex=01 Hex=142 Hex=2A43 Hex=2B
)->AsInteger = Par;
el 1
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Date : 2003-02-10Issue : 1.0 Page : 22 / 28
File: simulator.doc
case 198: // Set_Trajectory_Mode
if(Par==0)Form1->ComboBox6->ItemIndex=0;Form1->Timer4->Enabled=false; // Par
if(Par==2)Form1->ComboBox6->ItemIndex=1;Form2->Table4->Locate("CID_DEC",195,Opts); //double y0= Form2->Table4->FieldByName("C0_VALUE")->AsFloat;
Form2->Table4->Locate("CID_DEC",196,Opts); //double y1= Form2->Table4->FieldByName("C0_VALUE")->AsFloat;
Form2->Table4->Locate("CID_DEC",197,Opts); //Form1->Timer4->Interval= (int)(Form2->Table4->FieldByName("C0_VALUE")->AsFloat/2);
Form1->ch_y_sto=y1-y0;Form1->ch_x_sto=0;
Form1->Timer4->Enabled=true; // Par
break;
case 448:////////////////////if(Par==0)Form1->CheckBox11->Checked=false; //Stop TelemetryForm1->ComboBox1->Font->Color=clRed;Form1->ComboBox1->ItemIndex=0;else
Form1->ComboBox1->Font->Color=clGreen;Form2->Table4->Locate("CID_DEC",69,Opts); //SetTrajEndPosForm1->MCU_setTrajEndPos=Form2->Table4->FieldByName("C0_VALUE")->AsFloat;Form2->Table4->Locate("CID_DEC",70,Opts); //SetTrajStartPosForm1->MCU_setTrajStartPos=Form2->Table4->FieldByName("C0_VALUE")->AsFloat;Form2->Table4->Locate("CID_DEC",71,Opts); //Set_Scan_SpeedForm1->MCU_scan_speed=Form2->Table4->FieldByName("C0_VALUE")->AsFloat;Form2->Table4->Locate("CID_DEC",72,Opts); //Set_Number_Of_ScansForm1->MCU_N_blocks=(Form2->Table4->FieldByName("C0_VALUE")->AsFloat-1);
float distance_um = (Form1->MCU_setTrajEndPos)-(Form1->MCU_setTrajStartPos);float scan_time_ms = 1000*distance_um/(Form1->MCU_scan_speed); // um/(um/s)
//int No_of_blocks = scan_time_ms/Form1->ComboBox2->ItemIndex=0; // Assuming = 2umForm1->ComboBox2Change(this); //float EncoderDs_um=2;//////////////////////////////////////////////////////////////////Form1->MCU_gap= 1000*EncoderDs_um/(Form1->MCU_scan_speed);Form1->ChangeTimeGap(Form1->MCU_gap);Form1->Timer2->Interval=scan_time_ms;// Form1->Timer3->Interval=gap;Form1->Edit1->Text=FloatToStr(scan_time_ms);Form1->Edit2->Text=FloatToStr(distance_um);Form1->ComboBox1->ItemIndex=1;
Start timer event =updatingWith constant time interval
Locate Values inThe database andLoad them intoWorking variablesUsed in the Simfunction
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File: simulator.doc
////////////////////////////////////////
break;
case 450: Form1->StopMCU(Par); break;// case 2: break;// case 49: break;// //end switch
if(Form2->Table4->Locate("CID_DEC",Cmd,Opts))Form2->Table4->Edit();Form2->Table4->FieldByName("C0_VALUE")->AsInteger = Par;if(Form2->Table3->Locate("CID_DEC",Cmd+2048,Opts))Form2->Table3->Edit();Form2->Table3->FieldByName("C0_VALUE")->AsInteger = Par;Form2->Table3->Post(); //Table3 = get channel 1//added to notify the database that an update--get buffer is needed
// switch(Cmd)// case 1536 : Form1->SetMCU(Par);// Form1->ComboBox2Change(this);// break;
break;
//// T.B.D. //Channel 2case 2: if(Form2->Table6->Locate("CID_DEC",Cmd,Opts))Form2->Table6->Edit();Form2->Table6->FieldByName("C0_VALUE")->AsInteger = Par;if(Form2->Table5->Locate("CID_DEC",Cmd+2048,Opts))Form2->Table5->Edit();Form2->Table5->FieldByName("C0_VALUE")->AsInteger = Par; Form2->Table5->Post();break;//--Switch
2.9.4 Commanding ExamplesSome test examples. Implementation will change as more details are known.
Receiver side
Chopping examp Start simulator TraSelect Function 1 foTransferChannelSe
20
Command r
SET
43Channel
le
nsmitter r channel 0 (D1 in functtingsToDriver
SEND NOW
Paramete
tion unit) and click on
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Date : 2003-02-10Issue : 1.0 Page : 24 / 28
File: simulator.doc
Enter following command sequence (remember to change channel CH) on the “receiverside”
Command CH CIDDEC
CIDHEX
Parameter ParVaDEC
Simulator Action
Div factor 1 0 0 0 20000/d1 100 Received commandDivFactor2 0 1 1 20000/d1*d2 4 Time Gap =15 msMode Chang 0 41 29 2No Of Blocks 0 42 2A continuously 0 Loop is checkedStart/Stop 0 43 2B Start (!=0) 2 Block TransferStartsSet Pos Y0 1 195 C3 Y0 10 Value10 Stored in database Set Pos Y1 1 196 C4 Y1 30 Value 30 Stored in DatabaseChop Period 1 197 C5 Period ms 800 Value 800 stored in DatabaseStart Chop 1 198 C6 Chop Mode 2 ComboBox Changes ON
Chopped values are transferredStop Chop 1 198 C6 0=stop 0 Chop OFF comboboxStop Transf 0 43 2B 0=stop 0 Block TransferStops
Mirror position example
Select Function 0 in GUI for Channel 0 (D0 in function unit) and click onTransferChannelSettingsToDriver
Enter the following command sequence
If using the “Demo Receiver “ application this will display a sinus functionwhile the scans are in progress.
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Date : 2003-02-10Issue : 1.0 Page : 25 / 28
File: simulator.doc
Command CH CID CIDHex
Parameter ParV Simulator action
Chg Mode 0 41 29 accquistion 6 Changes Mode SettingsNo of Blocks 0 42 2A Contin=0 0 Loop is checkedStart/Stop 0 43 2BEndPos 1 69 45 End Pos um 11300 Value Stored in databaseStartPos 1 70 46 Start Pos um 4700 Value Stored in databaseSpeed 1 71 47 Speed um/s 1000 Value Stored in databaseNscan 1 72 48 N scans 2 Value Stored in databaseStart/Stop 1 448 1C0 Start Telem 2 Telemetry ON ScanMode 1 73 49 StartScan 2 RunSawTooth -during scan(s)Start/Stop 1 448 1C0 StopTelem. 0 Telemetry OFFStart/Stop 0 43 2B StopBlockTr 0 Transfer Stops
2.10 Trouble Shooting
Check Windows Task Manager So that only one transmit.exe is running
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Date : 2003-02-10Issue : 1.0 Page : 26 / 28
File: simulator.doc
3.1 System Tests
Performance
The processor load on transmitter side depends on number of active channels, lengths of blocksand breaks between the blocks. For the most critical situation i.e. all the channels working, nobreaks between the blocks (if the break between the blocks’ starts is set to time smaller than thetransmission of the block time then there is a break of 2 stop bits i.e. 2us between the blocks)and long blocks the processor load without the optimisation was equal to 100%. If a block islong (e.g. 1000 words) than there is no need to calculate new data with a full speed (approx. 1ms per block) as the new block is necessary every 17 ms. The calculating thread goes asleepfor this period and calculates the data only once instead of 17 times.
The function we are using is pretty complicated and the processor is calculating all the time.However as mentioned above the new data block is required only after the previous one wastransmitted. The optimisation is active and the program only calculates new data before theyare needed for a new transmission.
The maximum processor load we observed for all three channels sending constantly 500 or1000 words without a break between the blocks (break between the starts set to e.g. 1 ms) wasequal to 40% on 500 MHz Pentium III.
Performance test with the following assumptionsThe fastest block rate is 500 Hz (for a very short block, just 7 words). At the same time (but notsynchronised), larger blocks (69 words) are sent at 160 Hz (or so) on another channelThe load was around 6 to 8%. The measurement results are shown on the following twopages.
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File: simulator.doc
3.2 Logic Analyser Displays
Channel 0 – 330 words every 10 ms, Channel 1 – 10 words every 2 ms, Channel 2 – 50words every 5 ms Load 7%
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File: simulator.doc
The same settings as above – 10 times faster sampling to show the details. Not all theframes can be seen as not all the zeroes between the blocks are registered (they are tooshort for the sampling frequency set)
B
C
D
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B
INH1INSTR1
INH2INSTR2
INH3INSTR3
CLKIN
OUTH1
INL1INL2
OUTL2
INL3OUTL1
OUTL3
CLKOUT
OUTSTR1
OUTSTR3OUTH3
OUTSTR2OUTH2
DIR
INOUTINOUT.SCH
MD[7..0]
DQ[31..0]
PTADR#PTWR
ADDINT#
INH1INSTR1
INH2INSTR2
INH3INSTR3
OUTH1OUTSTR1
OUTSTR3OUTH3
OUTSTR2OUTH2
DIR
CLKIN
INL1INL2
OUTL2
INL3OUTL1
OUTL3
CLKOUT
DXFR#PTATN#
SYSRES#
WAIT#
20MHz
XilinxXilinx.sch
DQ[31..0]
MD[7..0]
ADCLK
ADDINT#
SYSRST#DXFR#
PTATN#PTADR#
PTWRWAIT#
PCIPCI.SCH
1 2 3 4 5 6
AA
Title
Number RevisionSize
B
Date: 5-Mar-2002 Sheet of File: C:\HERMES\Hermes.ddb Drawn By:
1 2 3 4 5 6 7 8
A
B
C
D
87654321
D
C
B
A
1
a brand new world Polskaul. Swietojanska 75/4
81-389 Gdyniatel/fax +48 58 62179201
A5-Mar-2002 10:52:11C:\HERMES\Hermes.ddb - Documents\Pci.sch
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A4
AD056
AD155
AD254
AD352
AD448
AD547
AD646
AD744
AD842
AD940
AD1039
AD1138
AD1236
AD1335
AD1434
AD1532
AD1614
AD1712
AD188
AD197
AD206
AD214
AD223
AD232
AD24158
AD25156
AD26155
AD27154
AD28152
AD29148
AD30147
AD31146
PCICLK142
RST#139
INTA#58
C/BE0#43
C/BE1#28
C/BE2#15
C/BE3#159
FRAME#16
DEVSEL#20
IRDY#18
TRDY#19
IDSEL160
STOP#22
LOCK#23
PAR27
PERR#24
SERR#26
DQMODE59
FLT#138
NC136
NC135
NC149
NC29
DQ0 100
DQ1 99
DQ2 98
DQ3 96
DQ4 95
DQ5 94
DQ6 92
DQ7 88
DQ8 86
DQ9 84
DQ10 83
DQ11 82
DQ12 80
DQ13 79
DQ14 78
DQ15 76
DQ16 157
DQ17 145
DQ18 133
DQ19 125
DQ20 117
DQ21 105
DQ22 93
DQ23 85
DQ24 77
DQ25 65
DQ26 53
DQ27 45
DQ28 37
DQ29 25
DQ30 13
DQ31 5
BPCLK 140
ADCLK 134
IRQ# 124
ADDINT# 102
SYSRST# 126
DXFR# 144
ADR2 68
ADR3 67
ADR4 66
ADR5 64
ADR6 132
BE0# 87
BE1# 63
BE2# 62
BE3#/ADR1 60
SELECT# 75
WR# 74
RD# 72
PTNUM0 122
PTNUM1 123
PTBE0# 116
PTBE1# 118
PTBE2# 119
PTBE3# 120
PTATN# 114
PTBURST# 112
PTADR# 107
PTWR 108
PTRDY# 115
PTMODE 104
MD0 57
MD1 61
MD2 69
MD3 73
MD4 81
MD5 89
MD6 97
MD7 101
LOAD# 109
MDMODE 143
SDA 127
SCL 128
NC113
U2
S5920
-12VB1
TCKB2
GROUNDB3
TDOB4
+5VB5
+5VB6
INTB#B7
INTD#B8
PRSNT1#B9
RESERVEDB10
PRSNT2#B11
GROUNDB12
GROUNDB13
RESERVEDB14
GROUNDB15
CLKB16
GROUNDB17
REQ#B18
+5VB19
AD31B20
AD29B21
GROUNDB22
AD27B23
AD25B24
+3.3VB25
C/BE3#B26
AD23B27
GROUNDB28
AD21B29
AD19B30
+3.3VB31
AD17B32
C/BE2#B33
GROUNDB34
IRDY#B35
+3.3VB36
DEVSEL#B37
GROUNDB38
LOCK#B39
PERR#B40
+3.3VB41
SERR#B42
+3.3VB43
C/BE1#B44
AD14B45
GROUNDB46
AD12B47
AD10B48
GROUNDB49
AD8B52
AD7B53
+3.3VB54
AD5B55
AD3B56
GROUNDB57
AD1B58
+5VB59
ACK64#B60
+5VB61
+5VB62
TRST# A1
+12V A2
TMS A3
TDI A4
+5V A5
INTA# A6
INTC# A7
+5V A8
RESERVED A9
+5V A10
RESERVED A11
GROUND A12
GROUND A13
RESERVED A14
RST# A15
+5V A16
GNT# A17
GROUND A18
RESERVED A19
AD30 A20
+3.3V A21
AD28 A22
AD26 A23
GROUND A24
AD24 A25
IDSEL A26
+3.3V A27
AD22 A28
AD20 A29
GROUND A30
AD18 A31
AD16 A32
+3.3V A33
FRAME# A34
GROUND A35
TRDY# A36
GROUND A37
STOP# A38
+3.3V A39
SDONE A40
SBO# A41
GROUND A42
PAR A43
AD15 A44
+3.3V A45
AD13 A46
AD11 A47
GROUND A48
AD9 A49
C/BE0# A52
+3.3V A53
AD6 A54
AD4 A55
GROUND A56
AD2 A57
AD0 A58
+5V A59
REQ64# A60
+5V A61
+5V A62
P1
PCI5V32BIT
PCI_LOCAL_BUS
+5V
+5V+5V
+5V+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V+5V
PCICLK
AD31AD29
AD27AD25
C/BE3#AD23
AD21AD19
AD17C/BE2#
IRDY#
DEVSEL#
LOCK#PERR#
SERR#
C/BE1#AD14
AD12AD10
AD8AD7
AD5AD3
AD1
INTA#
RST#
AD30
AD28AD26
AD24IDSEL
AD22AD20
AD18AD16
STOP#
FRAME#
TRDY#
PARAD15
AD13AD11
AD9
C/BE0#
AD6AD4
AD2AD0
AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31
PCICLKRST#INTA#
C/BE0#C/BE1#C/BE2#C/BE3#
FRAME#DEVSEL#IRDY#TRDY#IDSEL
STOP#LOCK#
PARPERR#SERR#
VCC+5V
VCC
DQ[31..0]DQ[31..0]
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31
IRQ#ADDINT#SYSRST#DXFR#
PTNUM0PTNUM1
PTBE0#PTBE1#PTBE2#PTBE3#
PTATN#PTBURST#
PTADR#PTWRWAIT#
MD0MD1MD2MD3MD4MD5MD6MD7
SCLSDA
ADCLK
MD[7..0] MD[7..0]
ADCLK
ADDINT#SYSRST#DXFR#
PTNUM0PTNUM1
PTATN#
PTADR#PTWR
TEST 7
SCL 6
SDA 5
A01
A12
A23
U3
24C16
VCC
VCC
R1
4k7
R2
4k7
LOAD# LOAD#
C1
10n
C2
10n
C3
10n
C4
10n
C5
10n
C6
10n
C7
10n
C8
10n
C9
10n
C10
10n
C11
10n
C12
10n
C13
10n
C14
10n
+ C1510n
VCC
WAIT#
C16
10n
C17
10n
C18
10n
C19
10n
C20
10n
C21
10n
C22
10n
C23
10n
C24
10n
C25
10n
VCC
1 2 3 4 5 6 7 8
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B
C
D
87654321
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B
A
1
a brand new world Polskaul. Swietojanska 75/4
81-389 Gdyniatel/fax +48 58 62179201
xilinx.sch
A5-Mar-2002 10:52:42C:\HERMES\Hermes.ddb - Documents\Xilinx.sch
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A4
VCC
MD[7..0]
MD0MD1MD2MD3MD4
MD[7..0]
DQ[31..0]DQ[31..0]IO/PGCK12
IO/PGCK239
IO/PGCK376
IO/PGCK4112
IO/SGCK1143
IO/SGCK233
IO/SGCK370
IO/SGCK4/DOUT106
NC 34NC 38
IO/TDI6 IO/TCK7
IO/TMS 11
MODE 36
IO/HDC40
IO/LDC 44
IO/INIT53
DONE72
PROGRAM74 IO/DIN105 CCLK107
O/TDO 109
IO3
IO4
IO5
IO 9
IO 10
IO12
IO 13
IO 14
IO 15
IO 16
IO 19
IO 20
IO 21
IO 22
IO 23
IO 24
IO 25
IO 26
IO 28
IO 29
IO 30
IO 31
IO32
IO41
IO 42
IO 43
IO 46
IO 47
IO 48
IO 49IO50
IO 51IO52
IO 56
IO 57
IO 58
IO 59IO60
IO61
IO62
IO63
IO65
IO66
IO67
IO68
IO 69
IO75
IO77
IO78
IO 79IO 80
IO 82IO 83IO 84IO 85IO 86IO 87
IO88
IO89
IO 92
IO 93
IO 94IO 95IO 96IO 97IO 98IO 99
IO101
IO102
IO103
IO104
IO111
IO113
IO114
IO115 IO116
IO 117
IO119
IO 120
IO121
IO 122
IO123
IO124
IO125
IO126
IO129
IO130
IO131
IO132
IO133
IO134
IO135
IO136
IO138
IO139
IO 140
IO141
IO142
U18
XCS20
MD5MD6MD7
PTADR#
PTWR
ADDINT#
INH1INSTR1
INH2INSTR2
INH3INSTR3
OUTH1OUTSTR1
OUTSTR3OUTH3
OUTSTR2OUTH2
DIR
CLKIN
INL1INL2
OUTL2
INL3
OUTL1
OUTL3
CLKOUT
INH1
OUTH1
INSTR1
OUTSTR1
INH2
OUTH2
INSTR2
OUTSTR2
DIR
INH3
OUTH3
INSTR3
OUTSTR3
CLKOUT
INL1
OUTL1
INL2
OUTL2
INL3
OUTL3
PTADR#
PTWR
CLKIN
R29
1kVCC
D1
LED
DXFR#
DQ0DQ1DQ2DQ3DQ4DQ5DQ7DQ8DQ9DQ10DQ11DQ6DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31
20MHz
DXFR#
DXFR
ADINT#
IR1IR2IR3
HF1HF2HF3
AF1AF2AF3
SYSRES#RESET#
WEN1WEN2WEN3
REN1REN2REN3
OR1OR2OR3
WAIT#
MHz 3Q1
IQXO-22
20MHz#
SYSRES#
WAIT#
RESET#1
OE 2
REN23 REN14 RDCLK5
D177 D168 D159 D1410 D1311 D1212 D1113 D1014 D915 D817 D719 D620 D521 D422 D323 D224 D125 D026
DAF#27
WRCLK29
WREN130
WREN231 AF 33
IR 35
HF 36
Q0 38
Q1 39
Q2 41
Q3 42
Q4 44
Q5 46
Q6 47
Q7 49
Q8 50
Q9 52
Q10 53
Q11 55
Q12 56
Q13 58
Q14 59
Q15 61
Q16 63
Q17 64
OR 66
U20SN74ACT7882
RESET#1
OE 2
REN23 REN14 RDCLK5
D177 D168 D159 D1410 D1311 D1212 D1113 D1014 D915 D817 D719 D620 D521 D422 D323 D224 D125 D026
DAF#27
WRCLK29
WREN130
WREN231 AF 33
IR 35
HF 36
Q0 38
Q1 39
Q2 41
Q3 42
Q4 44
Q5 46
Q6 47
Q7 49
Q8 50
Q9 52
Q10 53
Q11 55
Q12 56
Q13 58
Q14 59
Q15 61
Q16 63
Q17 64
OR 66
U19SN74ACT7882
RESET#1
OE 2
REN23 REN14 RDCLK5
D177 D168 D159 D1410 D1311 D1212 D1113 D1014 D915 D817 D719 D620 D521 D422 D323 D224 D125 D026
DAF#27
WRCLK29
WREN130
WREN231 AF 33
IR 35
HF 36
Q0 38
Q1 39
Q2 41
Q3 42
Q4 44
Q5 46
Q6 47
Q7 49
Q8 50
Q9 52
Q10 53
Q11 55
Q12 56
Q13 58
Q14 59
Q15 61
Q16 63
Q17 64
OR 66
U21SN74ACT7882
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15
GND
VCC
VCC VCC
GND GND
RESET#RESET#
RESET#
20MHz
20MHz 20MHz
20MHz
20MHz
20MHz
IR1REN1HF1AF1OR1
IR2REN2HF2AF2OR2
IR3REN3HF3AF3OR3
WEN3DXFR
REN3REN3
WEN2DXFR
REN2REN2
WEN1DXFR
REN1REN1
PTATN# PTATN#20MHz
R119 47kR120 47kR121 47k
VCC
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Transmitter: MainMacro: NAD1Date: 9/9/00
Date Last Modified: 2/27/02
P2
GND
P39P112
P49
GND
P117
L1
PAD31_16_INOUT
P[15:0]
GND
OBUF
P69OBUF
L2
LED
CLK_OUTCLOCK
BUFGS P143
P70
T3
LSIO
I
20MHZ
EN
SER
CLKL
PTWR
P[31:0]
DXFRBUFGP
L3
INOUT15_00
CLKCEDQ
P[15:0]
O[15:0]
OE
I[15:0]
ICLOCK
IQ[15:0]
ICLK_EN
T1
LSIO
I
20MHZ
EN
SER
CLKL
PTWR
P[31:0]
DXFR
OBUF
VCC
IBUF
P76
OBUF
INV
INV
BUFGS
H1
HSIO
P[15:0]
WAITCLKH
SER
FR
20MHZ
PTWR
Q
PTATNOR
RENDXFR
I
EN
P12
GND
OBUFOBUF
OBUFP5
OR2 L4
TRI16
OE
I[15:0] O[15:0]
L5
PAD15_0_INOUT
P[15:0]
L6 INOUT31_16
O[15:0]
P[15:0]
OE
I[15:0]
P42
P141
U3
INT_500USCLK_OUTCLOCK
GND
BUFGP
R3
LSIIP
P[31:0]
CLKL
EN
S
PTWR
I
DXFR
20MHZ
I514
FDCED
C
CE
CLR
Q
P59
BUFGP
GND
OBUF
L7
DIV20CLK_OUTCLOCK
P140OBUF
R1
LSII
CLKL
EN
S
DXFR
P[31:0]
I
20MHZ
PTWR
IBUFP122
H2
HSIO
P[15:0]
WAITCLKH
SER
FR
20MHZ
PTWR
Q
PTATNOR
RENDXFR
I
EN
OBUFOBUF
P138
P43
H3
HSIO
P[15:0]
WAITCLKH
SER
FR
20MHZ
PTWR
Q
PTATNOR
REN
DXFR
I
EN
OBUFOBUF
P44
P135
P51
T2
LSIO
I
20MHZ
EN
SER
CLKL
PTWR
P[31:0]
DXFR
OBUF
R2
LSII
CLKL
EN
S
DXFRP[31:0]
I
20MHZ
PTWR
IBUFP120
L8
LATCH4
CLOCK
D_IN[3:0] Q_OUT[3:0]
I59
D4_16EA0
A1
A2
A3
D0
D1
D10
D11
D12
D13
D14
D15
D2
D3
D4
D5
D6
D7
D8
D9
E
NOR2
BUFGP
P136IBUF
P139
AND3B2
P142
IBUF
AND3B1
VCC
VCC
I512
FDCED
C
CE
CLR
Q
P9
OBUF
P10
P11
OBUF
OBUF
NOR3
OBUFP4
STARTUPGSR
GTS
CLK
Q3
Q2
Q1Q4
DONEIN
U1
IRQMASK
A[15:0]
P[15:0]
ADCLK
DXFR
EN
PTWR
O[15:0]
IBUF
OBUFP3
OBUFP75
INV
P7OBUF
I409AND3B1
I410AND3B1
I411AND3B1
P6OBUF
OR8
OR8
I488
AND3B1
IBUF
OBUFP115
INV
BUFGSP33
P129P124
P132
IBUFIBUF
IBUF
P130P125
P133
IBUFIBUF
IBUF
P126P123
P131
IBUFIBUF
IBUF
P116
I508FD
C
D Q
INV
BUFGS
OR3
H4
FAZA
CLK Q1
Q2
Q3
A[3:0]
BUSOUT[31:16]
BUSOUT[31:0]
BUSOUT[15:0]
BUS[15:0]
BUSOUT[15:0]
BUSIN[31:16]
BUSIN[15:0]
BUS[31:16]
FIFOBUS[15:0]
BUSIN[31:0]
BUSOUT[31:0]
FIFOBUS[15:0]
FIFOBUS[15:0]
BUSIN[31:0]
BUSOUT[31:0]
BUSIN[31:0]
DQ[15:0]
BUSIN[5:2]
DQ[15:0]
BUSIN[15:0]IRQ[15:0]
FIFOBUS[15:0]
L1
PTWR
DQ11
ADDINT
PTWR
DXFR
DXFR
L2
L1
DXFR
PAD49
PAD70
PAD76
SOFT_INT
IRQ5
SEROUTH1
STROUTH1
H3
DIR
DQ14
PAD12
DXFR
PAD42
PAD141
DQ13
20MHZ
ADDINT
20MHZ
20MHZ
DXFR
PAD112
DXFR
PTADR
RD
INT_TICK
DATAINL3
IRQ6
IRQ
PAD69
PAD143
DQ12
PTWR
L5
IRQ_MASK
RD
DATAOUTL1
PTWR
20MHZ
PTADR
IRQ7
A3
L2
PAD39
PTWR
PTWR
L3
20MHZ
PAD2
PAD135
PAD140
IRQ_MASK
DATAINL1 PAD122
PAD44
SEROUTH2
STROUTH2
A0
PAD138
PAD43
RD
L0
CLKIN
SEROUTH3
STROUTH3
PAD51
DATAOUTL3
DATAOUTL2
DQ10
DATAINL2 PAD120
PAD117
PAD59
A1
IRQ
L4
A2
IRQ8
L0
CLKIN
DQ2
L3
L4
L5
DQ9
CLKOUT
20MHZ
CLKOUT
DQ3
DQ5
DQ0
DQ1
DQ4
DXFRPTATN
OR3
OR2PAD139
Q1
Q2
Q3
AF1
OR1PAD142
SOFT_INT
DXFR
PAD9
PAD11
PAD10
W1
W2
W3
REN1
REN2
REN3
PAD4WAIT
W1
W2
W3
DQ6
DQ7
DQ8
PAD3
PAD75
H1
H2
H3
PAD7
PAD6
PAD5
WEN1
WEN2
WEN3
PTWR
DXFR
H1
H2
IRQ10
DQ15
IRQ11
IRQ13
IRQ15
REN3
PTWR
PAD132
PAD129
PAD124
IR1
IR2
IR3
PAD133
PAD130
PAD125
HF1
HF2
HF3
PAD131
PAD126
PAD123
OR3
FIFO2
PAD136
PAD116
PAD115
RESRESET
PAD33PTATN
IRQ14
IRQ12
IRQ9
RESET
FIFO1
FIFO2
FIFO3
OR1
OR2
FIFO3
AF2
PTWR
AF3
FIFO1
CLKOUT
INT_TICK
DXFR
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
20MHZ
CLKIN
20MHZ
REN1
REN2
20MHZ
SOFT_INT
20MHZ
PTWR
CLKOUT Q1
Q2
Q3
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Transmitter: Fast channel transMacro: HSIODate: 7/25/00
Date Last Modified: 2/27/02
INV
I388
FDCE
D
C
CE
CLR
Q
L3
HSIOUT
CLOCK
D_IN[15:0]
LOAD
MS_OUT
L20
LATCH16E
CLOCK
CLK_EN
D_IN[15:0]Q_OUT[15:0]
VCC
I94
FDCE
D
C
CE
CLR
Q
L9
DIV16CLK_OUTCLOCK
ASYNC_CTRL
AND2
VCC
I387
FDCE
D
C
CE
CLR
QINV
AND2B1
I488
AND3B2
I494
FDCE
D
C
CE
CLR
Q
I490
FDCE
D
C
CE
CLR
Q
INV
I489
FD
C
D Q
I100
FDCE
D
C
CE
CLR
Q
I101
FDCE
D
C
CE
CLR
Q
I102
FDCE
D
C
CE
CLR
Q
I103
FDC
CCLR
D Q
INV
AND2B1AND2AND2
I112
FD
C
D Q
I113
FD
C
D Q
I114
FD
C
D Q
I115
FD
C
D Q
AND2
INV
I496
FD
C
DQ
VCC
GND
I492
FDCE
D
C
CE
CLR
Q
I493
FDCE
D
C
CE
CLR
Q
I512
FD
C
DQ
P[15:0]H[15:0]
FR-
CLKH-
FR-
FR
CLKH
20MHZ-
CLKH-
FR
FR
SER
FR-
EMPTY
ORDELAY
CLKH-
RDY
20MHZ
LOAD RDY
I
20MHZ-
FR-
20MHZ- EN
CLR_IRQ
PTWR
FR
Q
REN
REN
20MHZ- CLR
WAIT
STARTDXFR
PTATN
Q
ORDELAY
CLKH-
OR
CLKH-
CLKH
EMPTY
Q
20MHZ
CLKH
20MHZ-
CLR_IRQ
CLKH
CLR_IRQ
FR
FR
DXFR
FR-
CLKHCLKH
20MHZ-
REN
20MHZ
CLK_EN
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Transmitter: TESTMacro: test2Date: 7/25/00
Date Last Modified: 10/7/01
AND3B1
L10
LATCH16E
CLOCK
CLK_EN
D_IN[15:0]Q_OUT[15:0]
L13
BUSAND
A[15:0]
B[15:0]O[15:0]
P[15:0]B[15:0]
A[15:0]
O[15:0]
PTWR
ADCLK
EN
DXFR
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Transmitter: Macro: FAZADate: 7/3/01
Date Last Modified: 2/27/02
INV
FD
C
D Q
FD
C
D Q
FD
C
D Q
NOR2
CLK
Q2
Q1
Q3
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Transmitter: TransmiterMacro: LSIIPDate: 7/25/00
Date Last Modified: 2/27/02
FD
C
D Q
INV
L9
TRI32P
OE
I[31:0]O[31:0]
FDCE
D
C
CE
CLR
Q
GND
AND3B1
L10
LSIIN32
LS_IN
Q_OUT[31:0]
CLOCK
FDCE
D
C
CE
CLR
Q
L12
LATCH32E
CLOCK
CLK_EN
D_IN[31:0]Q_OUT[31:0]
INVL11
DIV32CLK_OUTCLOCK
ASYNC_CTRL
FDCE
D
C
CE
CLR
Q
INV
VCC
FDCE
D
C
CE
CLR
Q
FD
C
D Q
INV
GND
INV
P[31:0]DI[31:0] DO[31:0]
PTWR
CLKL
FR
FR-
EN
DXFR
CLK_EN
EN
20MHZ-
CLKL
CLKL-
I
CLKL
FRFR-
FR-
CLKL-S
LATCH_EN
CLKL
20MHZ
LATCH_EN
LATCH_ENCLK_EN-CLK_EN
20MHZ
20MHZ-
20MHZ-
CLKL-
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Transmitter: Slow channel receiverMacro: LSIIDate: 7/25/00
Date Last Modified: 2/27/02
INV
INVL9
TRI32
OE
I[31:0]O[31:0]
L12
LATCH32E
CLOCK
CLK_EN
D_IN[31:0]Q_OUT[31:0]
L10
LSIIN32
LS_IN
Q_OUT[31:0]
CLOCK
FD
C
D Q
FDCE
D
C
CE
CLR
Q
GND
AND3B1
FDCE
D
C
CE
CLR
Q
INVL11
DIV32CLK_OUTCLOCK
ASYNC_CTRL
FDCE
D
C
CE
CLR
Q
VCC
FDCE
D
C
CE
CLR
Q
FD
C
D Q
INV
GND
INV
P[31:0]DI[31:0] DO[31:0]
CLKL-
LATCH_EN
CLKL
EN
20MHZ
PTWR
CLKL
FR
FR-
DXFR
CLK_EN
EN
CLR_IRQ
I
CLKL
FRFR-
FR-
LATCH_EN
20MHZ
LATCH_ENCLK_EN-CLK_EN
CLKL-
S
20MHZ-
CLKL20MHZ-
20MHZ
CLKL-
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Transmitter: Slow channel transmitterMacro: LSIODate: 7/25/00
Date Last Modified: 2/27/02
L17
LSIOUT
CLOCK
D_IN[31:0]
LOAD
MS_OUT
VCC
L16
LATCH32E
CLOCK
CLK_EN
D_IN[31:0]Q_OUT[31:0]
INV
INV
GND
FDCE
D
C
CE
CLR
Q
L10
DIV32CLK_OUTCLOCK
ASYNC_CTRL
AND2
FDCE
D
C
CE
CLR
Q
AND3B1
AND3B1
VCC
AND2B1
FDCE
D
C
CE
CLR
Q
AND3B2
FD
C
D Q
FDCE
D
C
CE
CLR
Q
FD
C
D Q
D_IN[31:0]P[31:0]
CLKL-
20MHZ
SER
FR-
PTWR
FR
DXFR
DXFR
CLKL
EN
PTWR
CLKL-
I
CLKL
FR
EN
CLKL
DXFR
RDY
FR-
CLKL
20MHZ
CLK_EN
EN
PTWR
FR-
CLKL
CLKL-CLKL-
FR
RDY
FR
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Receiver: MainMacro: PCI2ODBDate: 9/9/00
Last Modified: 2/26/02 Date Last Modified: 2/27/02
P2
IBUF
P39P112
P49
P56
P117L1
PAD31_16_INOUT
P[15:0]
IBUF
OBUF
P69OBUF
L2
LED
CLK_OUTCLOCK
BUFGS P143
P70
T3
LSIO
I
20MHZ
EN
SER
CLKL
PTWR
P[31:0]
DXFR
BUFGP
L3 INOUT15_00
P[15:0]
O[15:0]
OE
I[15:0]
T1
LSIO
I
20MHZ
EN
SER
CLKL
PTWR
P[31:0]
DXFR
OBUF
U1
IRQMASK
EN
P[15:0]20MHZ
DXFR
A[15:0]
PTWR
O[15:0]
IBUF
P76
OBUF
BUF
INV
BUFGS
H1
HSII
CLKH
20MHZ
FR
WAIT
S
P[15:0]
Q
DXFRPTATN
WEN
IRQ2IRQ3
AF
IRQ1
EN
PTWR
P12
GND
I25 NOR2
I26
OR8
OBUF
P5
OR5
L4
TRI16P
OE
I[15:0] O[15:0]
L5
PAD15_0_INOUT
P[15:0]
L6 INOUT31_16
O[15:0]
P[15:0]
OE
I[15:0]
H4
FAZA
CLK Q1
Q2
Q3
P141
AND2
P33
BUFGP
R3
LSII
CLKL
EN
S
DXFRP[31:0]
I
20MHZ
PTWR
INV
P59
BUFGP
BUFGS
OBUF
L7
DIV64CLK_OUTCLOCK
P140OBUF
R1
LSII
CLKL
EN
S
DXFR
P[31:0]
I
20MHZ
PTWR
IBUFP122
H3
HSII
CLKH
20MHZ
FR
WAIT
S
P[15:0]
Q
DXFRPTATN
WEN
IRQ2IRQ3
AF
IRQ1
EN
PTWR
IBUFP116
P138
IBUF
H2
HSII
CLKH
20MHZ
FR
WAIT
S
P[15:0]
Q
DXFRPTATN
WEN
IRQ2IRQ3
AF
IRQ1
EN
PTWR
IBUFIBUF
P131
P135
P51
T2
LSIO
I
20MHZ
EN
SER
CLKL
PTWR
P[31:0]
DXFROBUF
R2
LSII
CLKL
EN
S
DXFRP[31:0]
I
20MHZ
PTWR
IBUFP120
L8
LATCH4
CLOCK
D_IN[3:0] Q_OUT[3:0]
I56
D4_16EA0
A1
A2
A3
D0
D1
D10
D11
D12
D13
D14
D15
D2
D3
D4
D5
D6
D7
D8
D9
E
I57
OR8
BUFGP
IBUFIBUFIBUF
P142P139P136
INV
GN
DG
ND
IBUF
P123
OBUF
P126
IBUF
OBUF
OBUF
I75NOR3
OBUFP4
P115OBUF
STARTUPGSR
GTS
CLK
Q3
Q2
Q1Q4
DONEIN
OBUFP3
I83OBUF
P75INV
P7OBUF
I88AND3B2
I89AND3B2
I90AND3B2
P6OBUF
P58P48
IBUFIBUF
P57P47
IBUFIBUF
P46
P129P124
P132
IBUFIBUF
IBUF
P130P125
P133
IBUFIBUF
GN
VCC
GN
D
BUFBUF
BUFBUFBUFBUFBUFBUFBUFBUFBUFBUF
L9
TRI16P
OE
I[15:0] O[15:0]
GN
D
I139
FD
C
D Q
INV
BUFGS
I142
BUFT
T
I143
BUFT
T
I144
BUFT
T
OR2
INV
INV
U3
INT_500US
CLK_OUTCLOCK
I150
AND3B1
I151
FDCED
C
CE
CLR
Q
A[3:0]
BUSOUT[31:16]
BUSOUT[31:0]
BUSOUT[15:0]BUS[15:0]
IRQ[31:16]
BUSIN[31:16]
BUSIN[15:0]
BUS[31:16]
BUSOUT[15:0]
BUSIN[31:0]
BUSOUT[31:0]
BUSOUT[15:0]
BUSOUT[15:0]
BUSIN[31:0]
BUSOUT[31:0]
BUSIN[31:0]
DQ[15:0]
BUSIN[5:2]
IRQ[15:0]
BUSIN[15:0]
DQ[15:0]
BUSOUT[31:16]
BUSOUT[15:0]
L1
PTWR
DQ13
IRQ27
PTWR
DXFR
DXFR
L2
L1
IRQ_MASK
PAD49
PAD70
PAD76
IRQ-
LED
IRQ28
Q3
H3
DIR
DQ14
PAD12
HF1
H1
PAD141
DQ11
20MHZ
ADDINT
20MHZ
HF2
DXFR
PAD112
DXFR
PTADR
RD2
HF3
DATAINL3
OR1
H3
PAD69
PAD143
DQ8
OR2
L5
20MHZ
RD1
DATAOUTL1
PTWR
20MHZ
PTADR
IRQ_MASK
A3
L2
PAD39
PTWR
IRQ
L3
20MHZ
H2
PAD2
PAD135
PAD140
DATAINL1 PAD122
OR3
IR2
AF2
A0
PAD138
H3
WAIT
L0
CLKOUT
AF3
ADDINT
PAD51
DATAOUTL3
DATAOUTL2
DQ10
DATAINL2 PAD120
PAD117
PAD59
A1
IRQ
L4
A2
WAIT
IRQ31
L0
CLKOUT
DQ2
L3
L4
L5
DQ7
CLKIN
20MHZ
CLKOUT
DQ3
DQ5
DQ0
DQ1
DQ4
DXFRPTATN
STRH3
OR1
INH3
Q1
Q2
Q3
PAD142
PAD139
PAD136
IRQ30
IRQ29
IRQ16
IRQ17
Q1
W1
W2
W3
REN1
REN2
REN3
PAD4WAIT
W1
W2
W3DQ6DQ9
DQ12
PAD3
PAD75
H1
H2
H3
PAD7
PAD6
PAD5
WEN1
WEN2
WEN3
PTWR
DXFR
H1
H2
PAD57
PAD47
PAD46
RESET
STRH1
INH2
STRH2
INH1
PAD56
PAD132
PAD129
PAD124
IR1
IR2
IR3
PAD133
PAD130
PAD125
HF1
HF2
HF3
PAD131
PAD126
PAD123
AF1
AF2
AF3
PAD116
PAD115
RESRESET
PAD33PTATN
PAD58
PAD48
OR2
OR3
FIFO6
FIFO7
FIFO8
AF1
RD1
CLKIN
AF3
AF2
PTWR
FIFO6
FIFO8
FIFO7
Q2
H2
PTWR
IRQ18
IRQ20
IRQ21
IRQ22
IRQ24
IR3
IRQ26
IRQ25
IRQ23
IRQ19IR1
AF1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
20MHZ
DXFR
PAD112BIS
20MHZ
CLKIN
OR1
OR2
OR3 BUSOUT18
BUSOUT16
BUSOUT17
DXFR
PTWRRD2
H1-
H2-
H3-
H1
IRQ-
INT_TICK
DQ15
PTWR
CLKIN
DXFR
CLR_IRQ
INT_TICK
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Receiver: Fast channel receiverMacro: HSIIDate: 8/25/00
Last Modified: 2/26/02 Date Last Modified: 2/27/02
L14
HSIIN
LS_IN
Q_OUT[15:0]
CLOCK
CLK_EN
L15
TRI16
OE
I[15:0]O[15:0]
L16
LATCH16E
CLOCK
CLK_EN
D_IN[15:0]Q_OUT[15:0]
INV
VCC
INV
I132
AND3B1
I163 FDCE
D
C
CE
CLR
Q
I487 FDCE
D
C
CE
CLR
Q
I488 FDCE
D
C
CE
CLR
Q
AND2
I490 FDC
CCLR
DQ
I471 FDC
CCLR
DQ
INV
I162 FD
C
DQ
INV
FDCE
D
C
CE
CLR
Q
VCC
FDCE
D
C
CE
CLR
Q
FDCE
D
C
CE
CLR
Q
FDCE
D
C
CE
CLR
Q
VCC
FD
C
DQ
FD
C
DQ
FDCE
D
C
CE
CLR
Q
FDCE
D
C
CE
CLR
Q
VCC
GNDI550 FDCE
D
C
CE
CLR
Q
INV
BL[15:0]P[15:0]
BI[15:0]
S
FR
CLR
20MHZ-
FR
CLR_IRQ
20MHZ-
EN
20MHZ
20MHZ
WAIT
FR-
FR-
FR
PTWR
CLKH
LATCH_FULL
20MHZ
DXFR
PTATNQ
WRITE
20MHZ
WAIT
CLR
WEN
20MHZ-
CLKH-
WAIT-
CLKH
FR-
CLKH-
DXFR
LATCH_EN
FR
CLKH-
CLR_IRQ
AF-
CLKHCLKH
CLKH
CLKH
IRQ1
CLKH
20MHZ
AF
IRQ2
LATCH_EN
FR
CLR_IRQ
AF-
AF
20MHZ-20MHZ-
20MHZ
IRQ3
FR-
CLR_IRQ
CLR_IRQ
LATCH_FULL
LATCH_FULLLATCH_EN
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Receiver: Macro: IRQMASKDate: 6/21/01
Last Modified: 2/26/02 Date Last Modified:
AND3B1
L10
LATCH16E
CLOCK
CLK_EN
D_IN[15:0]Q_OUT[15:0]
L12
BUSAND16
A[15:0]
B[15:0]O[15:0]
P[15:0]B[15:0]
A[15:0]
O[15:0]
PTWR
20MHZ
EN
CLK_EN
DXFR
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Receiver: Macro: FAZADate: 6/21/01
Last Modified: 10/29/01 Date Last Modified:
FD
C
D Q
FD
C
D Q
FD
C
D Q
NOR2
FD
C
D Q
FD
C
D Q
FD
C
D Q
FD
C
D Q
FD
C
D Q
FD
C
D QQ2
Q1
Q3
CLK
Q1
Q2
CLK
CLK
Q1
Q2
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Receiver: Slow channel transmitterMacro: LSIIDate: 7/25/00
Last Modified: 2/26/02 Date Last Modified: 2/27/02
INV
INV
L9
TRI32
OE
I[31:0]O[31:0]
L12
LATCH32E
CLOCK
CLK_EN
D_IN[31:0]Q_OUT[31:0]
L10
LSIIN32
LS_IN
Q_OUT[31:0]
CLOCK
I141
FD
C
D Q
I142
FDCE
D
C
CE
CLR
Q
GND
I144
AND3B1
I145
FDCE
D
C
CE
CLR
Q
INVL11
DIV32CLK_OUTCLOCK
ASYNC_CTRL
I147 FDCE
D
C
CE
CLR
Q
VCC
I149
FDCE
D
C
CE
CLR
Q
I150
FD
C
D Q
INV
GND
INV
P[31:0]DI[31:0] DO[31:0]
CLKL-
EN-
LATCH_EN
CLKL
EN
20MHZ
PTWR
CLKL
FR
FR-
DXFR
CLK_EN
EN
CLR_IRQ
I
CLKL
FRFR-
FR-
LATCH_EN
20MHZ
LATCH_ENCLK_EN-CLK_EN
CLKL20MHZ-
20MHZ
CLKL-
S
20MHZ-
abnw Polska sp. z o.o.ul. Swietojanska 75/481-389 Gdynia
Receiver: Slow channel receiverMacro: LSIODate: 7/25/00
Last Modified: 2/26/02 Date Last Modified: 2/27/02
L17
LSIOUT
CLOCK
D_IN[31:0]
LOAD
MS_OUTI231 AND2B1
L16
LATCH32E
CLOCK
CLK_EN
D_IN[31:0]Q_OUT[31:0]
I98 AND3B1
VCC
INV
INV
GND
FDCE
D
C
CE
CLR
Q
L10
DIV32CLK_OUTCLOCK
ASYNC_CTRL
AND2
I156
FDCE
D
C
CE
CLR
Q
AND3B1
VCC
I159
FDCE
D
C
CE
CLR
Q
I160AND3B2
FD
C
D Q
FDCE
D
C
CE
CLR
Q
I163
FD
C
D Q
D_IN[31:0]P[31:0]
CLKL-
RDY
EN
LOAD
FR
SER
20MHZ DXFR
CLK_ENPTWR
20MHZ
FR-
CLR
PTWR
FR
DXFR
EN
CLKL-
I
CLKL
FR
EN
START
CLKL
DXFR
RDY
FR-
CLKL
PTWR
FR-
CLKL
CLKL-CLKL-
FR
CLR_IRQ
CLKL
1 2 3 4 5 6 7 8
A
B
C
D
87654321
D
C
B
A
1
a brand new world Polskaul. Swietojanska 75/4
81-389 Gdyniatel/fax +48 58 62179201
A5-Mar-2002 10:51:25C:\HERMES\Hermes.ddb - Documents\Inout.sch
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A4
INH1
INSTR1
INH2
INSTR2
INH3
INSTR3
CLKOUT-A
CLKOUT-B
DATAH1-A
DATAH1-B
CLKIN-B
CLKIN-A
CLKIN
OUTH1
INL1
INL2
OUTL2
INL3
OUTL1
OUTL3
DATAH2-A
DATAH2-B
DATAH3-A
DATAH3-B
STR3-A
STR3-B
STR2-A
STR2-B
STR1-A
STR1-B
INL1-A
INL1-B
OUTL1-B
OUTL1-A
INL2-A
INL2-B
OUTL2-B
OUTL2-A
INL3-A
INL3-B
OUTL3-B
OUTL3-A
CLKOUT-ACLKOUT-B
DATAH1-ADATAH1-B
DATAH2-ADATAH2-B
STR2-A
STR1-ASTR1-B
DATAH3-ADATAH3-B
STR3-ASTR3-B
STR2-B
CLKIN-ACLKIN-B
INL1-AINL1-B
OUTL1-BOUTL1-A
INL2-AINL2-B
OUTL2-BOUTL2-A
INL3-AINL3-B
OUTL3-BOUTL3-A
R3100
T1 T2P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U4
ADM485
R5100
T3 T4P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U6
ADM485
R4100
T5 T7P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U5
ADM485
R7100
T6 T8P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U8
ADM485
R8100
T13 T15P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U9
ADM485
R11100
T14 T16P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U12
ADM485
R12100
T21 T23P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U13
ADM485
R15100
T22 T24P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U16
ADM485
R6100
T9 T11P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U7
ADM485
R9100
T10 T12P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U10
ADM485
R10100
T17 T19P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U11
ADM485
R13100
T18 T20P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U14
ADM485
R14100
T25 T27P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U15
ADM485
R16100
T26 T28P6SMB6.8A
GND
B 7
A 6
RO1
RE2
DE3
DI4
U17
ADM485
CLKOUT
OUTSTR1
OUTSTR3
OUTH3
OUTSTR2
OUTH2
VCC
DIRDIR
VCC
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950
J1
CON50
GND
GND
GND
GND
CLKOUT-ACLKOUT-B
GND
CLKOUT-ACLKOUT-B
GND
CLKIN-ACLKIN-B
GND
GND
GND
CLKIN-ACLKIN-B
GND
GND
GND
HERMES 3 x 6m & 6 x 3m interface cables marked : RED Description Side 1 marked : GREEN
Cannon DB25S (Socket) wire colour Signal Cannon DB25S (Socket)Side 1 Pin # "group" Name Side 2 Pin #
1 SHIELD "I" CLK_312.5kHz_SHD 92 white "I" CLK_312.5kHz_P+ 83 green "II" TX_P+ 44 gray "III" RX_P+ 35 SHIELD "III" RX_SHD 146 not connected not connected 67 not connected not connected 78 blue "IV" CLK_1MHz_P+ 29 SHIELD "IV" CLK_SHD 1
10 black "V" DATA_P+ 1011 gray/pink "VI" GATE_P+ 1112 SHIELD "VI" GATE_SHD 1213 not connected not connected 1314 SHIELD "II" TX_SHD 515 brown "I" CLK_312.5kHz_P- 2116 yellow "II" TX_P- 1717 pink "III" RX_P- 1618 not connected not connected 1819 not connected not connected 1920 not connected not connected 2021 red "IV" CLK_1MHz_P- 1522 violet "V" DATA_P- 2223 SHIELD "V" DATA_SHD 2324 blue/red "VI" GATE_P- 2425 not connected not connected 25
SHIELD SHIELD SHIELD SHIELD
Rev.
Date
EC
N #
Sign.
Sheet
Size /
A4
Date
Sign
Draw
n
Appr.
Final
Rem
arksN
ame:H
ER
ME
S interface cables
Draw
ing #1
11
ALL RIGTHS RESERVED, REPRODUCTION ORISSUE TO THIRD PARTIES IN ANY FORMWHATEVER IS NOT PERMITTED WITHOUTWRITTEN AUTHORITY FROM PROPRIETORS.
Copy/K
opiaT
oT
ill
PRO
TE
L
ICU
SCA
ND
INA
VIA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SHIELD
SIDE
1(marked : R
ED
)
Cannon D
B25S (Socket)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SHIELD
SIDE
2(marked : G
RE
EN
)
Cannon D
B25S (Socket)
SHIELD I
white I
green II
gray III
SHIELD III
not connected
not connected
not connected
not connected
not connected
not connected
blue IV
SHIELD IV
black V
gray/pink VI
SHIELD VI
SHIELD II
brown I
yellow II
pink III
red IV
violet V
SHIELD V
blue/red VI
not connected
SHIELD I
white I
green II
gray III
SHIELD III
not connected
not connected
not connected
not connected
not connected
not connected
blue IV
SHIELD IV
black V
gray/pink VI
SHIELD VI
SHIELD II
brown I
yellow II
pink III
red IV
violet V
SHIELD V
blue/red VI
not connected
RY
SL03.01.2003
HE
RM
ES 3 x 6m
& 6 x 3m
interface cables
Rev.
Date
EC
N #
Sign.
Sheet
Size /
A4
Date
Sign
Draw
n
Appr.
Final
Rem
arksN
ame:H
ER
ME
S terminators
Draw
ing #1
11
ALL RIGTHS RESERVED, REPRODUCTION ORISSUE TO THIRD PARTIES IN ANY FORMWHATEVER IS NOT PERMITTED WITHOUTWRITTEN AUTHORITY FROM PROPRIETORS.
Copy/K
opiaT
oT
ill
PRO
TE
L
ICU
SCA
ND
INA
VIA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SHIELD
SIDE
1
Cannon D
B25P
(Plug)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SHIELD
SIDE
2
Cannon D
B25S (Socket)
RY
SL03.01.2003
HE
RM
ES term
inators
RA
100R
RB
100R
RC
100R
RD
100R
RE
100R
RF
100R
FUNCTIONAL BLOCK DIAGRAM
R
A
B
DI
DE
RE
RO
ADM485
D
2
3
4 5
6
7
81 VCC
GND
REV. A
Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.
a +5 V Low PowerEIA RS-485 Transceiver
ADM485FEATURES
Meets EIA RS-485 Standard
5 Mb/s Data Rate
Single +5 V Supply
–7 V to +12 V Bus Common-Mode Range
High Speed, Low Power BiCMOS
Thermal Shutdown Protection
Short Circuit Protection
Zero Skew Driver
Driver Propagation Delay: 10 ns
Receiver Propagation Delay: 25 ns
High Z Outputs with Power Off
Superior Upgrade for LTC485
APPLICATIONS
Low Power RS-485 Systems
DTE-DCE Interface
Packet Switching
Local Area Networks
Data Concentration
Data Multiplexers
Integrated Services Digital Network (ISDN)
PRODUCT DESCRIPTIONThe ADM485 is a differential line transceiver suitable for highspeed bidirectional data communication on multipoint bustransmission lines. It is designed for balanced data transmissionand complies with both EIA Standards RS-485 and RS-422.The part contains a differential line driver and a differential linereceiver. Both the driver and the receiver may be enabled inde-pendently. When disabled, the outputs are tristated.
The ADM485 operates from a single +5 V power supply.Excessive power dissipation caused by bus contention or by out-put shorting is prevented by a thermal shutdown circuit. Thisfeature forces the driver output into a high impedance state ifduring fault conditions a significant temperature increase isdetected in the internal driver circuitry.
Up to 32 transceivers may be connected simultaneously on abus, but only one driver should be enabled at any time. It is im-portant, therefore, that the remaining disabled drivers do notload the bus. To ensure this, the ADM485 driver features highoutput impedance when disabled and also when powered down.
This minimizes the loading effect when the transceiver is notbeing utilized. The high impedance driver output is maintainedover the entire common-mode voltage range from –7 V to +12 V.
The receiver contains a fail safe feature which results in a logichigh output state if the inputs are unconnected (floating).
The ADM485 is fabricated on BiCMOS, an advanced mixedtechnology process combining low power CMOS with fastswitching bipolar technology. All inputs and outputs containprotection against ESD; all driver outputs feature high sourceand sink current capability. An epitaxial layer is used to guardagainst latch-up.
The ADM485 features extremely fast switching speeds. Minimaldriver propagation delays permit transmission at data rates up to5 Mbits/s while low skew minimizes EMI interference.
The part is fully specified over the commercial and industrialtemperature range and is available in an 8-lead DIL/SOIC package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
ADM485–SPECIFICATIONSParameter Min Typ Max Units Test Conditions/Comments
DRIVERDifferential Output Voltage, VOD 5.0 V R = ∞, Figure 1
2.0 5.0 V VCC = 5 V, R = 50 Ω (RS-422), Figure 11.5 5.0 V R = 27 Ω (RS-485), Figure 1
VOD3 1.5 5.0 V VTST = –7 V to +12 V, Figure 2∆|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 1Common-Mode Output Voltage VOC 3 V R = 27 Ω or 50 Ω, Figure 1∆|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 ΩOutput Short Circuit Current (VOUT = High) 35 250 mA –7 V ≤ VO ≤ +12 VOutput Short Circuit Current (VOUT = Low) 35 250 mA –7 V ≤ VO ≤ +12 VCMOS Input Logic Threshold Low, VINL 0.8 VCMOS Input Logic Threshold High, VINH 2.0 VLogic Input Current (DE, DI) ±1.0 µA
RECEIVERDifferential Input Threshold Voltage, VTH –0.2 +0.2 V –7 V ≤ VCM ≤ +12 VInput Voltage Hysteresis, ∆VTH 70 mV VCM = 0 VInput Resistance 12 kΩ –7 V ≤ VCM ≤ +12 VInput Current (A, B) +1 mA VIN = 12 V
–0.8 mA VIN = –7 VLogic Enable Input Current (RE) ±1 µACMOS Output Voltage Low, VOL 0.4 V IOUT = +4.0 mACMOS Output Voltage High, VOH 4.0 V IOUT = –4.0 mAShort Circuit Output Current 7 85 mA VOUT = GND or VCC
Tristate Output Leakage Current ±1.0 µA 0.4 V ≤ VOUT ≤ +2.4 V
POWER SUPPLY CURRENTICC (Outputs Enabled) 1.35 2.2 mA Outputs Unloaded, Digital Inputs = GND or VCC
ICC (Outputs Disabled) 0.7 1 mA Outputs Unloaded, Digital Inputs = GND or VCC
Specifications subject to change without notice.
TIMING SPECIFICATIONSParameter Min Typ Max Units Test Conditions/Comments
DRIVERPropagation Delay Input to Output TPLH, TPHL 2 10 15 ns RL Diff = 54 Ω CL1 = CL2 = 100 pF, Figure 3Driver O/P to O/P TSKEW 0 5 ns RL Diff = 54 Ω CL1 = CL2 = 100 pF, Figure 3Driver Rise/Fall Time TR, TF 2 10 ns RL Diff = 54 Ω CL1 = CL2 = 100 pF, Figure 3Driver Enable to Output Valid 10 25 nsDriver Disable Timing 10 25 ns
RECEIVERPropagation Delay Input to Output TPLH, TPHL 18 25 40 ns CL = 15 pF, Figure 5Skew |TPLH–TPHL| 0 5 nsReceiver Enable TEN1 15 25 ns Figure 6Receiver Disable TEN2 15 25 ns Figure 6
Specifications subject to change without notice.
REV. A–2–
(VCC = +5 V 5%. All specifications TMIN to TMAX unless otherwise noted)
(VCC = +5 V 5%. All specifications TMIN to TMAX unless otherwise noted.)
ADM485
REV. A –3–
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 VInputs
Driver Input (DI) . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 VControl Inputs (DE, RE) . . . . . . . . . . –0.3 V to VCC + 0.3 VReceiver Inputs (A, B) . . . . . . . . . . . . . . . . . –14 V to +14 V
OutputsDriver Outputs . . . . . . . . . . . . . . . . . . . . . . . –14 V to +14 VReceiver Output . . . . . . . . . . . . . . . . . –0.5 V to VCC +0.5 V
Power Dissipation 8-Pin DIP . . . . . . . . . . . . . . . . . . . 500 mWθJA, Thermal Impedance . . . . . . . . . . . . . . . . . . +130°C/W
Power Dissipation 8-Pin SOIC . . . . . . . . . . . . . . . . . 450 mWθJA, Thermal Impedance . . . . . . . . . . . . . . . . . . +170°C/W
Power Dissipation 8-Pin Cerdip . . . . . . . . . . . . . . . . 500 mWθJA, Thermal Impedance . . . . . . . . . . . . . . . . . . +125°C/W
Operating Temperature RangeCommercial (J Version) . . . . . . . . . . . . . . . . . 0°C to +70°CIndustrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°CStorage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°CVapour Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingsfor extended periods may affect device reliability.
Table I. Transmitting
INPUTS OUTPUTRE DE DI B A
X 1 1 0 1X 1 0 1 0X 0 X Z Z
Table II. Receiving
INPUTS OUTPUTRE DE A-B RO
0 0 ≥ +0.2 V 10 0 ≤ –0.2 V 00 0 Inputs Open 11 0 X Z
PIN FUNCTION DESCRIPTION
Pin Mnemonic Function
1 RO Receiver Output. When enabled if A > B by200 mV, then RO = High. If A < B by200 mV, then RO = Low.
2 RE Receiver Output Enable. A low level enablesthe receiver output, RO. A high level places itin a high impedance state.
3 DE Driver Output Enable. A high level enablesthe driver differential outputs, A and B. Alow level places it in a high impedance state.
4 DI Driver Input. When the driver is enabled alogic Low on DI forces A low and B highwhile a logic High on DI forces A high and Blow.
5 GND Ground Connection, 0 V.
6 A Noninverting Receiver Input A/DriverOutput A.
7 B Inverting Receiver Input B/Driver Output B.
8 VCC Power Supply, 5 V ± 5%.
PIN CONFIGURATION
RO
RE
DE
DI GND
A
B
VCC
1
2
3
4
8
7
6
5
TOP VIEW(Not to Scale)
ADM485
ORDERING GUIDE
Model Temperature Range Package Option
ADM485JN 0°C to +70°C N-8ADM485JR 0°C to +70°C SO-8ADM485AN –40°C to +85°C N-8ADM485AR –40°C to +85°C SO-8ADM485AQ –40°C to +85°C Q-8
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe ADM485 features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ADM485
REV. A–4–
Test Circuits
R
R VOC
VOD
Figure 1. Driver Voltage Measurement Test Circuit
375Ω
VOD3 V
TST
375Ω
60Ω
Figure 2. Driver Voltage Measurement Test Circuit 2
A
B
RLDIFF
CL1
CL2
Figure 3. Driver Propagation Delay Test Circuit
VOUTC
L
A
B
VCC
S2
RL
S10V OR 3V
DE IN
DE
Figure 4. Driver Enable/Disable Test Circuit
CL
VOUTRE
A
B
Figure 5. Receiver Propagation Delay Test Circuit
VOUT
VCC
S2
RL
S1
RE IN
REC
L
+1.5V
–1.5V
Figure 6. Receiver Enable/Disable Test Circuit
TPLH
TPHL
0V 0V
1.5V 1.5V
A–B
RO
VOL
VOH
Figure 9. Receiver Propagation Delay
TZH
1.5V 1.5V
3V
0V
1.5V
THZ
VOH
VOH
– 0.5V
0V
R
VOL
+ 0.5V
TZL
1.5V
TLZ
VOL
R
RE
O/P LOW
O/P HIGH
Figure 10. Receiver Enable/Disable Timing
Switching Characteristics
–VO
VO1/2VO
0V
3V
1.5V 1.5V
TPLH
TSKEW
VO
0V
90% POINT
10% POINT
90% POINT
10% POINT
TPHL
B
AT
SKEW
TR
TF
Figure 7. Driver Propagation Delay, Rise/Fall Timing
TZH
1.5VDE 1.5V
3V
0V
2.3V
THZ
VOH
VOH
– 0.5V
0V
A, B
VOL
+ 0.5V
TZL
2.3V
TLZ
VOL
A, B
Figure 8. Driver Enable/Disable Timing
Typical Performance Characteristics–ADM485
REV. A –5–
40
02.0
12
4
8
0.0
24
16
20
28
32
36
1.00.5 1.5OUTPUT VOLTAGE – Volts
OU
TP
UT
CU
RR
EN
T –
mA
Figure 11. Receiver Output LowVoltage vs. Output Current
0.4
0.1–50 125
0.3
0.2
–25 50 100250 75TEMPERATURE – °C
OU
TP
UT
VO
LT
AG
E –
Vo
lts I = 8mA
Figure 14. Receiver Output LowVoltage vs. Temperature
100
04
30
10
20
0
60
40
50
70
80
90
21 3OUTPUT VOLTAGE – Volts
OU
TP
UT
CU
RR
EN
T –
mA
Figure 17. Driver Output LowVoltage vs. Output Current
OUTPUT VOLTAGE – Volts
OU
TP
UT
CU
RR
EN
T –
mA
0
–205.0
–14
–18
–16
3.5
–8
–12
–10
–6
–4
–2
4.54.0
Figure 12. Receiver Output HighVoltage vs. Output Current
OUTPUT VOLTAGE – Volts
OU
TP
UT
CU
RR
EN
T –
mA
96
0
24
12
0
48
36
60
72
84
4321
Figure 15. Driver Differential Out-put Voltage vs. Output Current
0
–1005
–70
–90
–80
0
–40
–60
–50
–30
–20
–10
32 41OUTPUT VOLTAGE – Volts
OU
TP
UT
CU
RR
EN
T –
mA
Figure 18. Driver Output HighVoltage vs. Output Current
5.0
4.5125
4.8
4.6
–25
4.7
–50
4.9
1007550250TEMPERATURE – °C
OU
TP
UT
VO
LT
AG
E –
Vo
lts
I = 8mA
Figure 13. Receiver Output HighVoltage vs. Temperature
2.4
2.0–50 125
2.3
2.1
–25
2.2
1007550250
TEMPERATURE – °CD
IFF
ER
EN
TIA
L V
OL
TA
GE
– V
olt
s
Figure 16. Driver Differential OutputVoltage vs. Temperature, RL = 54 Ω
1.00
0.60125
0.70
0.65
–25–50
0.80
0.75
0.85
0.90
0.95
1007550250TEMPERATURE – °C
SU
PP
LY
CU
RR
EN
T –
mA DRIVER ENABLED
DRIVER DISABLED
Figure 19. Supply Current vs.Temperature
5
0125
3
1
–25
2
–50
4
1007550250TEMPERATURE – °C
TIM
E –
ns
Figure 20. Receiver tPLH–tPHL, vs.Temperature
10
90
100
0%
500mV
5ns
500mV
Figure 23. Loaded DriverDifferential Outputs
ADM485–Typical Performance Characteristics
REV. A–6–
1.0
0.4
0.7
0.5
0.6
0.9
0.8
125–25–50 1007550250TEMPERATURE – °C
TIM
E –
ns
Figure 21. Driver Skew vs.Temperature
10
90
100
0%
1 V
5 5 10ns HO
1 V
Figure 24. Driver/Receiver Propa-gation Delays Low to High
10
90
100
0%
1 V
5ns
1 V
Figure 22. Unloaded DriverDifferential Outputs
10
90
100
0%
1 V
5 5 10ns HO
1 V
Figure 25. Driver/Receiver Propaga-tion Delays High to Low
RT RT
D
R
DR
DR
R
D
Figure 26. Typical RS-485 Network
ADM485
REV. A –7–
APPLICATIONS INFORMATIONDifferential Data TransmissionDifferential data transmission is used to reliably transmit data athigh rates over long distances and through noisy environments.Differential transmission nullifies the effects of ground shiftsand noise signals which appear as common-mode voltageson the line. There are two main standards approved by theElectronics Industries Association (EIA) which specify the elec-trical characteristics of transceivers used in differential datatransmission.
The RS-422 standard specifies data rates up to 10 MBaud andline lengths up to 4000 ft. A single driver can drive a transmis-sion line with up to 10 receivers.
In order to cater for true multipoint communications, theRS-485 standard was defined. This standard meets or exceedsall the requirements of RS-422 but also allows for up to 32drivers and 32 receivers to be connected to a single bus. Anextended common-mode range of –7 V to +12 V is defined. Themost significant difference between RS-422 and RS-485 is thefact that the drivers may be disabled thereby allowing more thanone (32 in fact) to be connected to a single line. Only one drivershould be enabled at time, but the RS-485 standard containsadditional specifications to guarantee device safety in the eventof line contention.
Cable and Data RateThe transmission line of choice for RS-485 communications is atwisted pair. Twisted pair cable tends to cancel common-modenoise and also causes cancellation of the magnetic fields gener-ated by the current flowing through each wire, thereby, reducingthe effective inductance of the pair.
The ADM485 is designed for bidirectional data communica-tions on multipoint transmission lines. A typical applicationshowing a multipoint transmission network is illustrated in Fig-
ure 26. An RS-485 transmission line can have as many as 32 trans-ceivers on the bus. Only one driver can transmit at a particular timebut multiple receivers may be enabled simultaneously.
As with any transmission line, it is important that reflections areminimized. This may be achieved by terminating the extremeends of the line using resistors equal to the characteristic imped-ance of the line. Stub lengths of the main line should also bekept as short as possible. A properly terminated transmissionline appears purely resistive to the driver.
Thermal ShutdownThe ADM485 contains thermal shutdown circuitry which pro-tects the part from excessive power dissipation during fault con-ditions. Shorting the driver outputs to a low impedance sourcecan result in high driver currents. The thermal sensing circuitrydetects the increase in die temperature and disables the driveroutputs. The thermal sensing circuitry is designed to disable thedriver outputs when a die temperature of 150°C is reached. Asthe device cools, the drivers are reenabled at 140°C.
Propagation DelayThe ADM485 features very low propagation delay ensuringmaximum baud rate operation. The driver is well balanced en-suring distortion free transmission.
Another important specification is a measure of the skew be-tween the complementary outputs. Excessive skew impairs thenoise immunity of the system and increases the amount of elec-tromagnetic interference (EMI).
Receiver Open-Circuit Fail SafeThe receiver input includes a fail-safe feature which guaranteesa logic high on the receiver when the inputs are open circuit orfloating.
Table III. Comparison of RS-422 and RS-485 Interface Standards
Specification RS-422 RS-485
Transmission Type Differential DifferentialMaximum Cable Length 4000 ft. 4000 ft.Minimum Driver Output Voltage ±2 V ±1.5 VDriver Load Impedance 100 Ω 54 ΩReceiver Input Resistance 4 kΩ min 12 kΩ minReceiver Input Sensitivity ±200 mV ±200 mVReceiver Input Voltage Range –7 V to +7 V –7 V to +12 VNo of Drivers/Receivers Per Line 1/10 32/32
ADM485
REV. A–8–
C18
17–0
–5/0
0 (r
ev. A
) 00
078
PR
INT
ED
IN U
.S.A
.
OUTLINE DIMENSIONSDimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
0.0098 (0.25)0.0075 (0.19)
0.0500 (1.27)0.0160 (0.41)
80
0.0196 (0.50)0.0099 (0.25)
45
8 5
41
0.1968 (5.00)0.1890 (4.80)
0.2440 (6.20)0.2284 (5.80)
PIN 1
0.1574 (4.00)0.1497 (3.80)
0.0500 (1.27)BSC
0.0688 (1.75)0.0532 (1.35)
SEATINGPLANE
0.0098 (0.25)0.0040 (0.10)
0.0192 (0.49)0.0138 (0.35)
8-Lead Plastic DIP (N-8)
PIN 10.280 (7.11)0.240 (6.10)
4
58
1
SEATINGPLANE
0.060 (1.52)0.015 (0.38)
0.130(3.30)MIN
0.210(5.33)MAX
0.160 (4.06)0.115 (2.93)
0.430 (10.92)0.348 (8.84)
0.022 (0.558)0.014 (0.356)
0.070 (1.77)0.045 (1.15)
0.100(2.54)BSC
0.325 (8.25)0.300 (7.62)
0.015 (0.381)0.008 (0.204)
0.195 (4.95)0.115 (2.93)
8-Lead Cerdip (Q-8)
0.320 (8.13)0.290 (7.37)
0.015 (0.38)0.008 (0.20)
15°0°
0.005 (0.13) MIN 0.055 (1.4) MAX
1
PIN 1
4
58
0.310 (7.87)0.220 (5.59)
0.405 (10.29) MAX
0.200 (5.08)
MAX
SEATINGPLANE
0.023 (0.58)0.014 (0.36)
0.070 (1.78)0.030 (0.76)
0.060 (1.52)0.015 (0.38)
0.150(3.81)MIN
0.200 (5.08)0.125 (3.18)
0.100(2.54)BSC
1 2 3 4 5 6
A
B
C
D
654321
D
C
B
A
Scale Sheet
Size FCSM No. DWG No. Rev
1 of 1
B 1 A
A BRAND NEW WORLD Polska Sp. z o. o.ul. Swietojanska 75/481-389 Gdynia
Power load simulator
G7/CKO1
CKI2
L0/LOSCI3
L1/LOSCO4
L2/TX5
L3/RX6
L4/T2A7
L5/T2B8
L6/T3A9
L7/T3B10
B2/AD1011
B3/AD1112
B4/AD1213
B5/AD1314 B6/AD14 15B7/AD15 16DGND 17AGND 18AVCC 19DVCC 20RESET 21G0/INT 22G1/WD 23G2/T1B 24G3/T1A 25G4/SO 26G5/SK 27G6/SI 28U1
COP8AME GND
U2 LTV702
U3 LTV702
D11N41481
2345678
JP2
RS PLUG
12345678
JP1
RS SOCKET
R1
6k8
R2
6k8
R4
10k
R10
820
R14
100k
R88k2
R98R2
48
2
31
U7A
LM358
5
67
48
U7B
LM358
+ C7
10u
+ C9100u
GND
GND
V16
V16
R16
5k6
Rsensor0.1/5W
R170.2/5W
R20
220
R18
3k3
R19
100
Q1IRFP150
GND
1 3
2
V V
ADJ
IN OUT
U5 LM3171 3
2
V V
GNDIN OUT
U6 78L05
162738495
J1
DB9S
162738495
J2
DB9P
GND_PC
D2
GRN
D3
RED
PWR12
JP3
J2S
12
JP4
J2P
GND
F1
6.3A
DS1FAN
Q2BUZ10
1 3
2
V V
ADJ
IN OUT
U4 LM317
R15100k
R36k8
R12
560
GND
VCC
VCC
D4
1N4007
C4u1
C5u1
C6u1
C3u1
R6
47k
R7
8k2GND
R13
10
R11
RES2
R5
1k5
C222p
C122p
Y1 10MHz
GND
VCCV16
PWM
PWM
LEDR
LEDRLEDG
LEDG
FAN
FAN
VOLT
VOLT
CRNT
CRNT
TX
TX
RX
RX
VCC
+ C8100u
D5
1N4007GND
1
2
3
4 5
6
7
8IC1
ICL7660
162738495
J11
DB9 SOCKET
162738495
J12
DB9 PLUG
PC SIMULATOR
D1 1N4148
D2 1N4148
D3 1N4148
+ C1
10u
+
C310u
+ C2
10u
GND
GND
GND
+VCC
-VCC
GND
