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Published in IET Microwaves, Antennas & Propagation Received on 3rd December 2007 Revised on 8th June 2008 doi: 10.1049/iet-map.2007.0307 ISSN 1751-8725 Analysis and design of high-efficiency variable conduction angle Doherty amplifier S. Bousnina Ecole Polytechnique de Montre ´al, Poly-Grames Research Center, Montre ´al, Canada S. Bousnina is currently a Senior RF Design Engineer at Tyco Electronics, Torrance, CA E-mail: [email protected] Abstract: The Doherty amplifier was first proposed to improve the efficiency under output power back-off using the technique of load-line modulation of a ‘carrier’ amplifier through a ‘peak’ amplifier. By varying input bias of the peak amplifier along with load of the carrier amplifier at low drive levels, different topologies of the Doherty amplifier are distinguished. An analytical analysis that determines the optimum output performance of these topologies in terms of output power, efficiency and output power back-off ensuring a near-peak efficiency is developed. The presented comprehensive analysis considered for variation of conduction angle of the peak amplifier biased class C. New design equations of the analysed topologies are derived. A realisation at a central frequency of 1.9 GHz using GaAs field effect transistor (FET) devices of a Doherty amplifier topology is reported. In this topology the carrier operates (at low drive levels) into load impedance 5/2 times larger than its optimum. Power-added efficiency of 61.8% is measured at P 1dB of 25.9 dB m and 33.2% is measured at 9 dB back-off from P 1dB . Nomenclature G m transconductance of the FET device I max maximum drain current of the carrier and peak amplifiers P out instantaneous output power of the Doherty amplifier P out_L_max maximum output power of the Doherty amplifier topology at the first saturation of the carrier amplifier P out_max maximum output power of the Doherty amplifier topology in the general case P out_max_ST maximum output power of the Doherty amplifier in the case of the standard topology R L load of the Doherty amplifier R opt optimum load of the carrier and peak amplifiers V d max maximum drain voltage of the carrier and peak amplifiers V gs-bias-carrier gate bias voltage of the carrier amplifier V gs-bias-peak gate bias voltage of the peak amplifier V out output voltage in the terminals of the load R L V p pinch-off voltage of the FET device Z c characteristic impedance of the quarter-wave transformer Z peak impedance presented to the peak amplifier Z carrier impedance presented to the carrier amplifier a the transition point where the peak amplifier turns on (equal to the ratio of the optimum load R opt to the impedance of the carrier amplifier Z carrier at low drive levels) h Instantaneous efficiency of the Doherty amplifier h max efficiency of the Doherty amplifier at maximum drive level u conduction angle of the peak amplifier 416 IET Microw. Antennas Propag., 2009, Vol. 3, Iss. 3, pp. 416–425 & The Institution of Engineering and Technology 2009 doi: 10.1049/iet-map.2007.0307 www.ietdl.org Authorized licensed use limited to: King Fahd University of Petroleum and Minerals. Downloaded on April 23,2010 at 16:29:34 UTC from IEEE Xplore. Restrictions apply.

Doherty Amplifier

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amplifier, class C, class B, GaAs FET, efficiency, linearity

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Published in IET Microwaves, Antennas & PropagationReceived on 3rd December 2007Revised on 8th June 2008doi: 10.1049/iet-map.2007.0307

ISSN 1751-8725

Analysis and design of high-efficiency variableconduction angle Doherty amplifierS. Bousnina†Ecole Polytechnique de Montreal, Poly-Grames Research Center, Montreal, Canada†S. Bousnina is currently a Senior RF Design Engineer at Tyco Electronics, Torrance, CAE-mail: [email protected]

Abstract: The Doherty amplifier was first proposed to improve the efficiency under output power back-off using thetechnique of load-line modulation of a ‘carrier’ amplifier through a ‘peak’ amplifier. By varying input bias of the peakamplifier along with load of the carrier amplifier at low drive levels, different topologies of the Doherty amplifier aredistinguished. An analytical analysis that determines the optimum output performance of these topologies in termsof output power, efficiency and output power back-off ensuring a near-peak efficiency is developed. The presentedcomprehensive analysis considered for variation of conduction angle of the peak amplifier biased class C. Newdesign equations of the analysed topologies are derived. A realisation at a central frequency of 1.9 GHz usingGaAs field effect transistor (FET) devices of a Doherty amplifier topology is reported. In this topology the carrieroperates (at low drive levels) into load impedance 5/2 times larger than its optimum. Power-added efficiency of61.8% is measured at P1dB of 25.9 dB m and 33.2% is measured at 9 dB back-off from P1dB.

T

u

NomenclatureGm transconductance of the FET device

Imax maximum drain current of the carrier andpeak amplifiers

Pout instantaneous output power of the Dohertyamplifier

Pout_L_max maximum output power of the Dohertyamplifier topology at the first saturation ofthe carrier amplifier

Pout_max maximum output power of the Dohertyamplifier topology in the general case

Pout_max_ST maximum output power of the Dohertyamplifier in the case of the standardtopology

RL load of the Doherty amplifier

Ropt optimum load of the carrier and peakamplifiers

Vdmaxmaximum drain voltage of the carrier andpeak amplifiers

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Vgs-bias-carrier gate bias voltage of the carrier amplifier

Vgs-bias-peak gate bias voltage of the peak amplifier

Vout output voltage in the terminals of the loadRL

Vp pinch-off voltage of the FET device

Zc characteristic impedance of the quarter-wavetransformer

Zpeak impedance presented to the peak amplifier

Zcarrier impedance presented to the carrieramplifier

a the transition point where the peakamplifier turns on (equal to the ratio of theoptimum load Ropt to the impedance ofthe carrier amplifier Zcarrier at low drivelevels)

h Instantaneous efficiency of the Dohertyamplifier

hmax efficiency of the Doherty amplifier atmaximum drive level

u conduction angle of the peak amplifier

ET Microw. Antennas Propag., 2009, Vol. 3, Iss. 3, pp. 416–425doi: 10.1049/iet-map.2007.0307

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1 IntroductionThe need for high-efficiency and linear microwave poweramplifiers has grown rapidly, especially as mobile andsatellite communication systems have been developed andexpanded [1]. These systems mandate that the amplifierefficiency be as high as possible in order to extend theoperating time of portable power sources. For acceptablelinearity in handling multi-carrier signals with highpeak-to-average envelope ratios, the amplifier output powermust be backed off from its peak value. This has thedisadvantage of reducing the amplifier efficiency andincreasing energy consumption. Such trade-off betweenlinearity and efficiency was difficult to solve withconventional amplifiers. One of the promising techniquesto improve the efficiency under output power back-off isload-line modulation technique used in the Dohertyamplifier [2, 3].

A simplified block diagram of the Doherty amplifier adoptedin this work is shown in Fig. 1. Amplifier 1 is referred to as the‘carrier’ amplifier and it is biased class B. Amplifier 2 is referredto as the ‘peak’ amplifier and it is biased class C. Theinput power is divided equally with a quarter-wave delay atthe input of the peak amplifier. The output power fromthe two amplifiers is combined with a quarter-waveimpedance transformer (with characteristic impedance Zc).Thus, the output signals of the two amplifiers are combinedin phase.

The Doherty amplifier could be realised using class Boperating condition for both carrier and peak amplifiers.However, in this case an additional control circuitry isrequired to turn on the peak amplifier only at the requiredinput power level. Such additional control circuitryincreases the complexity of the implementation and reducesthe overall system efficiency.

Theoretical analysis of the Doherty amplifier is importantfor system-level estimation of its capabilities in terms ofoutput power, efficiency and output power back-off. Inaddition, determination of the impedance (Zc) of thequarter-wave transmission line and the optimum load (RL)

Figure 1 Configuration of the Doherty amplifier withoutinput drive controller

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are critical parameters in the circuit design of this amplifier.Previous realisations of the Doherty amplifier withpromising results in terms of linearity and efficiency werereported in [4–15]. Most of the realised topologies of theDoherty amplifier were designed on the basis of the designequations reported in [3]. However, these design equationsare derived assuming that both carrier and peak amplifiersare biased class B and a drive controller is used to turn onthe peak amplifier when the input drive exceeds certainthreshold. Therefore the derived design equations andtheoretical performance of the Doherty amplifier are notoptimum when no drive controller is used and instead, asdone in most of the reported realisations, the peakamplifier is biased class C.

In this paper, the term topology of the Doherty amplifier isa synonym to configuration of this amplifier where the peakamplifier biased class C turns on only at specific level ofinput drive. A given topology of the Doherty amplifier isdistinguished from other one by the specific bias of thepeak amplifier and by the specific values of the load RL andcharacteristic impedance Zc.

This paper presents a comprehensive analysis of thecharacteristics of the topologies of the Doherty amplifier.Variation of the conduction angle of the peak amplifier isconsidered in the derivation of these characteristics. Thepresented analysis leads to a new estimation for eachtopology of the corresponding maximum output power,maximum efficiency and maximum output power back-offensuring a near-peak efficiency. In addition, new designequations for the determination of the load RL andcharacteristic impedance Zc are derived for each topology.

This paper is organised as follows: In Section 2, theoreticaloutput performance of the Doherty amplifier topologies isdetermined and new design equations of theses topologiesare presented. The design and measurement of the realisedDoherty amplifier topology are presented and discussed inSection 3. Conclusions are given in Section 4.

2 Theoretical analysis of theDoherty amplifier topologiesThe objectives of the analysis presented in this section are thedetermination of the optimum output performance of theDoherty amplifier topologies and the proposal of newdesign equations for each topology.

In this paper, the term standard Doherty amplifiertopology refers to the original configuration of thisamplifier reported in [2]. In this configuration, both carrierand peak amplifiers are biased class B and each of themcontributes equally to the output power at maximum inputdrive. In this configuration, a control circuitry is required toturn on the peak amplifier only at the required input powerlevel.

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The parameters a and Zc are defined as follows:

a ¼Ropt

(Zcarrier)at low drive levels

(1)

Zc ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiRoptRL

a

r(2)

2.1 Doherty amplifier topologies withoutinput drive controller

For simplicity purposes, subsequent analysis is based uponclass B and class C amplifiers with resistive loads andidentical ideal DC characteristics. Ideal filters areassumingly used at the output of each of the peak andcarrier amplifiers to filter odd and even harmonics whenpresenting an open circuit for the fundamental signal.

It is easy to understand the principle of operation of theDoherty amplifier in its two stages of operation dependingon the level of the input drive. In the first stage, the drivelevel is so low such that the peak amplifier remains off.Consequently, only the carrier amplifier amplifies the inputsignal. In the second stage, the drive level is high andexceeds certain threshold level allowing the peak amplifierto turn on. As deduced from the analysis reported in [3],the expressions describing the characteristics andperformance of the Doherty amplifier are presented inAppendix.

2.1.1 Low input drive levels: At low input drive levels,the carrier amplifier operates into a load equal to Ropt/a.Fig. 2 shows the load-line and waveform of the draincurrent of the carrier amplifier.

In Fig. 2, Ic_cri is defined as a critical value of the draincurrent of the carrier amplifier when this amplifier reachesits first saturation. As illustrated in this figure, thefollowing relation is deduced:

Ic cri

Imax

¼Ropt

Ropt=a¼ a

Figure 2 Current and voltage waveforms and load-lines ofthe carrier amplifier

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Thus

Ic cri ¼ aImax (3)

The carrier amplifier is biased class B:

Vgs-bias-carrier ¼ �jVpj (4)

The peak amplifier is biased class C and it turns on when thedrain current of the carrier amplifier reaches Ic_cri:

Vgs-bias-peak ¼ �jVpj �Ic cri

Gm

¼ �jVpj �aImax

Gm

(5)

2.1.2 High input drive levels: At high input drive levelsand as the power delivered by the peak amplifier increases,the load presented to the carrier amplifier decreases. Sincethe peak amplifier is biased class C, the variation of itsconduction angle (shown in Fig. 3) has to be considered inthe calculation of the performance of the Doherty amplifiertopologies.

As shown in Fig. 3, the drain current of the peak amplifieris expressed as follows:

Id-peak ¼ IA cos u 0 � cosu

2

� �(6)

with

IA ¼Ik

1� cos ðu=2Þ(7)

From Fourier analysis of the waveform of the drain current ofthe peak amplifier, the fundamental component is given by

Id-peak-fund ¼IA

2p(u� sin u) (8)

Figure 3 Waveform and conduction angle of the draincurrent of the peak amplifier

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The DC component is given by

Idc-peak ¼Ik

2p

2 sin (u=2)� u cos (u=2)

1� cos (u=2)

� �(9)

Fig. 4 shows the voltage and current waveforms and thetransfer characteristics of the peak and carrier amplifiers.

In Fig. 4, Ic_max is defined as the peak value of the draincurrent of the carrier amplifier at any high drive level.Ip_max is defined as the peak value of the drain current ofthe peak amplifier at any high drive level.

Figure 4 Current and voltage waveforms of the carrier (top)and peak (bottom) amplifiers

Figure 5 Maximum conduction angle of the peak amplifierfor different topologies of the Doherty amplifier

Microw. Antennas Propag., 2009, Vol. 3, Iss. 3, pp. 416–425i: 10.1049/iet-map.2007.0307

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As illustrated in Fig. 4 and at maximum input power, thefollowing relation is deduced:

Ip max ¼ Imax � Ic cri

Using (3), the following relation is deduced:

Ip max ¼ (1� a)Imax (10)

At maximum input power IA is equal to Imax, and Ik is equalto Ip_max:

u ¼ umax (at maximum input power) (11)

IA ¼ Imax (12)

Ik ¼ Ip max (13)

From (7), (10), (12) and (13), the maximum conductionangle of the drain current of the peak amplifier can bedetermined as a function of a:

umax ¼ 2 cos�1 (a) (14)

As shown in Fig. 5 and by (5), the conduction angle of thepeak amplifier is maximised only when this amplifier isbiased closer to the pinch-off voltage.

Imax is defined as a function of the maximum drain voltageand optimum load as follows:

Imax ¼Vdmax

Ropt

(15)

Using (10), (13) and (15), the following relation is deduced:

Ik ¼ (1� a)Vdmax

Ropt

(16)

Using (8) and (16), the expression of the fundamental currentof the peak amplifier can be written as

Id-peak-fund ¼ (1� a)Vdmax

2pRopt

umax � sin umax

1� cos (umax=2)

� �(17)

Using (17) and (43), the impedance presented to the peakamplifier is given by:

Zpeak ¼Vdmax

2Id-peak-fund

¼pRopt

(1� a)[(umax � sin umax)

=(1� cos (umax=2))]

(18)

At maximum drive level, the DC current of the carrieramplifier is given by

Idc-carrier ¼2

p

(Vdmax=2)

Zcarrier

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