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DLP Pico Chipset v2 Programmers Guide

User's Guide

Literature Number: DLPU002A

February 2010 Revised July 2010

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2 DLPU002A February 2010 Revised July 2010

Copyright 2010, Texas Instruments Incorporated

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Contents

Preface ....................................................................................................................................... 5

1 Interface Protocol ................................................................................................................ 71.1 Projector Control I2C Commands ......................................................................................... 7

1.1.1 Slave Receive Mode (Write to Chipset) ......................................................................... 71.1.2 Slave Transmit Mode (Read from Chipset) ..................................................................... 81.1.3 Reserved Areas .................................................................................................... 8

1.2 I2C Interface .................................................................................................................. 91.2.1 I2C Control Commands ............................................................................................ 91.2.2 I2C Alternate Address Select Pin ................................................................................. 91.2.3 Momentary Image Corruption During Command Writes ...................................................... 9

1.3 I2C Projector Control Commands ......................................................................................... 91.3.1 Configuration Register Projector Control Commands ......................................................... 91.3.2 Color Coordinate Adjustment (CCA) Command/Field Definitions .......................................... 211.3.3 Structured Light Control Command/Field Definitions ........................................................ 241.3.4 LED Color Mask Command/Field Definitions ................................................................. 251.3.5 Structured Light Control Command/Field Definitions (continued) .......................................... 261.3.6 Internal Pattern Structured Light Command/Field Definitions .............................................. 271.3.7 Options for Input Image Resolutions/Orientations and DMD Displayed Images ......................... 33

2 Powerup and Powerdown Considerations ............................................................................ 392.1 Powerup .................................................................................................................... 392.2 Powerdown ................................................................................................................. 39

3 Command Quick Reference ................................................................................................ 41

3DLPU002A February 2010 Revised July 2010 Contents


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www.ti.com

List of Figures

1-1. I2C Interface Write Register................................................................................................ 81-2. I2C Interface Read Register................................................................................................ 81-3. Portrait QVGA to HVGA .................................................................................................. 331-4. Portrait HVGA to HVGA .................................................................................................. 341-5. Portrait VGA to HVGA .................................................................................................... 351-6. Landscape QVGA to HVGA.............................................................................................. 361-7. Landscape HVGA to HVGA.............................................................................................. 361-8. Landscape VGA to HVGA................................................................................................ 371-9. Landscape NTSC to HVGA .............................................................................................. 371-10. Landscape PAL/SECAM to HVGA ...................................................................................... 381-11. Landscape VGA Cropped to HVGA (Not Scaled)..................................................................... 38

List of Tables

3-1. ............................................................................................................................... 41

4 List of Figures DLPU002A February 2010 Revised July 2010


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PrefaceDLPU002AFebruary 2010Revised July 2010

Read This First

About This Manual

This document specifies the command and control interface to the Pico Chipset. It defines all applicablecommands, default settings, and control register bit definitions to communicate with the Pico Chipset.

Input Format

DVI-D interface

Pixel clock: 27 MHz

Pixel format: RGB888

Reference Documents

DLPC100 DLP Pico Processor Datasheet, DLPS019

Using Pico 2.0 Kit for Structured Light Applications, DLPA021

DLP is a registered trademark of Texas Instruments.Pico is a trademark of others.

5DLPU002A February 2010 Revised July 2010 Read This First

http://www.ti.com/lit/pdf/dlps019http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlps019

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6 Read This First DLPU002A February 2010 Revised July 2010


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Chapter 1DLPU002AFebruary 2010Revised July 2010

Interface Protocol

The I2C protocol used in communicating information to the Pico Chipset consists of a serial data busconforming to the Philips I2C specification, up to 400 KHz. The I2C interface timing waveforms are shownin Figure 1-1 and Figure 1-2. The chipset operates as an I2C F/S mode slave.

1.1 Projector Control I2C Commands

The I2C Addresses for projector control are 8 bits, followed by an 8-bit sub-address. The address and/orsubaddress are followed by either writing or reading 32 bits of data. The protocols for I 2C projector controlread and write are listed below.

Write Command:

Address Sub-Address Data

(8-bit) (8-bit) (32-bit)

x36 xAA DDDDDDDDh (AAh = Register Address, DDDDDDDDh =write data)

Read Command:

Address Sub-Address Data

(8-bit) (8-bit) (8-bit)

x36 x15 xxh (address of Read Part 1 (Write address of requestedreg.) register)

(8-bit) (32-bit)

x37 XXXXXXXXh Read Part 2 (Read data of requested register)

1.1.1 Slave Receive Mode (Write to Chipset)

With the Pico Chipset operating in the slave-receiver configuration, the first byte following the startcondition is the Pico device write address (ex. 36h). The interface consists of a number of sub-addressregisters, each capable of accepting multiple bytes of data. Each command/sub-address expects a certainnumber of data bytes, typically 4. The number of data bytes for each command/sub-address is describedin Section 1.1.

Writing to registers is performed with a single series of bus transactions, preceded by exactly one start

condition (S) and terminated by exactly one stop condition (P). All register write transactions must includeone byte for the sub-address and 4 bytes for data.

An example of a register write to device address x36, sub-address x04 with data x00000000 would be asfollows:

S 36 04 00 00 00 00 P

7DLPU002A February 2010 Revised July 2010 Interface Protocol


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SCL

SDA 0x36 0x04 0x000x00 0x00 0x00

SCL

SDA 0x37 0x00 0x000x00 0x00

SDA 0x36 0x15 0x04

SCL

Projector Control I2C Commands www.ti.com

Figure 1-1. I2C Interface Write Register

1.1.2 Slave Transmit Mode (Read from Chipset)

Reading from registers is accomplished with a two-step process of writing (via I2C address x36) to aspecific sub-address containing the register address pointer (sub-address x15), then reading up to 4 byteson a subsequent read transaction (from I2C address x37). Once the register sub-address pointer iswritten, the Pico Chipset is ready for a read operation in the slave-transmitter mode. To read from theselected register, another I2C start condition is issued by the master, followed by the pico chipset readaddress (37h). The slave will follow with up to four bytes of read data, in response to SCL clocks driven bythe master device. The master device must then issue a stop condition to properly terminate the register

read access.

A full two-step read transaction would follow this format:

For the specific example of reading from register x04 that has data x00000000, the bus data wouldbe:

S 36 15 04 P

S 37 00 00 00 00 P

Figure 1-2. I2C Interface Read Register

1.1.3 Reserved Areas

When writing to valid registers, all unused/reserved bits should be set to zero unless specified otherwise.Reserved registers should never be written to or read from. When reading non-reserved registers, allunused and/or reserved bits should be explicitly ignored (i.e., read values of reserved bits may vary).

8 Interface Protocol DLPU002A February 2010 Revised July 2010


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www.ti.com I2C Interface

1.2 I2C Interface

1.2.1 I 2C Control Commands

I2C addresses 36h and 37h are used to issue control commands to the chipset. These control commands,register sub-addresses and corresponding control bits are specified below. Control commands may beissued in any order by the I2C bus master.

1.2.2 I 2C Alternate Address Select Pin

The I2C_ADDR_SEL pin can select an alternate set of I2C device addresses. If I2C_ADDR_SEL pin islow, then 36h/37h are enabled. If I2C_ADDR_SEL pin is high, then 3Ah/3Bh are enabled.

1.2.3 Momentary Image Corruption During Command Writes

Note that certain commands may cause brief visual artifacts in the display image under somecircumstances. (Command data values may be read without impacting projected image.) In practice, thismomentary corruption due to command writes can be easily masked at the system level by disabling theLEDs prior to the command write, then re-enabling after all other commands have been issued.

1.3 I2

C Projector Control Commands

1.3.1 Configuration Register Projector Control Commands

The following tables list the supported configuration registers and control commands. In the Typecolumn, wr type is writeable. Data can also be read back through the I2C interface for wr type bits. Typer is read-only.

Type s signifies a special latched status bit. Reading a 1 from an s bit means that the hardware signalassociated with that bit has gone active since the last clear of that status bit. Writing a 1 to an s bitclears the status bit. The bit will then read zero until the next active condition of the hardware associatedwith the status bit.

The Reset column in all of the following command tables is the default value in the command registerimmediately after powerup. These values may be overwritten after powerup.

When writing to valid registers, all bits marked as unused or reserved should be set to zero unlessspecified otherwise.

Registers marked as reserved should not be accessed.



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I2C Projector Control Commands www.ti.com

1.3.1.1 Input Source and Interface Mode (I2C: x04)

When a command x04 is received by the projector, the 32 bits of data define the projector input imagemode.

BIT(S) DESCRIPTION RESET TYPE

2:0 b000 wrSelect the input source and interface mode:

0 - Parallel RGB I/F (1)

1 - Internal test patterns (2)

2 - Splash screen (3)

3 - RESERVED

4 BT.656 format (with embedded syncs)

5-7 RESERVED

15:3 Spare x0000

31:16 Unused

(1) See Pixel Format command (I2C: x06) for supported input pixel format options.(2) Internal test patterns uses command (I2C: x0B) to define the test pattern source and command (I2C:

x05) for resolution. Internal test patterns mode should be selected when using internal stripe patternstructured light modes (see Display Mode command, I2C: x1F).

(3) For Splash screens, Free-run sequence synchronization mode must be used (see Sequence Sync

Mode register, I2C: x24). A pre-determined set of splash screens are stored in the chipset in QVGAlandscape format. Chipset must be set to display in QVGA landscape mode.

1.3.1.2 Input Resolution: (I2C: x05)


3:0 b001 wrSelect the input resolution:

x0 - QVGA portrait (240h*320v)

x1 - QVGA landscape (320h*240v) (1)

x2 - HVGA portrait (320h*480v)

x3 - HVGA landscape (480h*320v)

x4 - VGA portrait (480h*640v)

x5 - VGA landscape (640h*480v) (1)

x6 - NTSC landscape (720h*240v)x7 - VGA landscape (640h*480v) cropped to HVGA (not scaled) (2)

x8 - PAL/SECAM landscape (720h*288v)

x9 - RESERVED

xA+ - RESERVED

15:4 Spare x000

31:16 Unused

(1) Behavior of QVGA landscape and VGA landscape modes are further modified by settings of the AspectRatio Modification command (I2C: x0A).

(2) VGA landscape mode is required for structured light applications to prevent unwanted scaling ofpatterns. In this mode, the chipset expects to see VGA landscape input frame, but then the left and topportions of VGA input image frame are ignored (cropped). This results in only the lower right hand480x320 corner being displayed.

For each of the input resolutions listed, the first parameter is the number of pixels in the horizontal (x-axis)and the second parameter is the number of pixels in the vertical (y-axis).

1.3.1.3 Pixel Format: (I2C: x06)



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DMD

Flip EnabledFlip Disabled

www.ti.com I2C Projector Control Commands


2:0 b010 wrSelect the pixel format:

0 - RGB565 (1)

1 - RGB666 (1)

2 - RGB888 (2)

3+ - RESERVED

15:3 Spare x0000

31:16 Unused

(1) The splash screen interface uses RGB565(2) Internal test patterns and the BT.656 interface use RGB888

1.3.1.4 Image Rotation: (I2C: x07)

When this command is received by the projector, the data defines if the input image is rotated by -90degrees on the DMD. This command is used when the portrait image is to be displayed as landscape.


0 b0 wrImage rotation (only used if input is 'portrait', should be set to 0 ifinput is landscape)

0 - no rotation (center image on DMD and pad w/ black bars)1 - 90 degree rotation (input portrait is scaled and rotated onDMD)

15:1 Spare x0000

31:16 Unused

Section 1.3.7 shows diagrams of the valid image rotation options.

1.3.1.5 Image Flip Long Axis: (I2C: x08)

When this command is received by the projector, the data defines if the input image is flipped across thelong axis of the DMD.


0 b1 wrFlips image along long axis on DMD:

0 - Disable flip

1 - Enable flip

15:1 Spare x0000

31:16 Unused

Long axis flip means this:



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DMD

Flip EnabledFlip Disabled


1.3.1.6 Image Flip Short Axis: (I2C: x09)

When this command is received by the projector, the data defines if the input image is flipped across theshort axis of the DMD.


0 b1 wrFlips image along short axis on DMD:

0 - Disable flip

1 - Enable flip

15:1 Spare x0000

31:16 Unused

Short axis flip means this:

1.3.1.7 DMD Aspect Ratio: (I2C: x0A)

This command modifies the scaling behavior of two specific Input Resolution command (I2C: x05)modes: QVGA Landscape (x1) and VGA Landscape (x5). Based on the value of the aspect ratiomodification command, these two 4:3 aspect ratio input sources are either a) stretched horizontallyslightly to fit the DMDs native 3:2 aspect ratio, or b) displayed in a 427x320 line sub-region of DMD,thereby preserving the 4:3 aspect ratio of the input source. For all other settings of Input Resolutioncommand, this aspect ratio correction command has no effect.


0 b0 wQVGA/VGA Landscape Mode Aspect Ratio Modification:

0 force 4:3 input aspect ratio source to fill 3:2 display

1 preserve 4:3 aspect ratio of source

15:1 Spare x0000

31:16 Unused



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1.3.1.8 Internal Test Patterns: (I2C: x0B)


3:0 b0 wrTest pattern select:

x0 - Checkerboard

x1 - Solid black

x2 - Solid white

x3 - Solid red

x4 - Solid blue

x5 - Solid green

x6 - Vertical lines - 1-white, 7-black

x7 - Horizontal lines - 1-white, 7-black

x8 - Vertical lines - 1-white, 1-black

x9 - Horizontal lines - 1-white, 1-black

xA - Diagonal lines

xB - Vertical Gray Ramps

xC - Horizontal Gray Ramps

xD - 8x8 grid w/ border (1 pixel wide)

xE - 16x16 grid w/ border (1 pixel wide)

xF - 32x32 grid w/ border (1 pixel wide)15:4 Spare x000

31:16 Unused

The test patterns are internally injected into the beginning of the image processing path. Therefore allimage processing is performed on the test images. All command registers should be set up as if the testimages are input from an external source. To achieve single pixel resolution for test images, the InputResolution (I2C: x05) should be set to HVGA landscape (x3).

The test pattern generator (TPG) generates the test patterns such that they mimic the resolution selectedby the Input Resolution command (I2C: x05). For example, if NTSC landscape (720h*240v) is selected,then the TPG will input a 720x240 image into the image processing path.

For typical test pattern usage, these command settings should be used:

Input Source and Interface Mode: (I2C: x04) x1 - Internal Test Patterns

Input Resolution: (I2C: x05)

x3 - HVGA landscape (480h*320v)

Pixel Format: (I2C: x06)

x2 - RGB888

1.3.1.9 Pixel Interface Clock Edge: (I2C: x0C)


0 b1 wrDefines the clock edge (for PCLK) on which pixel data is sampled:

0 - Sample on falling edge

1 - Sample on rising edge

15:1 Spare x0000

31:16 Unused

1.3.1.10 Pixel Interface Sync Polarity: (I2C: x0D)



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0 b0 wrDefines the polarity of the incoming VSYNC signal:

0 Active low pulse

1 Active high pulse

1 b0 wrDefines the polarity of the incoming HSYNC signal:

0 Active low pulse

1 Active high pulse

2 b1 wrDefines the polarity of the incoming DATEN signal:

0 Active low pulse

1 Active high pulse

15:3 Spare x0000

31:16 Unused

1.3.1.11 Red LED Current PWM Output Control: (I2C: x0E)


9:0 x3FF wrRed LED current control PWM output pin duty cycle

Valid range:x000 (0% PWM output pin duty cycle)

to

x3FF (100% PWM output pin duty cycle)

15:10 Spare x00

31:16 Unused

This command directly controls the pulse width of the red LED PWM modulation output pin.

Equation 1 provides the approximate ungated LED current specifically for the light module included in thePico 2.0 kit. The equation is not applicable for other external light modules.

ILED = 70 + 0.74 * (1023 unsigned(PWM(9:0))) mA, rms (1)

Note that choice of display mode also impacts total LED current and average power by gating the LEDon periods during video frames via the R/G/B LED enable pins in the chipset. See Section 1.3.1.18 forfurther details.

Care should be taken when using this command in practice. Depending on many system designdependent factors (including projector thermal design, LED specifications, selected display mode, etc.),recommended and absolute maximum settings will vary.

1.3.1.12 Green LED Current PWM Output Control: (I2C: x0F)


9:0 x3FF wrGreen LED current control PWM output pin duty cycle

Valid range:

x000 (0% PWM output pin duty cycle)

to


15:10 Spare x00

31:16 Unused

This command directly controls the pulse width of the green LED PWM modulation output pin.

Equation 2 provides the approximate ungated LED current specifically for the light module included in thePico 2.0 kit. The equation is not applicable for other external light modules.




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1.3.1.13 Blue LED Current PWM Output Control: (I2C: x10)


9:0 x3FF wrBlue LED current control PWM output pin duty cycle

Valid range:

x000 (0% PWM output pin duty cycle)

to


15:10 Spare x00

31:16 Unused

This command directly controls the pulse width of the blue LED PWM modulation output pin.Equation 3 provides the approximate ungated LED current specifically for the light module included in thePico 2.0 kit. The equation is not applicable for other external light modules.




1.3.1.14 Enable Red LED: (I2C: x11)

When this command is received by the projector, the data defines if the Red LED is enabled.


0 b1 wrEnable red LED:

0 - disable LED / forces LED enable output pin to disable state

1 - enable LED / enable output pin toggles per color field sequentialpattern as determined by Display Mode Select (I2C: x1F) setting

15:1 Spare x0000

31:16 Unused

1.3.1.15 Enable Green LED: (I2C: x12)

When this command is received by the projector, the data defines if the Green LED is enabled.


0 b1 wrEnable green LED:



15:1 Spare x0000

31:16 Unused



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1.3.1.16 Enable Blue LED: (I2C: x13)

When this command is received by the projector, the data defines if the Blue LED is enabled.


0 Enable blue LED: b1 wr



15:1 Spare x0000

31:16 Unused



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1.3.1.17 Degamma Curve Select: (I2C: x1E)

When this command is received by the projector, the chipset will load the selected degamma curveaccording to the table below. If an image is being displayed, momentary image corruption may beobservable while the curve table update is proceeding. Shortly after power on reset, the chipset will loadthe reset default table.


3:0 x0 wrDegamma curve select:

x0 - Degamma curve #1 (1)




x4 to xF - RESERVED

15:4 Spare x000

31:16 Unused

(1) Enhanced Graphics (power on reset default, an s-curve) recommended..(2) Power Law 2.2 (NTSC and also almost identical to sRGB except for very dark shades of colors)(3) Power Law 2.5 (NTSC-like but tends to look better on projectors than Power Law 2.2)(4) Linear (for test and structured light-mode applications. See Using Pico 2.0 Kit for Structured Light

Applications, TI literature number DLPA021, for more details )

1.3.1.18 Display Mode Select: (I2C: x1F)

When this command is received by the projector, the data defines the display mode selected.


3:0 x0 wrNormal Video/Graphics modes:

x0 60 Hz video/graphics, LED duty cycles: R39%, G48%, B13% (1)(2)



x3 50 Hz video/graphics, LED duty cycles: R40,% G45%, B15% (1)(2)

External Pattern Structured Light modes:

x4 120 Hz, 8 bit green only, LED duty cycles: R0%, G100%, B0%

(3)(4)

x5 180 Hz, 7 bit green only, LED duty cycles: R0%, G100%, B0% (3)(4)

x6 1440 Hz, 1 bit green only, LED duty cycles: R0%, G100%, B0% (4)

x7 120 Hz, 4 bit per color, LED duty cycles: R33%, G33%, B33% (4)



Internal Stripe Pattern Structured Light modes:

xA 1200Hz pattern rate, LED duty cycles: R33%, G33%, B33% (4)

xB 2400Hz pattern rate, LED duty cycles: R33%, G33%, B33% (4)

xC-xF RESERVED

15:4 Spare x000

31:16 Unused

(1) The LED duty cycles listed for each mode represent the percentage of net frame time allocated to each LED, determined by sequentialgating of the R/G/B LED enable signals. (For example: R39% means that over a video frame period, 39% of the time the red LED will beenabled, 61% of the time it will be disabled.) To calculate net RMS current, ungated current levels supplied by the LED drive circuitshould be multiplied by this duty cycle percentage for total average current. See Section 1.3.1.11 for more information about controllingLED current.

(2) 60 Hz modes support up to a maximum of 60.3 Hz. 50 Hz modes support up to a maximum of 50.3 Hz. Above these frame rates, subtleimage anomalies may be observable.

(3) When using these 100% green duty cycle modes, Green LED current should be reduced to approximately 45% of the current levelsassociated with Normal Video/Graphics Display Modes (x0-x3 above). This is recommended to maintain similar thermal loading ongreen LED as found in normal modes. See Section 1.3.1.12 for more information about controlling LED current.

(4) These modes are specially designed to enable significant performance enhancements for structured light applications. See Using Pico2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details.


http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021

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1.3.1.19 Sync Mode: (I2C: x24)

When this command is received by the projector, the vertical synchronization method is selected.


0 b0 wrSync mode (1) (2)(3)

0 - Lock to internally generated vertical sync

1 - Lock to incoming vertical sync (frequency of the input source is60Hz or 50Hz)

3:1 Spare b000

31:4 Unused

(1) Generally, when displaying externally generated 50 Hz or 60 Hz sources, lock to incoming sync willproduce the best results. In this mode, display frame reads are synchronous with input write frames.

(2) For input frames less than 50 Hz, or internal splash screens, or internal test patterns, internallygenerated sync mode should be used.

(3) If lock to incoming sync mode is selected but the source does not supply a valid vertical sync signal,the chipset will turn off the LEDs for protection after expiration of a watchdog timer.

1.3.1.20 Splash Image Select: (I2C: x25)

When this command is received by the projector, one of the preloaded splash screen images is selected.

Splash screens are stored in landscape QVGA format.


3:0 x0 wrSplash screen image select

x0 - Splash image #1



x3 to xF - RESERVED

31:4 Unused

To properly display a splash screen image, the following set of command settings should be used inaddition to the image select command above:

Input Source and Interface Mode: (I2C: x04)

x2 - Splash Screen

Input Resolution: (I2C: x05)

x1 - QVGA landscape (320h*240v)

Pixel Format: (I2C: x06)

x0 RGB565

Sync Mode : (I2C: x24)

x0 Lock to internally generated sync

AGC Control: (I2C: x82)

x0 AGC Disabled

When returning to displaying input images from an external source, these registers should besubsequently returned to their original values.

1.3.1.21 Video/Graphics Enhancement Enable: (I2C: x26)

When this command is received by the projector, video/graphics enhancement is turned on or off.Video/graphics enhancement function seeks to visually smooth discrete steps in gradually transitioningshades (such as facial skin tones). Video/graphics enhancement should be disabled for any non-periodicsource or when using one of the structured light modes (see Section 1.3.1.18). Otherwise video/graphicsenhancement should be enabled to maximize image quality.



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0 b0 wrTemporal enhance enable (1)(2)

0 - Disabled

1 - Enabled

3:1 Spare b000

31:4 Unused

(1) Video/graphics enhancement Enable recommended for us in all video/graphics modes to maximizeimage quality.

(2) Video/graphics enhancement should be disabled in all structured light Display Modes. See Using Pico2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details

1.3.1.22 VSYNC DELAY: (I2C: x27)

When this command is received by the projector, an adjustable delay on VSYNC can be added internalto the DLPC100. This delay is sometimes necessary if the vertical front porch in the input video isunusually short.


14:0 x0000 wVSYNC delay time interval (Used to effectively add vertical frontporch to the external video/graphics input timing. Adjustments arein increments of four pixel clocks.)

Valid range is x0000 to x7FFF RESERVED

15 Spare b0

31:16 Unused

1.3.1.23 Structured Light Output Display Inhibit: (I2C: x29)

When this command is received by the projector, DMD output display will stop updating. For internallygenerated structured light patterns, it is necessary to toggle this command to ensure propersynchronization of output strobes. See Using Pico 2.0 Kit for Structured Light Applications, TI literaturenumber DLPA021, for more details.

CAUTION

This command should not be used other than as recommended in theaforementioned application note. Leaving the display in the disabled state for aprolonged periods of time can result in device degradation. However, infrequentshort durations in inhibit state (i.e., much less than one second) are harmless.


0 b1 wStructured light output display inhibit

0 Disable output display processing

1 Enable output display processing

3:1 Spare b000

31:4 Unused

1.3.1.24 Firmware Revision: (I2C: x40)


11:0 Chipset firmware revision (read only) x06C r

31:12 Unused


http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021

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1.3.1.25 Structured Light Non-Linear Processing Inhibit: (I2C: x62)

This command disables certain internal video processing blocks that perform non-linear actions on thevideo path. For normal video, these blocks are necessary to produce visually pleasing images. But, forstructured light applications, it is desirable to have a straight forward linear relationship between projectorinput pixel data bits and light output.


0 b1 wrStructured Light Non-Linear Processing Inhibit (1)

0 Inhibit certain non-linear processing blocks to support linearinput to output transfer function for structured light processingmodes

1 Do not inhibit: all normal video processing blocks enabled, pergoverning command settings

3:1 Spare

31:4 Unused

(1) See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for moredetails.

1.3.1.26 SL Auxiliary Output Multiplexer Setup Command (I2C: x80)


7:0 x00 wStructured Light Auxiliary Output Signal Mux Control Valid selections:(1)

x00 normal

x19 baseline structured light output configuration

31:8 Unused

(1) See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for moredetails.

1.3.1.27 AGC Control: (I2C: x82)


0 b1 IAGC enable (1)

0 - AGC Disabled

1 - AGC Enabled

1 RESERVED (Always write a 1 when the AGC is enabled.)(1) b1 I

2 RESERVED (Always write a 1 when the AGC is enabled.)(1) b1 I

3 Spare b0

31:4 Unused

(1) Should be disabled when using structured light modes. See Using Pico 2.0 Kit for Structured LightApplications, TI literature number DLPA021, for more details.

1.3.1.28 AGC Strength: (I2C: x85)

The AGC adaptively gains up images on a frame-by-frame basis. This AGC Strength command sets themaximum gain that the AGC may apply to any input image frame.


4:0 x10 bAGC Strength

Maximum gain is equal to: ((STRENGTH+1)/32) * 4.0

Valid range is x00 to x1F.

7:5 Spare b000

31:18 Unused


http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021

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C1R1 C2R1 C3R1 C4R1 C5R1 C6R1 C7R1C1R2 C2R2 C3R2 C4R2 C5R2 C6R2 C7R2C1R3 C2R3 C3R3 C4R3 C5R3 C6R3 C7R3

Red

Green

Blue

Cyan

Magenta

Yellow

White

Red

Green

Blue

=


1.3.2 Color Coordinate Adjustment (CCA) Command/Field Definitions

The Color Coordinate Adjustment function allows the color coordinates and color gain to be adjusted forR, G, B, Y, C, M, and W. The format is s1.10 for all coefficients. CCA Disabled passes RGB valuesthrough unchanged.

When enabled:

1.3.2.1 CCA Enable: (I2C: x92)


0 b0 ICCA enable (1)

0 CCA Disabled

1 CCA Enabled

3:1 Spare b000

31:4 Unused

(1) Should be disabled when using structured light modes. See Using Pico 2.0 Kit for Structured LightApplications, TI literature number DLPA021, for more details.

1.3.2.2 CCA C1R1 Coef: (I2C: x93)


11:0 Column 1 row 1 coefficient x400 b

31:12 Unused

1.3.2.3 CCA C1R2 Coef: (I2C: x94)



31:12 Unused

1.3.2.4 CCA C1R3 Coef: (I2C: x95)


11:0 Column 1 row 3 coefficient x000 b31:12 Unused

1.3.2.5 CCA C2R2 Coef: (I2C: x96)



31:12 Unused


http://www.ti.com/lit/pdf/dlpa021http://www.ti.com/lit/pdf/dlpa021

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1.3.2.6 CCA C2R2 Coef: (I2C: x97)



31:12 Unused

1.3.2.7 CCA C2R3 Coef: (I2C: x98)



31:12 Unused

1.3.2.8 CCA C3R1 Coef: (I2C: x99)



31:12 Unused

1.3.2.9 CCA C3R2 Coef: (I2C: x9A)



31:12 Unused

1.3.2.10 CCA C3R3 Coef: (I2C: x9B)



31:12 Unused

1.3.2.11 CCA C4R1 Coef: (I2C: x9C)



31:12 Unused

1.3.2.12 CCA C4R2 Coef: (I2C: x9D)



1.3.2.13 CCA C4R3 Coef: (I2C: x9E)


11:0 Column 4 row 3coefficient x400 b

31:12 Unused



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1.3.2.14 CCA C5R1 Coef: (I2C: x9F)



31:12 Unused

1.3.2.15 CCA C5R2 Coef: (I2C: xA0)



31:12 Unused

1.3.2.16 CCA C5R3 Coef: (I2C: xA1)



31:12 Unused

1.3.2.17 CCA C6R1 Coef: (I2C: xA2)



31:12 Unused

1.3.2.18 CCA C6R2 Coef: (I2C: xA3)



31:12 Unused

1.3.2.19 CCA C6R3 Coef: (I2C: xA4)



31:12 Unused

1.3.2.20 CCA C7R1 Coef: (I2C: xA5)



1.3.2.21 CCA C7R2 Coef: (I2C: xA6)



31:12 Unused



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1.3.2.22 CCA C7R3 Coef: (I2C: xA7)



31:12 Unused

1.3.3 Structured Light Control Command/Field Definitions

The following commands are specifically for use with structured light display modes. See Using Pico 2.0Kit for Structured Light Applications, TI literature number DLPA021, for more details.

1.3.3.1 Structured Light Auxiliary Control Register Command: (I2C: xB2)


7:0 x00 wTiming clock granularityDefines the clock period used for the auxiliary bit pulse width anddelay commands. Period = GRANULARITY * 33.3ns

8 b0 wAuxiliary Internal Bit 4 Edge Select

0 - Falling edge1 - Rising edge

9 b0 wAuxiliary Internal Bit 5 Edge Select

0 - Falling edge

1 - Rising edge

11:10 Reserved b00 w

31:12 Unused

1.3.3.2 SL Auxiliary Internal Bit 0 Control Command : (I2C: xB3)


7:0 x00 wStructured Light Auxiliary Internal Bit 0 Mux Control

x00 normal

x40 baseline structured light configuration

11:8 Reserved x0 w

31:12 Unused




x00 normal


11:8 Reserved x0 w

31:12 Unused




x00 normal


11:8 Reserved x0 w



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31:12 Unused

1.3.3.5 SL Auxiliary Internal Bit 5 Control Command: (I2C: xB8)



x00 normal


11:8 Reserved x0 w

31:12 Unused

1.3.4 LED Color Mask Command/Field Definitions

The following commands allow selection of the LED color enables. This function may be used to changedisplay colors when in monochromatic Display Modes (I2C: x1F). For example, a 100% green displaymode can be switched to 100% red by selecting green on the red LED enable mask.

Note that when using the LED driver circuit included with the Pico Development Kit, setting more than oneLED enable to the same source is not supported and may result in unpredictable behavior.

1.3.4.1 Red LED Enable Mask : (I2C: xBB)


7:0 x08 wRed LED enable mask

Valid selections:

x08 Red LED enable mapped to red data channel

x10 Red LED enable mapped to green data channelx20 Red LED enable mapped to blue data channel

31:8 Unused

1.3.4.2 Green LED Enable Mask : (I2C: xBC)


7:0 x10 wGreen LED enable mask

Valid selections:

x08 Green LED enable mapped to red data channel

x10 Green LED enable mapped to green data channelx20 Green LED enable mapped to blue data channel

31:8 Unused

1.3.4.3 Blue LED Enable Mask: (I2C: xBD)


7:0 x20 wBlue LED enable mask

Valid selections:

x08 Blue LED enable mapped to red data channel

x10 Blue LED enable mapped to green data channelx20 Blue LED enable mapped to blue data channel

31:8 Unused



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1.3.5 Structured Light Control Command/Field Definitions (continued)

The following commands are specifically for use with structured light display modes. See Using Pico 2.0Kit for Structured Light Applications, TI literature number DLPA021, for more details.

1.3.5.1 SL Auxiliary Internal Pattern Sync Control Command: (I2C: xBE)


7:0 x40 wStructured Light Auxiliary Internal Pattern Sync Mux Control

x00 normalx40 baseline structured light configuration

31:8 Unused

1.3.5.2 SL Auxiliary Internal Bit 4 Delay Command: (I2C: xBF)


14:0 x0001 wStructured Light Auxiliary Internal Bit 4 DelaySpecifies how many clocks to delay the output pulse from the edgeselected by "edge select". Actual delay amount is this register

setting plus two clocks. Zero is an invalid setting.

15 Spare b0

31:16 Unused

1.3.5.3 SL Auxiliary Internal Bit 4 Pulse Width Command: (I2C: xC0)


14:0 x0001 wStructured Light Auxiliary Internal Bit 4 Pulse WidthSpecifies how many clocks wide the output pulse will be. Zero isinvalid.

15 Spare b0

31:16 Unused

1.3.5.4 Auxiliary Internal Bit 5 Delay Command: (I2C: xC1)


14:0 x0001 wStructured Light Auxiliary Internal Bit 5 DelaySpecifies how many clocks to delay the output pulse from the edgeselected by "edge select". Actual delay amount is this registersetting plus two clocks. Zero is an invalid setting.

15 Spare b0

31:16 Unused

1.3.5.5 SL Auxiliary Internal Bit 5 Pulse Width Command: (I2C: xC2)


14:0 x0001 wStructured Light Auxiliary Internal Bit 5 Pulse WidthSpecifies how many clocks wide the output pulse will be. Zero isinvalid.

15 Spare b0

31:16 Unused



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1.3.6 Internal Pattern Structured Light Command/Field Definitions

The following commands are specifically for use with internal pattern structured light display modes. SeeUsing Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details.

Up to 32 patterns vertical stripe pattern (selected from a list of 15 options) can be displayed sequentially athigh speeds without supplying any video inputs to the chipset. The predefined list of 15 vertical stripe

patterns are as follows:Pattern Pointer = x0 - all black (or white with inversion bit set):

Pattern Pointer = x1 50% stripe width

Pattern Pointer =x2 256 pixel black stripe width, centered

Pattern Pointer = x3 128 pixel black & white stripe widths

Pattern Pointer = x4 64 pixel




Pattern Pointer = x8 - 4 pixel



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Pattern Pointer = x9 stripe width = two pixels

Pattern Pointer = xA

Pattern Pointer = xB

Pattern Pointer = xC

Pattern Pointer = xD

Pattern Pointer = xE

(Pattern Pointer = xF invalid.)

Synchronization strobes from the chipset mark the display times of these patterns, and can be used forcamera/projector synchronization. See Using Pico 2.0 Kit for Structured Light Applications, TI literaturenumber DLPA021, for more details.

1.3.6.1 Internal Structured Light Configuration Command: (I2C: xD2)


0 b0 wInternal Structured Light Pattern Function Enable

0 - Disable1 Enable

3:1 Spare b000

8:4 x00 wInternal Structured Light Pattern CountNumber of structured light patterns minus one that will be displayedbefore pattern sequence repeats

11:9 Spare b000



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31:12 Unused

1.3.6.2 Internal Structured Light Inversion Mask 1 Command : (I2C: xD3)


7:0 x00 wInternal Structured Light Pattern Inversion Mask 7:0

1 Invert data of pattern corresponding to index number

0 Do not invert

31:8 Unused




1 Invert data of pattern corresponding to index number0 Do not invert

31:8 Unused





31:8 Unused





31:8 Unused

1.3.6.6 Internal Structured Light Pattern Pointer 1 Command : (I2C: xD7)


3:0 Internal Structured Light Pattern Pointer x00 x0 w


31:8 Unused





31:8 Unused



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31:8 Unused

1.3.6.9 Internal Structured Light Pattern Pointer 4 Command : (I2C: xDA)




31:8 Unused

1.3.6.10 Internal Structured Light Pattern Pointer 5 Command : (I2C: xDB)


3:0 x0 wInternal Structured Light Pattern Pointer x08


31:8 Unused

1.3.6.11 Internal Structured Light Pattern Pointer 6 Command: (I2C: xDC)


3:0 x0 wInternal Structured LightPattern Pointer x0A

7:4 Internal Structured Light x0 wPattern Pointer x0B

31:8 Unused

1.3.6.12 Internal Structured Light Pattern Pointer 7 Command: (I2C: xDD)


3:0 Internal Structured Light Pattern Pointer x0C x0 w

7:4 Internal Structured Light Pattern Pointer x0D x0 w

31:8 Unused

1.3.6.13 Internal Structured Light Pattern Pointer 8 Command: (I2C: xDE)


3:0 x0 wInternal Structured Light Pattern Pointer x0E

7:4 Internal Structured Light Pattern Pointer x0F x0 w

31:8 Unused

1.3.6.14 Internal Structured Light Pattern Pointer 9 Command: (I2C: xDF)



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31:8 Unused

1.3.6.15 Internal Structured Light Pattern Pointer 10 Command: (I2C: xE0)




31:8 Unused

1.3.6.16 Internal Structured Light Pattern Pointer 11 Command: (I2C: xE1)



7:4 Internal Structured Light Pattern Pointer x15 x0 w31:8 Unused

1.3.6.17 Internal Structured Light Pattern Pointer 12 Command : (I2C: xE2)




31:8 Unused





31:8 Unused



3:0 x0 wInternal Structured Light Pattern Pointer x1A

7:4 Internal Structured Light Pattern Pointer x1B x0 w

31:8 Unused



3:0 x0 wInternal Structured Light Pattern Pointer x1C

7:4 Internal Structured Light Pattern Pointer x1D x0 w

31:8 Unused



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3:0 x0 wInternal Structured Light Pattern Pointer x1E

7:4 Internal Structured Light Pattern Pointer x1F x0 w

31:8 Unused



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FOR NORMAL IMAGE

Scale factor: Height 1:1Width 1:1

240

320 320

480

Fill with black

Commands:Image resolution QVGA Portrait (Addr x05 = x0)Image rotation No rotation (Addr x07 = x0)

FOR ROTATED IMAGE

Scale factor: Height 1:1.33Width 1:1.50

240

320 320

480

Commands:Image resolution QVGA Portrait (Addr x05 = x0)Image rotation Rotation( 90 degrees) (Addr x07 = x1)


1.3.7 Options for Input Image Resolutions/Orientations and DMD Displayed Images

Figure 1-3. Portrait QVGA to HVGA



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FOR NORMAL IMAGE


320

480 320

480

Fill with black

Commands:Image resolution HVGA Por trait (Addr x05 = x2)Image rotation No rotation (Addr x07 = x0)

FOR ROTATED IMAGE


320

480 320

480

Commands:Image resolution HVGA Portrait (Addr x05 = x2)Image rotation Rotation( 90 degrees) (Addr x07 = x1)


Figure 1-4. Portrait HVGA to HVGA



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FOR NORMAL IMAGE


480

640 320

480

Fill with black

Commands:Image resolution VGA Portrait (Addr x05 = x4)Image rotation No rotation (Addr x07 = x0)

FOR ROTATED IMAGE

Scale factor: Height 1.50:1Width 1.33:1

480

640 320

480

Commands:Image resolution VGA Portrait (Addr x05 = x4)Image rotation Rotation( 90 degrees) (Addr x07 = x1)


Figure 1-5. Portrait VGA to HVGA



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320

240 320

480

Commands:Image resolution QVGA Landscape (Addr x05 = x1)Image rotation No rotation (Addr x07 = x0)


Commands:Image resolution HVGA Landscape (Addr x05 = x3)Image rotation No rotation (Addr x07 = x0)

320

480

320

480


Figure 1-6. Landscape QVGA to HVGA

Figure 1-7. Landscape HVGA to HVGA



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Commands:Image resolution VGA Landscape (Addr x05 = x5)Image rotation No rotation (Addr x07 = x0)

320

480

480

640


Commands:Image resolution NTSC Landscape (Addr x05 = x6)Image rotation No rotation (Addr x07 = x0)

320

480

240

720


Figure 1-8. Landscape VGA to HVGA

Figure 1-9. Landscape NTSC to HVGA

72x240 is the image size output by the TVP5150 video decoder for each 60Hz NTSC field. The image isonly 240 lines tall because every other line is missing due to interlacing. The DLPC100 scales the field tocreate a full frame of data to display on the DMD at a 60Hz frame rate. The scaling operation achieves alow-cost method of deinterlacing.



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Commands:Image resolution PAL/SECAM Landscape (Addr x05 = x8)Image rotation No rotation (Addr x07 = x0)

320

480

288

720


Commands:Image resolution VGA Landscape cropped to HVGA (Addr x05 = x7)Image rotation No rotation (Addr x07 = x0)

320

480

480

640


Figure 1-10. Landscape PAL/SECAM to HVGA

72x288 is the image size output by the TVP5150 video decoder for each 60Hz PAL or SECAM field. Theimage is only 288 lines tall because every other line is missing due to interlacing. The DLPC100 scalesthe field to create a full frame of data to display on the DMD at a 50Hz frame rate. The scaling operationachieves a low-cost method of deinterlacing.

Figure 1-11. Landscape VGA Cropped to HVGA (Not Scaled)

Input pixels within the HVGA input sub-image map one-for-one to pixels on the HVGA DMD. This is usefulfor inputting optical test patterns.



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Powerup and Powerdown Considerations

2.1 Powerup

The Pico Chipset electronics and I2C command processor interface inside the DLPC100 will be initializedand ready to process commands 1.0 seconds after signal PWRGOOD goes high. Detailed power-uptiming is given in the DLPC100 data sheet, TI literature number DLPS019 .

Commands input prior to 1.0 second after PWRGOOD goes high may not be decoded properly.

2.2 Powerdown

No commands are required at power down of the Pico Chipset. The DC power supplies must be turnedoff, and PWRGOOD must be set low, according to the timing in the DLPC100 data sheet.

39DLPU002A February 2010 Revised July 2010 Powerup and Powerdown Considerations

http://www.ti.com/lit/pdf/dlps019http://www.ti.com/lit/pdf/dlps019

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40 Powerup and Powerdown Considerations DLPU002A February 2010 Revised July 2010


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Command Quick Reference

Table 3-1 provides a quick reference summary of all available projector commands.

Table 3-1.

I2C DEFAULT DEFAULTREGISTER (1) SIZE TYPE (2)

ADDRESS VALUE ACTION

x04 Input Source and Interface Mode 16 WR x2 Splash

x05 Input Resolution 16 WR x1 QVGA landsc.

x06 Pixel Format 16 WR x2 RGB888

x07 Input Rotation (for portrait inputs only) 16 WR x0 No rotate

x08 Image Flip Long Axis 16 WR x0 Disabled

x09 Image Flip Short Axis 16 WR x0 Disabled

x0A Aspect Ratio Modification 16 WR x0 3:2 (48x320)

x0B Internal Test Patterns 16 WR x0 Checkerboard

x0C Pixel Interface Clock Edge 16 WR x1 Rising edge

x0D Pixel Interface Sync Polarity 16 WR x4 DATEN high

x0E Red LED Driver Current 16 WR x03FF Min current

x0F Green LED Driver Current 16 WR x03FF Min current

x10 Blue LED Driver Current 16 WR x03FF Min current

x11 Enable Red LED 16 WR x0 Disabled

x12 Enable Green LED 16 WR x0 Disabled

x13 Enable Blue LED 16 WR x0 Disabledx14-1D * RESERVED

x1E Degamma Curve Select 16 WR x0 Enhanced Gr.

x1F Display Mode Select 16 WR x0 R39G48B13

x20-23 * RESERVED

x24 Sync Mode 4 WR x0 Free Run

x25 Splash Image Select 4 WR x1 Logo in Flash

x26 Video/graphics enhancement Enable 4 WR x0 Disabled

x27 VSYNC Delay 15 WR x0000 No delay

x28 * RESERVED

x29 SL Output Display Inhibit 4 WR x1 Not Inhibited

x2A-x3F * RESERVED

x40 Firmware Revision 12 R n/a n/a

x41-x61 * RESERVED

x62 SL Non-Linear Processing Inhibit 4 WR x1 Not Inhibited

x63-x7F * RESERVED

x80 SL Aux Output Mux Setup 8 WR x00 Normal

x81 * RESERVED

x82 AGC Control 3 WR x7 Enabled

(1) RESERVED registers should never be written to.(2) WR type is writeable and data is also readable. R type is read-only. Writes to these fields will have no effect. S type is a

latched status bit. Reading a 1 in this field means that the signal has gone high since the last clear. Writing a 1 to this fieldclears the status bit. * RESERVED registers should never be written to.

41DLPU002A February 2010 Revised July 2010 Command Quick Reference


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www.ti.com

Table 3-1. (continued)



x83-x84 * RESERVED

x85 AGC Strength 5 WR x10 Max gain=2.1

x86-x91 * RESERVEDx92 CCA Enable 1 WR x1 Enabled

x93 CCA Column 1 Row 1 Coefficient 12 WR x400

x94 CCA Column 1 Row 2 Coefficient 12 WR x0C5




x98 CCA Column 2 Row 3 Coefficient 12 WR x0ED


x9A CCA Column 3 Row 2 Coefficient 12 WR x000

x9B CCA Column 3 Row 3 Coefficient 12 WR x400

x9C CCA Column 4 Row 1 Coefficient 12 WR x000

x9D CCA Column 4 Row 2 Coefficient 12 WR x400

x9E CCA Column 4 Row 3 Coefficient 12 WR x400

x9F CCA Column 5 Row 1 Coefficient 12 WR x400

xA0 CCA Column 5 Row 2 Coefficient 12 WR x000








xA6-xB1 * RESERVEDxB2 SL Auxiliary Control Register 8 WR x00 n/a

xB3 SL Aux Input Bit 0 Control 8 WR x00 Normal


xB5-xB6 * RESERVED



xB9-xBA * RESERVED

xBB Red LED Enable Mask 8 WR x08

xBC Green LED Enable Mask 8 WR x10

xBD Blue LED Enable Mask 8 WR x20

xBE SL Aux Internal Pattern Sync Control 8 WR x40 Normal

xBF SL Aux Internal Bit 4 Delay 16 WR x0001 Delay by 3

xC0 SL Aux Internal Bit 4 Pulse Width 16 WR x0001 2 clocks wide

xC1 SL Aux Internal Bit 5 Delay 16 WR x0001 Delay by 3

xC2 SL Aux Internal Bit 5 Pulse Width 16 WR x0001 2 clocks wide

xC1-xD1 * RESERVED

xD2 Internal Structured Light Config 12 WR x000 Disabled

xD3 Internal SL Inversion Mask 1 8 WR x00 No inversion




42 Command Quick Reference DLPU002A February 2010 Revised July 2010


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www.ti.com

Table 3-1. (continued)



xD7 Internal SL Pattern Pointer 1 8 WR x00 Pattern 0

xD8 Internal SL Pattern Pointer 2 8 WR x00 Pattern 0

xD9 Internal SL Pattern Pointer 3 8 WR x00 Pattern 0xDA Internal SL Pattern Pointer 4 8 WR x00 Pattern 0

xDB Internal SL Pattern Pointer 5 8 WR x00 Pattern 0

xDC Internal SL Pattern Pointer 6 8 WR x00 Pattern 0

xDD Internal SL Pattern Pointer 7 8 WR x00 Pattern 0

xDE Internal SL Pattern Pointer 8 8 WR x00 Pattern 0

xDF Internal SL Pattern Pointer 9 8 WR x00 Pattern 0

xE0 Internal SL Pattern Pointer 10 8 WR x00 Pattern 0







xE7-xFF * RESERVED

43DLPU002A February 2010 Revised July 2010 Command Quick Reference


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REVISION HISTORY www.ti.com

REVISION HISTORY

REVISION DATE SECTION(S) COMMENT

* 2/2010 All Initial release

1.3.1.26 Bit(7:0) description correctedA 7/2010

Revision History Added Revision History table

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

44 Revision History DLPU002A February 2010 Revised July 2010


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